1/* $NetBSD: nouveau_nvkm_engine_fifo_dmanv50.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $ */ 2 3/* 4 * Copyright 2012 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Ben Skeggs 25 */ 26#include <sys/cdefs.h> 27__KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_fifo_dmanv50.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $"); 28 29#include "channv50.h" 30 31#include <core/client.h> 32#include <core/ramht.h> 33 34#include <nvif/class.h> 35#include <nvif/cl506e.h> 36#include <nvif/unpack.h> 37 38static int 39nv50_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, 40 void *data, u32 size, struct nvkm_object **pobject) 41{ 42 struct nvkm_object *parent = oclass->parent; 43 union { 44 struct nv50_channel_dma_v0 v0; 45 } *args = data; 46 struct nv50_fifo *fifo = nv50_fifo(base); 47 struct nv50_fifo_chan *chan; 48 int ret = -ENOSYS; 49 50 nvif_ioctl(parent, "create channel dma size %d\n", size); 51 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { 52 nvif_ioctl(parent, "create channel dma vers %d vmm %"PRIx64" " 53 "pushbuf %"PRIx64" offset %016"PRIx64"\n", 54 args->v0.version, args->v0.vmm, args->v0.pushbuf, 55 args->v0.offset); 56 if (!args->v0.pushbuf) 57 return -EINVAL; 58 } else 59 return ret; 60 61 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) 62 return -ENOMEM; 63 *pobject = &chan->base.object; 64 65 ret = nv50_fifo_chan_ctor(fifo, args->v0.vmm, args->v0.pushbuf, 66 oclass, chan); 67 if (ret) 68 return ret; 69 70 args->v0.chid = chan->base.chid; 71 72 nvkm_kmap(chan->ramfc); 73 nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset)); 74 nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset)); 75 nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset)); 76 nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset)); 77 nvkm_wo32(chan->ramfc, 0x3c, 0x003f6078); 78 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); 79 nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); 80 nvkm_wo32(chan->ramfc, 0x4c, 0xffffffff); 81 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); 82 nvkm_wo32(chan->ramfc, 0x78, 0x00000000); 83 nvkm_wo32(chan->ramfc, 0x7c, 0x30000001); 84 nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | 85 (4 << 24) /* SEARCH_FULL */ | 86 (chan->ramht->gpuobj->node->offset >> 4)); 87 nvkm_done(chan->ramfc); 88 return 0; 89} 90 91const struct nvkm_fifo_chan_oclass 92nv50_fifo_dma_oclass = { 93 .base.oclass = NV50_CHANNEL_DMA, 94 .base.minver = 0, 95 .base.maxver = 0, 96 .ctor = nv50_fifo_dma_new, 97}; 98