1/*	$NetBSD: nouveau_nvkm_engine_disp_vga.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $	*/
2
3/*
4 * Copyright 2012 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs
25 */
26#include <sys/cdefs.h>
27__KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_disp_vga.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $");
28
29#include <subdev/vga.h>
30
31u8
32nvkm_rdport(struct nvkm_device *device, int head, u16 port)
33{
34	if (device->card_type >= NV_50)
35		return nvkm_rd08(device, 0x601000 + port);
36
37	if (port == 0x03c0 || port == 0x03c1 ||	/* AR */
38	    port == 0x03c2 || port == 0x03da ||	/* INP0 */
39	    port == 0x03d4 || port == 0x03d5)	/* CR */
40		return nvkm_rd08(device, 0x601000 + (head * 0x2000) + port);
41
42	if (port == 0x03c2 || port == 0x03cc ||	/* MISC */
43	    port == 0x03c4 || port == 0x03c5 ||	/* SR */
44	    port == 0x03ce || port == 0x03cf) {	/* GR */
45		if (device->card_type < NV_40)
46			head = 0; /* CR44 selects head */
47		return nvkm_rd08(device, 0x0c0000 + (head * 0x2000) + port);
48	}
49
50	return 0x00;
51}
52
53void
54nvkm_wrport(struct nvkm_device *device, int head, u16 port, u8 data)
55{
56	if (device->card_type >= NV_50)
57		nvkm_wr08(device, 0x601000 + port, data);
58	else
59	if (port == 0x03c0 || port == 0x03c1 ||	/* AR */
60	    port == 0x03c2 || port == 0x03da ||	/* INP0 */
61	    port == 0x03d4 || port == 0x03d5)	/* CR */
62		nvkm_wr08(device, 0x601000 + (head * 0x2000) + port, data);
63	else
64	if (port == 0x03c2 || port == 0x03cc ||	/* MISC */
65	    port == 0x03c4 || port == 0x03c5 ||	/* SR */
66	    port == 0x03ce || port == 0x03cf) {	/* GR */
67		if (device->card_type < NV_40)
68			head = 0; /* CR44 selects head */
69		nvkm_wr08(device, 0x0c0000 + (head * 0x2000) + port, data);
70	}
71}
72
73u8
74nvkm_rdvgas(struct nvkm_device *device, int head, u8 index)
75{
76	nvkm_wrport(device, head, 0x03c4, index);
77	return nvkm_rdport(device, head, 0x03c5);
78}
79
80void
81nvkm_wrvgas(struct nvkm_device *device, int head, u8 index, u8 value)
82{
83	nvkm_wrport(device, head, 0x03c4, index);
84	nvkm_wrport(device, head, 0x03c5, value);
85}
86
87u8
88nvkm_rdvgag(struct nvkm_device *device, int head, u8 index)
89{
90	nvkm_wrport(device, head, 0x03ce, index);
91	return nvkm_rdport(device, head, 0x03cf);
92}
93
94void
95nvkm_wrvgag(struct nvkm_device *device, int head, u8 index, u8 value)
96{
97	nvkm_wrport(device, head, 0x03ce, index);
98	nvkm_wrport(device, head, 0x03cf, value);
99}
100
101u8
102nvkm_rdvgac(struct nvkm_device *device, int head, u8 index)
103{
104	nvkm_wrport(device, head, 0x03d4, index);
105	return nvkm_rdport(device, head, 0x03d5);
106}
107
108void
109nvkm_wrvgac(struct nvkm_device *device, int head, u8 index, u8 value)
110{
111	nvkm_wrport(device, head, 0x03d4, index);
112	nvkm_wrport(device, head, 0x03d5, value);
113}
114
115u8
116nvkm_rdvgai(struct nvkm_device *device, int head, u16 port, u8 index)
117{
118	if (port == 0x03c4) return nvkm_rdvgas(device, head, index);
119	if (port == 0x03ce) return nvkm_rdvgag(device, head, index);
120	if (port == 0x03d4) return nvkm_rdvgac(device, head, index);
121	return 0x00;
122}
123
124void
125nvkm_wrvgai(struct nvkm_device *device, int head, u16 port, u8 index, u8 value)
126{
127	if      (port == 0x03c4) nvkm_wrvgas(device, head, index, value);
128	else if (port == 0x03ce) nvkm_wrvgag(device, head, index, value);
129	else if (port == 0x03d4) nvkm_wrvgac(device, head, index, value);
130}
131
132bool
133nvkm_lockvgac(struct nvkm_device *device, bool lock)
134{
135	bool locked = !nvkm_rdvgac(device, 0, 0x1f);
136	u8 data = lock ? 0x99 : 0x57;
137	if (device->card_type < NV_50)
138		nvkm_wrvgac(device, 0, 0x1f, data);
139	else
140		nvkm_wrvgac(device, 0, 0x3f, data);
141	if (device->chipset == 0x11) {
142		if (!(nvkm_rd32(device, 0x001084) & 0x10000000))
143			nvkm_wrvgac(device, 1, 0x1f, data);
144	}
145	return locked;
146}
147
148/* CR44 takes values 0 (head A), 3 (head B) and 4 (heads tied)
149 * it affects only the 8 bit vga io regs, which we access using mmio at
150 * 0xc{0,2}3c*, 0x60{1,3}3*, and 0x68{1,3}3d*
151 * in general, the set value of cr44 does not matter: reg access works as
152 * expected and values can be set for the appropriate head by using a 0x2000
153 * offset as required
154 * however:
155 * a) pre nv40, the head B range of PRMVIO regs at 0xc23c* was not exposed and
156 *    cr44 must be set to 0 or 3 for accessing values on the correct head
157 *    through the common 0xc03c* addresses
158 * b) in tied mode (4) head B is programmed to the values set on head A, and
159 *    access using the head B addresses can have strange results, ergo we leave
160 *    tied mode in init once we know to what cr44 should be restored on exit
161 *
162 * the owner parameter is slightly abused:
163 * 0 and 1 are treated as head values and so the set value is (owner * 3)
164 * other values are treated as literal values to set
165 */
166u8
167nvkm_rdvgaowner(struct nvkm_device *device)
168{
169	if (device->card_type < NV_50) {
170		if (device->chipset == 0x11) {
171			u32 tied = nvkm_rd32(device, 0x001084) & 0x10000000;
172			if (tied == 0) {
173				u8 slA = nvkm_rdvgac(device, 0, 0x28) & 0x80;
174				u8 tvA = nvkm_rdvgac(device, 0, 0x33) & 0x01;
175				u8 slB = nvkm_rdvgac(device, 1, 0x28) & 0x80;
176				u8 tvB = nvkm_rdvgac(device, 1, 0x33) & 0x01;
177				if (slA && !tvA) return 0x00;
178				if (slB && !tvB) return 0x03;
179				if (slA) return 0x00;
180				if (slB) return 0x03;
181				return 0x00;
182			}
183			return 0x04;
184		}
185
186		return nvkm_rdvgac(device, 0, 0x44);
187	}
188
189	return 0x00;
190}
191
192void
193nvkm_wrvgaowner(struct nvkm_device *device, u8 select)
194{
195	if (device->card_type < NV_50) {
196		u8 owner = (select == 1) ? 3 : select;
197		if (device->chipset == 0x11) {
198			/* workaround hw lockup bug */
199			nvkm_rdvgac(device, 0, 0x1f);
200			nvkm_rdvgac(device, 1, 0x1f);
201		}
202
203		nvkm_wrvgac(device, 0, 0x44, owner);
204
205		if (device->chipset == 0x11) {
206			nvkm_wrvgac(device, 0, 0x2e, owner);
207			nvkm_wrvgac(device, 0, 0x2e, owner);
208		}
209	}
210}
211