1/*	$NetBSD: nouveau_nvkm_engine_disp_coregf119.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $	*/
2
3/*
4 * Copyright 2012 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs
25 */
26#include <sys/cdefs.h>
27__KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_disp_coregf119.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $");
28
29#include "channv50.h"
30
31#include <subdev/timer.h>
32
33const struct nv50_disp_mthd_list
34gf119_disp_core_mthd_base = {
35	.mthd = 0x0000,
36	.addr = 0x000000,
37	.data = {
38		{ 0x0080, 0x660080 },
39		{ 0x0084, 0x660084 },
40		{ 0x0088, 0x660088 },
41		{ 0x008c, 0x000000 },
42		{}
43	}
44};
45
46const struct nv50_disp_mthd_list
47gf119_disp_core_mthd_dac = {
48	.mthd = 0x0020,
49	.addr = 0x000020,
50	.data = {
51		{ 0x0180, 0x660180 },
52		{ 0x0184, 0x660184 },
53		{ 0x0188, 0x660188 },
54		{ 0x0190, 0x660190 },
55		{}
56	}
57};
58
59const struct nv50_disp_mthd_list
60gf119_disp_core_mthd_sor = {
61	.mthd = 0x0020,
62	.addr = 0x000020,
63	.data = {
64		{ 0x0200, 0x660200 },
65		{ 0x0204, 0x660204 },
66		{ 0x0208, 0x660208 },
67		{ 0x0210, 0x660210 },
68		{}
69	}
70};
71
72const struct nv50_disp_mthd_list
73gf119_disp_core_mthd_pior = {
74	.mthd = 0x0020,
75	.addr = 0x000020,
76	.data = {
77		{ 0x0300, 0x660300 },
78		{ 0x0304, 0x660304 },
79		{ 0x0308, 0x660308 },
80		{ 0x0310, 0x660310 },
81		{}
82	}
83};
84
85static const struct nv50_disp_mthd_list
86gf119_disp_core_mthd_head = {
87	.mthd = 0x0300,
88	.addr = 0x000300,
89	.data = {
90		{ 0x0400, 0x660400 },
91		{ 0x0404, 0x660404 },
92		{ 0x0408, 0x660408 },
93		{ 0x040c, 0x66040c },
94		{ 0x0410, 0x660410 },
95		{ 0x0414, 0x660414 },
96		{ 0x0418, 0x660418 },
97		{ 0x041c, 0x66041c },
98		{ 0x0420, 0x660420 },
99		{ 0x0424, 0x660424 },
100		{ 0x0428, 0x660428 },
101		{ 0x042c, 0x66042c },
102		{ 0x0430, 0x660430 },
103		{ 0x0434, 0x660434 },
104		{ 0x0438, 0x660438 },
105		{ 0x0440, 0x660440 },
106		{ 0x0444, 0x660444 },
107		{ 0x0448, 0x660448 },
108		{ 0x044c, 0x66044c },
109		{ 0x0450, 0x660450 },
110		{ 0x0454, 0x660454 },
111		{ 0x0458, 0x660458 },
112		{ 0x045c, 0x66045c },
113		{ 0x0460, 0x660460 },
114		{ 0x0468, 0x660468 },
115		{ 0x046c, 0x66046c },
116		{ 0x0470, 0x660470 },
117		{ 0x0474, 0x660474 },
118		{ 0x0480, 0x660480 },
119		{ 0x0484, 0x660484 },
120		{ 0x048c, 0x66048c },
121		{ 0x0490, 0x660490 },
122		{ 0x0494, 0x660494 },
123		{ 0x0498, 0x660498 },
124		{ 0x04b0, 0x6604b0 },
125		{ 0x04b8, 0x6604b8 },
126		{ 0x04bc, 0x6604bc },
127		{ 0x04c0, 0x6604c0 },
128		{ 0x04c4, 0x6604c4 },
129		{ 0x04c8, 0x6604c8 },
130		{ 0x04d0, 0x6604d0 },
131		{ 0x04d4, 0x6604d4 },
132		{ 0x04e0, 0x6604e0 },
133		{ 0x04e4, 0x6604e4 },
134		{ 0x04e8, 0x6604e8 },
135		{ 0x04ec, 0x6604ec },
136		{ 0x04f0, 0x6604f0 },
137		{ 0x04f4, 0x6604f4 },
138		{ 0x04f8, 0x6604f8 },
139		{ 0x04fc, 0x6604fc },
140		{ 0x0500, 0x660500 },
141		{ 0x0504, 0x660504 },
142		{ 0x0508, 0x660508 },
143		{ 0x050c, 0x66050c },
144		{ 0x0510, 0x660510 },
145		{ 0x0514, 0x660514 },
146		{ 0x0518, 0x660518 },
147		{ 0x051c, 0x66051c },
148		{ 0x052c, 0x66052c },
149		{ 0x0530, 0x660530 },
150		{ 0x054c, 0x66054c },
151		{ 0x0550, 0x660550 },
152		{ 0x0554, 0x660554 },
153		{ 0x0558, 0x660558 },
154		{ 0x055c, 0x66055c },
155		{}
156	}
157};
158
159static const struct nv50_disp_chan_mthd
160gf119_disp_core_mthd = {
161	.name = "Core",
162	.addr = 0x000000,
163	.prev = -0x020000,
164	.data = {
165		{ "Global", 1, &gf119_disp_core_mthd_base },
166		{    "DAC", 3, &gf119_disp_core_mthd_dac  },
167		{    "SOR", 8, &gf119_disp_core_mthd_sor  },
168		{   "PIOR", 4, &gf119_disp_core_mthd_pior },
169		{   "HEAD", 4, &gf119_disp_core_mthd_head },
170		{}
171	}
172};
173
174void
175gf119_disp_core_fini(struct nv50_disp_chan *chan)
176{
177	struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
178	struct nvkm_device *device = subdev->device;
179
180	/* deactivate channel */
181	nvkm_mask(device, 0x610490, 0x00000010, 0x00000000);
182	nvkm_mask(device, 0x610490, 0x00000003, 0x00000000);
183	if (nvkm_msec(device, 2000,
184		if (!(nvkm_rd32(device, 0x610490) & 0x001e0000))
185			break;
186	) < 0) {
187		nvkm_error(subdev, "core fini: %08x\n",
188			   nvkm_rd32(device, 0x610490));
189	}
190}
191
192static int
193gf119_disp_core_init(struct nv50_disp_chan *chan)
194{
195	struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
196	struct nvkm_device *device = subdev->device;
197
198	/* initialise channel for dma command submission */
199	nvkm_wr32(device, 0x610494, chan->push);
200	nvkm_wr32(device, 0x610498, 0x00010000);
201	nvkm_wr32(device, 0x61049c, 0x00000001);
202	nvkm_mask(device, 0x610490, 0x00000010, 0x00000010);
203	nvkm_wr32(device, 0x640000, 0x00000000);
204	nvkm_wr32(device, 0x610490, 0x01000013);
205
206	/* wait for it to go inactive */
207	if (nvkm_msec(device, 2000,
208		if (!(nvkm_rd32(device, 0x610490) & 0x80000000))
209			break;
210	) < 0) {
211		nvkm_error(subdev, "core init: %08x\n",
212			   nvkm_rd32(device, 0x610490));
213		return -EBUSY;
214	}
215
216	return 0;
217}
218
219const struct nv50_disp_chan_func
220gf119_disp_core_func = {
221	.init = gf119_disp_core_init,
222	.fini = gf119_disp_core_fini,
223	.intr = gf119_disp_chan_intr,
224	.user = nv50_disp_chan_user,
225	.bind = gf119_disp_dmac_bind,
226};
227
228int
229gf119_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
230		    struct nv50_disp *disp, struct nvkm_object **pobject)
231{
232	return nv50_disp_core_new_(&gf119_disp_core_func, &gf119_disp_core_mthd,
233				   disp, 0, oclass, argv, argc, pobject);
234}
235