1/* $NetBSD: nouveau_reg.h,v 1.3 2021/12/18 23:45:32 riastradh Exp $ */ 2 3/* SPDX-License-Identifier: MIT */ 4 5#define NV04_PFB_BOOT_0 0x00100000 6# define NV04_PFB_BOOT_0_RAM_AMOUNT 0x00000003 7# define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000 8# define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001 9# define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002 10# define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003 11# define NV04_PFB_BOOT_0_RAM_WIDTH_128 0x00000004 12# define NV04_PFB_BOOT_0_RAM_TYPE 0x00000028 13# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x00000000 14# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT 0x00000008 15# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK 0x00000010 16# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT 0x00000018 17# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT 0x00000020 18# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16 0x00000028 19# define NV04_PFB_BOOT_0_UMA_ENABLE 0x00000100 20# define NV04_PFB_BOOT_0_UMA_SIZE 0x0000f000 21#define NV04_PFB_DEBUG_0 0x00100080 22# define NV04_PFB_DEBUG_0_PAGE_MODE 0x00000001 23# define NV04_PFB_DEBUG_0_REFRESH_OFF 0x00000010 24# define NV04_PFB_DEBUG_0_REFRESH_COUNTX64 0x00003f00 25# define NV04_PFB_DEBUG_0_REFRESH_SLOW_CLK 0x00004000 26# define NV04_PFB_DEBUG_0_SAFE_MODE 0x00008000 27# define NV04_PFB_DEBUG_0_ALOM_ENABLE 0x00010000 28# define NV04_PFB_DEBUG_0_CASOE 0x00100000 29# define NV04_PFB_DEBUG_0_CKE_INVERT 0x10000000 30# define NV04_PFB_DEBUG_0_REFINC 0x20000000 31# define NV04_PFB_DEBUG_0_SAVE_POWER_OFF 0x40000000 32#define NV04_PFB_CFG0 0x00100200 33# define NV04_PFB_CFG0_SCRAMBLE 0x20000000 34#define NV04_PFB_CFG1 0x00100204 35#define NV04_PFB_FIFO_DATA 0x0010020c 36# define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK 0xfff00000 37# define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_SHIFT 20 38#define NV10_PFB_REFCTRL 0x00100210 39# define NV10_PFB_REFCTRL_VALID_1 (1 << 31) 40#define NV04_PFB_PAD 0x0010021c 41# define NV04_PFB_PAD_CKE_NORMAL (1 << 0) 42#define NV10_PFB_TILE(i) (0x00100240 + (i*16)) 43#define NV10_PFB_TILE__SIZE 8 44#define NV10_PFB_TLIMIT(i) (0x00100244 + (i*16)) 45#define NV10_PFB_TSIZE(i) (0x00100248 + (i*16)) 46#define NV10_PFB_TSTATUS(i) (0x0010024c + (i*16)) 47#define NV04_PFB_REF 0x001002d0 48# define NV04_PFB_REF_CMD_REFRESH (1 << 0) 49#define NV04_PFB_PRE 0x001002d4 50# define NV04_PFB_PRE_CMD_PRECHARGE (1 << 0) 51#define NV20_PFB_ZCOMP(i) (0x00100300 + 4*(i)) 52# define NV20_PFB_ZCOMP_MODE_32 (4 << 24) 53# define NV20_PFB_ZCOMP_EN (1 << 31) 54# define NV25_PFB_ZCOMP_MODE_16 (1 << 20) 55# define NV25_PFB_ZCOMP_MODE_32 (2 << 20) 56#define NV10_PFB_CLOSE_PAGE2 0x0010033c 57#define NV04_PFB_SCRAMBLE(i) (0x00100400 + 4 * (i)) 58#define NV40_PFB_TILE(i) (0x00100600 + (i*16)) 59#define NV40_PFB_TILE__SIZE_0 12 60#define NV40_PFB_TILE__SIZE_1 15 61#define NV40_PFB_TLIMIT(i) (0x00100604 + (i*16)) 62#define NV40_PFB_TSIZE(i) (0x00100608 + (i*16)) 63#define NV40_PFB_TSTATUS(i) (0x0010060c + (i*16)) 64#define NV40_PFB_UNK_800 0x00100800 65 66#define NV_PEXTDEV_BOOT_0 0x00101000 67#define NV_PEXTDEV_BOOT_0_RAMCFG 0x0000003c 68# define NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT (8 << 12) 69#define NV_PEXTDEV_BOOT_3 0x0010100c 70 71#define NV_RAMIN 0x00700000 72 73#define NV_RAMHT_HANDLE_OFFSET 0 74#define NV_RAMHT_CONTEXT_OFFSET 4 75# define NV_RAMHT_CONTEXT_VALID (1<<31) 76# define NV_RAMHT_CONTEXT_CHANNEL_SHIFT 24 77# define NV_RAMHT_CONTEXT_ENGINE_SHIFT 16 78# define NV_RAMHT_CONTEXT_ENGINE_SW 0 79# define NV_RAMHT_CONTEXT_ENGINE_GRAPHICS 1 80# define NV_RAMHT_CONTEXT_INSTANCE_SHIFT 0 81# define NV40_RAMHT_CONTEXT_CHANNEL_SHIFT 23 82# define NV40_RAMHT_CONTEXT_ENGINE_SHIFT 20 83# define NV40_RAMHT_CONTEXT_INSTANCE_SHIFT 0 84 85/* Some object classes we care about in the drm */ 86#define NV_CLASS_DMA_FROM_MEMORY 0x00000002 87#define NV_CLASS_DMA_TO_MEMORY 0x00000003 88#define NV_CLASS_NULL 0x00000030 89#define NV_CLASS_DMA_IN_MEMORY 0x0000003D 90 91#define NV03_USER(i) (0x00800000+(i*NV03_USER_SIZE)) 92#define NV03_USER__SIZE 16 93#define NV10_USER__SIZE 32 94#define NV03_USER_SIZE 0x00010000 95#define NV03_USER_DMA_PUT(i) (0x00800040+(i*NV03_USER_SIZE)) 96#define NV03_USER_DMA_PUT__SIZE 16 97#define NV10_USER_DMA_PUT__SIZE 32 98#define NV03_USER_DMA_GET(i) (0x00800044+(i*NV03_USER_SIZE)) 99#define NV03_USER_DMA_GET__SIZE 16 100#define NV10_USER_DMA_GET__SIZE 32 101#define NV03_USER_REF_CNT(i) (0x00800048+(i*NV03_USER_SIZE)) 102#define NV03_USER_REF_CNT__SIZE 16 103#define NV10_USER_REF_CNT__SIZE 32 104 105#define NV40_USER(i) (0x00c00000+(i*NV40_USER_SIZE)) 106#define NV40_USER_SIZE 0x00001000 107#define NV40_USER_DMA_PUT(i) (0x00c00040+(i*NV40_USER_SIZE)) 108#define NV40_USER_DMA_PUT__SIZE 32 109#define NV40_USER_DMA_GET(i) (0x00c00044+(i*NV40_USER_SIZE)) 110#define NV40_USER_DMA_GET__SIZE 32 111#define NV40_USER_REF_CNT(i) (0x00c00048+(i*NV40_USER_SIZE)) 112#define NV40_USER_REF_CNT__SIZE 32 113 114#define NV50_USER(i) (0x00c00000+(i*NV50_USER_SIZE)) 115#define NV50_USER_SIZE 0x00002000 116#define NV50_USER_DMA_PUT(i) (0x00c00040+(i*NV50_USER_SIZE)) 117#define NV50_USER_DMA_PUT__SIZE 128 118#define NV50_USER_DMA_GET(i) (0x00c00044+(i*NV50_USER_SIZE)) 119#define NV50_USER_DMA_GET__SIZE 128 120#define NV50_USER_REF_CNT(i) (0x00c00048+(i*NV50_USER_SIZE)) 121#define NV50_USER_REF_CNT__SIZE 128 122 123#define NV03_FIFO_SIZE 0x8000UL 124 125#define NV03_PMC_BOOT_0 0x00000000 126#define NV03_PMC_BOOT_1 0x00000004 127#define NV03_PMC_INTR_0 0x00000100 128# define NV_PMC_INTR_0_PFIFO_PENDING (1<<8) 129# define NV_PMC_INTR_0_PGRAPH_PENDING (1<<12) 130# define NV_PMC_INTR_0_NV50_I2C_PENDING (1<<21) 131# define NV_PMC_INTR_0_CRTC0_PENDING (1<<24) 132# define NV_PMC_INTR_0_CRTC1_PENDING (1<<25) 133# define NV_PMC_INTR_0_NV50_DISPLAY_PENDING (1<<26) 134# define NV_PMC_INTR_0_CRTCn_PENDING (3<<24) 135#define NV03_PMC_INTR_EN_0 0x00000140 136# define NV_PMC_INTR_EN_0_MASTER_ENABLE (1<<0) 137#define NV03_PMC_ENABLE 0x00000200 138# define NV_PMC_ENABLE_PFIFO (1<<8) 139# define NV_PMC_ENABLE_PGRAPH (1<<12) 140/* Disabling the below bit breaks newer (G7X only?) mobile chipsets, 141 * the card will hang early on in the X init process. 142 */ 143# define NV_PMC_ENABLE_UNK13 (1<<13) 144#define NV40_PMC_GRAPH_UNITS 0x00001540 145#define NV40_PMC_BACKLIGHT 0x000015f0 146# define NV40_PMC_BACKLIGHT_MASK 0x001f0000 147#define NV40_PMC_1700 0x00001700 148#define NV40_PMC_1704 0x00001704 149#define NV40_PMC_1708 0x00001708 150#define NV40_PMC_170C 0x0000170C 151 152/* probably PMC ? */ 153#define NV50_PUNK_BAR0_PRAMIN 0x00001700 154#define NV50_PUNK_BAR_CFG_BASE 0x00001704 155#define NV50_PUNK_BAR_CFG_BASE_VALID (1<<30) 156#define NV50_PUNK_BAR1_CTXDMA 0x00001708 157#define NV50_PUNK_BAR1_CTXDMA_VALID (1<<31) 158#define NV50_PUNK_BAR3_CTXDMA 0x0000170C 159#define NV50_PUNK_BAR3_CTXDMA_VALID (1<<31) 160#define NV50_PUNK_UNK1710 0x00001710 161 162#define NV04_PBUS_PCI_NV_1 0x00001804 163#define NV04_PBUS_PCI_NV_19 0x0000184C 164#define NV04_PBUS_PCI_NV_20 0x00001850 165# define NV04_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED (0 << 0) 166# define NV04_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED (1 << 0) 167 168#define NV04_PTIMER_INTR_0 0x00009100 169#define NV04_PTIMER_INTR_EN_0 0x00009140 170#define NV04_PTIMER_NUMERATOR 0x00009200 171#define NV04_PTIMER_DENOMINATOR 0x00009210 172#define NV04_PTIMER_TIME_0 0x00009400 173#define NV04_PTIMER_TIME_1 0x00009410 174#define NV04_PTIMER_ALARM_0 0x00009420 175 176#define NV04_PGRAPH_DEBUG_0 0x00400080 177#define NV04_PGRAPH_DEBUG_1 0x00400084 178#define NV04_PGRAPH_DEBUG_2 0x00400088 179#define NV04_PGRAPH_DEBUG_3 0x0040008c 180#define NV10_PGRAPH_DEBUG_4 0x00400090 181#define NV03_PGRAPH_INTR 0x00400100 182#define NV03_PGRAPH_NSTATUS 0x00400104 183# define NV04_PGRAPH_NSTATUS_STATE_IN_USE (1<<11) 184# define NV04_PGRAPH_NSTATUS_INVALID_STATE (1<<12) 185# define NV04_PGRAPH_NSTATUS_BAD_ARGUMENT (1<<13) 186# define NV04_PGRAPH_NSTATUS_PROTECTION_FAULT (1<<14) 187# define NV10_PGRAPH_NSTATUS_STATE_IN_USE (1<<23) 188# define NV10_PGRAPH_NSTATUS_INVALID_STATE (1<<24) 189# define NV10_PGRAPH_NSTATUS_BAD_ARGUMENT (1<<25) 190# define NV10_PGRAPH_NSTATUS_PROTECTION_FAULT (1<<26) 191#define NV03_PGRAPH_NSOURCE 0x00400108 192# define NV03_PGRAPH_NSOURCE_NOTIFICATION (1<<0) 193# define NV03_PGRAPH_NSOURCE_DATA_ERROR (1<<1) 194# define NV03_PGRAPH_NSOURCE_PROTECTION_ERROR (1<<2) 195# define NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION (1<<3) 196# define NV03_PGRAPH_NSOURCE_LIMIT_COLOR (1<<4) 197# define NV03_PGRAPH_NSOURCE_LIMIT_ZETA (1<<5) 198# define NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD (1<<6) 199# define NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION (1<<7) 200# define NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION (1<<8) 201# define NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION (1<<9) 202# define NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION (1<<10) 203# define NV03_PGRAPH_NSOURCE_STATE_INVALID (1<<11) 204# define NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY (1<<12) 205# define NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE (1<<13) 206# define NV03_PGRAPH_NSOURCE_METHOD_CNT (1<<14) 207# define NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION (1<<15) 208# define NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION (1<<16) 209# define NV03_PGRAPH_NSOURCE_DMA_WIDTH_A (1<<17) 210# define NV03_PGRAPH_NSOURCE_DMA_WIDTH_B (1<<18) 211#define NV03_PGRAPH_INTR_EN 0x00400140 212#define NV40_PGRAPH_INTR_EN 0x0040013C 213# define NV_PGRAPH_INTR_NOTIFY (1<<0) 214# define NV_PGRAPH_INTR_MISSING_HW (1<<4) 215# define NV_PGRAPH_INTR_CONTEXT_SWITCH (1<<12) 216# define NV_PGRAPH_INTR_BUFFER_NOTIFY (1<<16) 217# define NV_PGRAPH_INTR_ERROR (1<<20) 218#define NV10_PGRAPH_CTX_CONTROL 0x00400144 219#define NV10_PGRAPH_CTX_USER 0x00400148 220#define NV10_PGRAPH_CTX_SWITCH(i) (0x0040014C + 0x4*(i)) 221#define NV04_PGRAPH_CTX_SWITCH1 0x00400160 222#define NV10_PGRAPH_CTX_CACHE(i, j) (0x00400160 \ 223 + 0x4*(i) + 0x20*(j)) 224#define NV04_PGRAPH_CTX_SWITCH2 0x00400164 225#define NV04_PGRAPH_CTX_SWITCH3 0x00400168 226#define NV04_PGRAPH_CTX_SWITCH4 0x0040016C 227#define NV04_PGRAPH_CTX_CONTROL 0x00400170 228#define NV04_PGRAPH_CTX_USER 0x00400174 229#define NV04_PGRAPH_CTX_CACHE1 0x00400180 230#define NV03_PGRAPH_CTX_CONTROL 0x00400190 231#define NV03_PGRAPH_CTX_USER 0x00400194 232#define NV04_PGRAPH_CTX_CACHE2 0x004001A0 233#define NV04_PGRAPH_CTX_CACHE3 0x004001C0 234#define NV04_PGRAPH_CTX_CACHE4 0x004001E0 235#define NV40_PGRAPH_CTXCTL_0304 0x00400304 236#define NV40_PGRAPH_CTXCTL_0304_XFER_CTX 0x00000001 237#define NV40_PGRAPH_CTXCTL_UCODE_STAT 0x00400308 238#define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_MASK 0xff000000 239#define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT 24 240#define NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK 0x00ffffff 241#define NV40_PGRAPH_CTXCTL_0310 0x00400310 242#define NV40_PGRAPH_CTXCTL_0310_XFER_SAVE 0x00000020 243#define NV40_PGRAPH_CTXCTL_0310_XFER_LOAD 0x00000040 244#define NV40_PGRAPH_CTXCTL_030C 0x0040030c 245#define NV40_PGRAPH_CTXCTL_UCODE_INDEX 0x00400324 246#define NV40_PGRAPH_CTXCTL_UCODE_DATA 0x00400328 247#define NV40_PGRAPH_CTXCTL_CUR 0x0040032c 248#define NV40_PGRAPH_CTXCTL_CUR_LOADED 0x01000000 249#define NV40_PGRAPH_CTXCTL_CUR_INSTANCE 0x000FFFFF 250#define NV40_PGRAPH_CTXCTL_NEXT 0x00400330 251#define NV40_PGRAPH_CTXCTL_NEXT_INSTANCE 0x000fffff 252#define NV50_PGRAPH_CTXCTL_CUR 0x0040032c 253#define NV50_PGRAPH_CTXCTL_CUR_LOADED 0x80000000 254#define NV50_PGRAPH_CTXCTL_CUR_INSTANCE 0x00ffffff 255#define NV50_PGRAPH_CTXCTL_NEXT 0x00400330 256#define NV50_PGRAPH_CTXCTL_NEXT_INSTANCE 0x00ffffff 257#define NV03_PGRAPH_ABS_X_RAM 0x00400400 258#define NV03_PGRAPH_ABS_Y_RAM 0x00400480 259#define NV03_PGRAPH_X_MISC 0x00400500 260#define NV03_PGRAPH_Y_MISC 0x00400504 261#define NV04_PGRAPH_VALID1 0x00400508 262#define NV04_PGRAPH_SOURCE_COLOR 0x0040050C 263#define NV04_PGRAPH_MISC24_0 0x00400510 264#define NV03_PGRAPH_XY_LOGIC_MISC0 0x00400514 265#define NV03_PGRAPH_XY_LOGIC_MISC1 0x00400518 266#define NV03_PGRAPH_XY_LOGIC_MISC2 0x0040051C 267#define NV03_PGRAPH_XY_LOGIC_MISC3 0x00400520 268#define NV03_PGRAPH_CLIPX_0 0x00400524 269#define NV03_PGRAPH_CLIPX_1 0x00400528 270#define NV03_PGRAPH_CLIPY_0 0x0040052C 271#define NV03_PGRAPH_CLIPY_1 0x00400530 272#define NV03_PGRAPH_ABS_ICLIP_XMAX 0x00400534 273#define NV03_PGRAPH_ABS_ICLIP_YMAX 0x00400538 274#define NV03_PGRAPH_ABS_UCLIP_XMIN 0x0040053C 275#define NV03_PGRAPH_ABS_UCLIP_YMIN 0x00400540 276#define NV03_PGRAPH_ABS_UCLIP_XMAX 0x00400544 277#define NV03_PGRAPH_ABS_UCLIP_YMAX 0x00400548 278#define NV03_PGRAPH_ABS_UCLIPA_XMIN 0x00400560 279#define NV03_PGRAPH_ABS_UCLIPA_YMIN 0x00400564 280#define NV03_PGRAPH_ABS_UCLIPA_XMAX 0x00400568 281#define NV03_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C 282#define NV04_PGRAPH_MISC24_1 0x00400570 283#define NV04_PGRAPH_MISC24_2 0x00400574 284#define NV04_PGRAPH_VALID2 0x00400578 285#define NV04_PGRAPH_PASSTHRU_0 0x0040057C 286#define NV04_PGRAPH_PASSTHRU_1 0x00400580 287#define NV04_PGRAPH_PASSTHRU_2 0x00400584 288#define NV10_PGRAPH_DIMX_TEXTURE 0x00400588 289#define NV10_PGRAPH_WDIMX_TEXTURE 0x0040058C 290#define NV04_PGRAPH_COMBINE_0_ALPHA 0x00400590 291#define NV04_PGRAPH_COMBINE_0_COLOR 0x00400594 292#define NV04_PGRAPH_COMBINE_1_ALPHA 0x00400598 293#define NV04_PGRAPH_COMBINE_1_COLOR 0x0040059C 294#define NV04_PGRAPH_FORMAT_0 0x004005A8 295#define NV04_PGRAPH_FORMAT_1 0x004005AC 296#define NV04_PGRAPH_FILTER_0 0x004005B0 297#define NV04_PGRAPH_FILTER_1 0x004005B4 298#define NV03_PGRAPH_MONO_COLOR0 0x00400600 299#define NV04_PGRAPH_ROP3 0x00400604 300#define NV04_PGRAPH_BETA_AND 0x00400608 301#define NV04_PGRAPH_BETA_PREMULT 0x0040060C 302#define NV04_PGRAPH_LIMIT_VIOL_PIX 0x00400610 303#define NV04_PGRAPH_FORMATS 0x00400618 304#define NV10_PGRAPH_DEBUG_2 0x00400620 305#define NV04_PGRAPH_BOFFSET0 0x00400640 306#define NV04_PGRAPH_BOFFSET1 0x00400644 307#define NV04_PGRAPH_BOFFSET2 0x00400648 308#define NV04_PGRAPH_BOFFSET3 0x0040064C 309#define NV04_PGRAPH_BOFFSET4 0x00400650 310#define NV04_PGRAPH_BOFFSET5 0x00400654 311#define NV04_PGRAPH_BBASE0 0x00400658 312#define NV04_PGRAPH_BBASE1 0x0040065C 313#define NV04_PGRAPH_BBASE2 0x00400660 314#define NV04_PGRAPH_BBASE3 0x00400664 315#define NV04_PGRAPH_BBASE4 0x00400668 316#define NV04_PGRAPH_BBASE5 0x0040066C 317#define NV04_PGRAPH_BPITCH0 0x00400670 318#define NV04_PGRAPH_BPITCH1 0x00400674 319#define NV04_PGRAPH_BPITCH2 0x00400678 320#define NV04_PGRAPH_BPITCH3 0x0040067C 321#define NV04_PGRAPH_BPITCH4 0x00400680 322#define NV04_PGRAPH_BLIMIT0 0x00400684 323#define NV04_PGRAPH_BLIMIT1 0x00400688 324#define NV04_PGRAPH_BLIMIT2 0x0040068C 325#define NV04_PGRAPH_BLIMIT3 0x00400690 326#define NV04_PGRAPH_BLIMIT4 0x00400694 327#define NV04_PGRAPH_BLIMIT5 0x00400698 328#define NV04_PGRAPH_BSWIZZLE2 0x0040069C 329#define NV04_PGRAPH_BSWIZZLE5 0x004006A0 330#define NV03_PGRAPH_STATUS 0x004006B0 331#define NV04_PGRAPH_STATUS 0x00400700 332# define NV40_PGRAPH_STATUS_SYNC_STALL 0x00004000 333#define NV04_PGRAPH_TRAPPED_ADDR 0x00400704 334#define NV04_PGRAPH_TRAPPED_DATA 0x00400708 335#define NV04_PGRAPH_SURFACE 0x0040070C 336#define NV10_PGRAPH_TRAPPED_DATA_HIGH 0x0040070C 337#define NV04_PGRAPH_STATE 0x00400710 338#define NV10_PGRAPH_SURFACE 0x00400710 339#define NV04_PGRAPH_NOTIFY 0x00400714 340#define NV10_PGRAPH_STATE 0x00400714 341#define NV10_PGRAPH_NOTIFY 0x00400718 342 343#define NV04_PGRAPH_FIFO 0x00400720 344 345#define NV04_PGRAPH_BPIXEL 0x00400724 346#define NV10_PGRAPH_RDI_INDEX 0x00400750 347#define NV04_PGRAPH_FFINTFC_ST2 0x00400754 348#define NV10_PGRAPH_RDI_DATA 0x00400754 349#define NV04_PGRAPH_DMA_PITCH 0x00400760 350#define NV10_PGRAPH_FFINTFC_FIFO_PTR 0x00400760 351#define NV04_PGRAPH_DVD_COLORFMT 0x00400764 352#define NV10_PGRAPH_FFINTFC_ST2 0x00400764 353#define NV04_PGRAPH_SCALED_FORMAT 0x00400768 354#define NV10_PGRAPH_FFINTFC_ST2_DL 0x00400768 355#define NV10_PGRAPH_FFINTFC_ST2_DH 0x0040076c 356#define NV10_PGRAPH_DMA_PITCH 0x00400770 357#define NV10_PGRAPH_DVD_COLORFMT 0x00400774 358#define NV10_PGRAPH_SCALED_FORMAT 0x00400778 359#define NV20_PGRAPH_CHANNEL_CTX_TABLE 0x00400780 360#define NV20_PGRAPH_CHANNEL_CTX_POINTER 0x00400784 361#define NV20_PGRAPH_CHANNEL_CTX_XFER 0x00400788 362#define NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD 0x00000001 363#define NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE 0x00000002 364#define NV04_PGRAPH_PATT_COLOR0 0x00400800 365#define NV04_PGRAPH_PATT_COLOR1 0x00400804 366#define NV04_PGRAPH_PATTERN 0x00400808 367#define NV04_PGRAPH_PATTERN_SHAPE 0x00400810 368#define NV04_PGRAPH_CHROMA 0x00400814 369#define NV04_PGRAPH_CONTROL0 0x00400818 370#define NV04_PGRAPH_CONTROL1 0x0040081C 371#define NV04_PGRAPH_CONTROL2 0x00400820 372#define NV04_PGRAPH_BLEND 0x00400824 373#define NV04_PGRAPH_STORED_FMT 0x00400830 374#define NV04_PGRAPH_PATT_COLORRAM 0x00400900 375#define NV20_PGRAPH_TILE(i) (0x00400900 + (i*16)) 376#define NV20_PGRAPH_TLIMIT(i) (0x00400904 + (i*16)) 377#define NV20_PGRAPH_TSIZE(i) (0x00400908 + (i*16)) 378#define NV20_PGRAPH_TSTATUS(i) (0x0040090C + (i*16)) 379#define NV20_PGRAPH_ZCOMP(i) (0x00400980 + 4*(i)) 380#define NV10_PGRAPH_TILE(i) (0x00400B00 + (i*16)) 381#define NV10_PGRAPH_TLIMIT(i) (0x00400B04 + (i*16)) 382#define NV10_PGRAPH_TSIZE(i) (0x00400B08 + (i*16)) 383#define NV10_PGRAPH_TSTATUS(i) (0x00400B0C + (i*16)) 384#define NV04_PGRAPH_U_RAM 0x00400D00 385#define NV47_PGRAPH_TILE(i) (0x00400D00 + (i*16)) 386#define NV47_PGRAPH_TLIMIT(i) (0x00400D04 + (i*16)) 387#define NV47_PGRAPH_TSIZE(i) (0x00400D08 + (i*16)) 388#define NV47_PGRAPH_TSTATUS(i) (0x00400D0C + (i*16)) 389#define NV04_PGRAPH_V_RAM 0x00400D40 390#define NV04_PGRAPH_W_RAM 0x00400D80 391#define NV10_PGRAPH_COMBINER0_IN_ALPHA 0x00400E40 392#define NV10_PGRAPH_COMBINER1_IN_ALPHA 0x00400E44 393#define NV10_PGRAPH_COMBINER0_IN_RGB 0x00400E48 394#define NV10_PGRAPH_COMBINER1_IN_RGB 0x00400E4C 395#define NV10_PGRAPH_COMBINER_COLOR0 0x00400E50 396#define NV10_PGRAPH_COMBINER_COLOR1 0x00400E54 397#define NV10_PGRAPH_COMBINER0_OUT_ALPHA 0x00400E58 398#define NV10_PGRAPH_COMBINER1_OUT_ALPHA 0x00400E5C 399#define NV10_PGRAPH_COMBINER0_OUT_RGB 0x00400E60 400#define NV10_PGRAPH_COMBINER1_OUT_RGB 0x00400E64 401#define NV10_PGRAPH_COMBINER_FINAL0 0x00400E68 402#define NV10_PGRAPH_COMBINER_FINAL1 0x00400E6C 403#define NV10_PGRAPH_WINDOWCLIP_HORIZONTAL 0x00400F00 404#define NV10_PGRAPH_WINDOWCLIP_VERTICAL 0x00400F20 405#define NV10_PGRAPH_XFMODE0 0x00400F40 406#define NV10_PGRAPH_XFMODE1 0x00400F44 407#define NV10_PGRAPH_GLOBALSTATE0 0x00400F48 408#define NV10_PGRAPH_GLOBALSTATE1 0x00400F4C 409#define NV10_PGRAPH_PIPE_ADDRESS 0x00400F50 410#define NV10_PGRAPH_PIPE_DATA 0x00400F54 411#define NV04_PGRAPH_DMA_START_0 0x00401000 412#define NV04_PGRAPH_DMA_START_1 0x00401004 413#define NV04_PGRAPH_DMA_LENGTH 0x00401008 414#define NV04_PGRAPH_DMA_MISC 0x0040100C 415#define NV04_PGRAPH_DMA_DATA_0 0x00401020 416#define NV04_PGRAPH_DMA_DATA_1 0x00401024 417#define NV04_PGRAPH_DMA_RM 0x00401030 418#define NV04_PGRAPH_DMA_A_XLATE_INST 0x00401040 419#define NV04_PGRAPH_DMA_A_CONTROL 0x00401044 420#define NV04_PGRAPH_DMA_A_LIMIT 0x00401048 421#define NV04_PGRAPH_DMA_A_TLB_PTE 0x0040104C 422#define NV04_PGRAPH_DMA_A_TLB_TAG 0x00401050 423#define NV04_PGRAPH_DMA_A_ADJ_OFFSET 0x00401054 424#define NV04_PGRAPH_DMA_A_OFFSET 0x00401058 425#define NV04_PGRAPH_DMA_A_SIZE 0x0040105C 426#define NV04_PGRAPH_DMA_A_Y_SIZE 0x00401060 427#define NV04_PGRAPH_DMA_B_XLATE_INST 0x00401080 428#define NV04_PGRAPH_DMA_B_CONTROL 0x00401084 429#define NV04_PGRAPH_DMA_B_LIMIT 0x00401088 430#define NV04_PGRAPH_DMA_B_TLB_PTE 0x0040108C 431#define NV04_PGRAPH_DMA_B_TLB_TAG 0x00401090 432#define NV04_PGRAPH_DMA_B_ADJ_OFFSET 0x00401094 433#define NV04_PGRAPH_DMA_B_OFFSET 0x00401098 434#define NV04_PGRAPH_DMA_B_SIZE 0x0040109C 435#define NV04_PGRAPH_DMA_B_Y_SIZE 0x004010A0 436#define NV40_PGRAPH_TILE1(i) (0x00406900 + (i*16)) 437#define NV40_PGRAPH_TLIMIT1(i) (0x00406904 + (i*16)) 438#define NV40_PGRAPH_TSIZE1(i) (0x00406908 + (i*16)) 439#define NV40_PGRAPH_TSTATUS1(i) (0x0040690C + (i*16)) 440 441 442/* It's a guess that this works on NV03. Confirmed on NV04, though */ 443#define NV04_PFIFO_DELAY_0 0x00002040 444#define NV04_PFIFO_DMA_TIMESLICE 0x00002044 445#define NV04_PFIFO_NEXT_CHANNEL 0x00002050 446#define NV03_PFIFO_INTR_0 0x00002100 447#define NV03_PFIFO_INTR_EN_0 0x00002140 448# define NV_PFIFO_INTR_CACHE_ERROR (1<<0) 449# define NV_PFIFO_INTR_RUNOUT (1<<4) 450# define NV_PFIFO_INTR_RUNOUT_OVERFLOW (1<<8) 451# define NV_PFIFO_INTR_DMA_PUSHER (1<<12) 452# define NV_PFIFO_INTR_DMA_PT (1<<16) 453# define NV_PFIFO_INTR_SEMAPHORE (1<<20) 454# define NV_PFIFO_INTR_ACQUIRE_TIMEOUT (1<<24) 455#define NV03_PFIFO_RAMHT 0x00002210 456#define NV03_PFIFO_RAMFC 0x00002214 457#define NV03_PFIFO_RAMRO 0x00002218 458#define NV40_PFIFO_RAMFC 0x00002220 459#define NV03_PFIFO_CACHES 0x00002500 460#define NV04_PFIFO_MODE 0x00002504 461#define NV04_PFIFO_DMA 0x00002508 462#define NV04_PFIFO_SIZE 0x0000250c 463#define NV50_PFIFO_CTX_TABLE(c) (0x2600+(c)*4) 464#define NV50_PFIFO_CTX_TABLE__SIZE 128 465#define NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED (1<<31) 466#define NV50_PFIFO_CTX_TABLE_UNK30_BAD (1<<30) 467#define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80 0x0FFFFFFF 468#define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84 0x00FFFFFF 469#define NV03_PFIFO_CACHE0_PUSH0 0x00003000 470#define NV03_PFIFO_CACHE0_PULL0 0x00003040 471#define NV04_PFIFO_CACHE0_PULL0 0x00003050 472#define NV04_PFIFO_CACHE0_PULL1 0x00003054 473#define NV03_PFIFO_CACHE1_PUSH0 0x00003200 474#define NV03_PFIFO_CACHE1_PUSH1 0x00003204 475#define NV03_PFIFO_CACHE1_PUSH1_DMA (1<<8) 476#define NV40_PFIFO_CACHE1_PUSH1_DMA (1<<16) 477#define NV03_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000000f 478#define NV10_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000001f 479#define NV50_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000007f 480#define NV03_PFIFO_CACHE1_PUT 0x00003210 481#define NV04_PFIFO_CACHE1_DMA_PUSH 0x00003220 482#define NV04_PFIFO_CACHE1_DMA_FETCH 0x00003224 483# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000 484# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000008 485# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000010 486# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000018 487# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000020 488# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000028 489# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000030 490# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000038 491# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000040 492# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000048 493# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x00000050 494# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x00000058 495# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x00000060 496# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x00000068 497# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x00000070 498# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x00000078 499# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000080 500# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000088 501# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000090 502# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000098 503# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x000000A0 504# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x000000A8 505# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x000000B0 506# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x000000B8 507# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x000000C0 508# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x000000C8 509# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x000000D0 510# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x000000D8 511# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x000000E0 512# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x000000E8 513# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x000000F0 514# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x000000F8 515# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 0x0000E000 516# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000 517# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00002000 518# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00004000 519# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00006000 520# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00008000 521# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x0000A000 522# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x0000C000 523# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x0000E000 524# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 0x001F0000 525# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000 526# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00010000 527# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00020000 528# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00030000 529# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00040000 530# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00050000 531# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00060000 532# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00070000 533# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00080000 534# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00090000 535# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x000A0000 536# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x000B0000 537# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x000C0000 538# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x000D0000 539# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x000E0000 540# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x000F0000 541# define NV_PFIFO_CACHE1_ENDIAN 0x80000000 542# define NV_PFIFO_CACHE1_LITTLE_ENDIAN 0x7FFFFFFF 543# define NV_PFIFO_CACHE1_BIG_ENDIAN 0x80000000 544#define NV04_PFIFO_CACHE1_DMA_STATE 0x00003228 545#define NV04_PFIFO_CACHE1_DMA_INSTANCE 0x0000322c 546#define NV04_PFIFO_CACHE1_DMA_CTL 0x00003230 547#define NV04_PFIFO_CACHE1_DMA_PUT 0x00003240 548#define NV04_PFIFO_CACHE1_DMA_GET 0x00003244 549#define NV10_PFIFO_CACHE1_REF_CNT 0x00003248 550#define NV10_PFIFO_CACHE1_DMA_SUBROUTINE 0x0000324C 551#define NV03_PFIFO_CACHE1_PULL0 0x00003240 552#define NV04_PFIFO_CACHE1_PULL0 0x00003250 553# define NV04_PFIFO_CACHE1_PULL0_HASH_FAILED 0x00000010 554# define NV04_PFIFO_CACHE1_PULL0_HASH_BUSY 0x00001000 555#define NV03_PFIFO_CACHE1_PULL1 0x00003250 556#define NV04_PFIFO_CACHE1_PULL1 0x00003254 557#define NV04_PFIFO_CACHE1_HASH 0x00003258 558#define NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT 0x00003260 559#define NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP 0x00003264 560#define NV10_PFIFO_CACHE1_ACQUIRE_VALUE 0x00003268 561#define NV10_PFIFO_CACHE1_SEMAPHORE 0x0000326C 562#define NV03_PFIFO_CACHE1_GET 0x00003270 563#define NV04_PFIFO_CACHE1_ENGINE 0x00003280 564#define NV04_PFIFO_CACHE1_DMA_DCOUNT 0x000032A0 565#define NV40_PFIFO_GRCTX_INSTANCE 0x000032E0 566#define NV40_PFIFO_UNK32E4 0x000032E4 567#define NV04_PFIFO_CACHE1_METHOD(i) (0x00003800+(i*8)) 568#define NV04_PFIFO_CACHE1_DATA(i) (0x00003804+(i*8)) 569#define NV40_PFIFO_CACHE1_METHOD(i) (0x00090000+(i*8)) 570#define NV40_PFIFO_CACHE1_DATA(i) (0x00090004+(i*8)) 571 572#define NV_CRTC0_INTSTAT 0x00600100 573#define NV_CRTC0_INTEN 0x00600140 574#define NV_CRTC1_INTSTAT 0x00602100 575#define NV_CRTC1_INTEN 0x00602140 576# define NV_CRTC_INTR_VBLANK (1<<0) 577 578#define NV04_PRAMIN 0x00700000 579 580/* Fifo commands. These are not regs, neither masks */ 581#define NV03_FIFO_CMD_JUMP 0x20000000 582#define NV03_FIFO_CMD_JUMP_OFFSET_MASK 0x1ffffffc 583#define NV03_FIFO_CMD_REWIND (NV03_FIFO_CMD_JUMP | (0 & NV03_FIFO_CMD_JUMP_OFFSET_MASK)) 584 585/* This is a partial import from rules-ng, a few things may be duplicated. 586 * Eventually we should completely import everything from rules-ng. 587 * For the moment check rules-ng for docs. 588 */ 589 590#define NV50_PMC 0x00000000 591#define NV50_PMC__LEN 0x1 592#define NV50_PMC__ESIZE 0x2000 593# define NV50_PMC_BOOT_0 0x00000000 594# define NV50_PMC_BOOT_0_REVISION 0x000000ff 595# define NV50_PMC_BOOT_0_REVISION__SHIFT 0 596# define NV50_PMC_BOOT_0_ARCH 0x0ff00000 597# define NV50_PMC_BOOT_0_ARCH__SHIFT 20 598# define NV50_PMC_INTR_0 0x00000100 599# define NV50_PMC_INTR_0_PFIFO (1<<8) 600# define NV50_PMC_INTR_0_PGRAPH (1<<12) 601# define NV50_PMC_INTR_0_PTIMER (1<<20) 602# define NV50_PMC_INTR_0_HOTPLUG (1<<21) 603# define NV50_PMC_INTR_0_DISPLAY (1<<26) 604# define NV50_PMC_INTR_EN_0 0x00000140 605# define NV50_PMC_INTR_EN_0_MASTER (1<<0) 606# define NV50_PMC_INTR_EN_0_MASTER_DISABLED (0<<0) 607# define NV50_PMC_INTR_EN_0_MASTER_ENABLED (1<<0) 608# define NV50_PMC_ENABLE 0x00000200 609# define NV50_PMC_ENABLE_PFIFO (1<<8) 610# define NV50_PMC_ENABLE_PGRAPH (1<<12) 611 612#define NV50_PCONNECTOR 0x0000e000 613#define NV50_PCONNECTOR__LEN 0x1 614#define NV50_PCONNECTOR__ESIZE 0x1000 615# define NV50_PCONNECTOR_HOTPLUG_INTR 0x0000e050 616# define NV50_PCONNECTOR_HOTPLUG_INTR_PLUG_I2C0 (1<<0) 617# define NV50_PCONNECTOR_HOTPLUG_INTR_PLUG_I2C1 (1<<1) 618# define NV50_PCONNECTOR_HOTPLUG_INTR_PLUG_I2C2 (1<<2) 619# define NV50_PCONNECTOR_HOTPLUG_INTR_PLUG_I2C3 (1<<3) 620# define NV50_PCONNECTOR_HOTPLUG_INTR_UNPLUG_I2C0 (1<<16) 621# define NV50_PCONNECTOR_HOTPLUG_INTR_UNPLUG_I2C1 (1<<17) 622# define NV50_PCONNECTOR_HOTPLUG_INTR_UNPLUG_I2C2 (1<<18) 623# define NV50_PCONNECTOR_HOTPLUG_INTR_UNPLUG_I2C3 (1<<19) 624# define NV50_PCONNECTOR_HOTPLUG_CTRL 0x0000e054 625# define NV50_PCONNECTOR_HOTPLUG_CTRL_PLUG_I2C0 (1<<0) 626# define NV50_PCONNECTOR_HOTPLUG_CTRL_PLUG_I2C1 (1<<1) 627# define NV50_PCONNECTOR_HOTPLUG_CTRL_PLUG_I2C2 (1<<2) 628# define NV50_PCONNECTOR_HOTPLUG_CTRL_PLUG_I2C3 (1<<3) 629# define NV50_PCONNECTOR_HOTPLUG_CTRL_UNPLUG_I2C0 (1<<16) 630# define NV50_PCONNECTOR_HOTPLUG_CTRL_UNPLUG_I2C1 (1<<17) 631# define NV50_PCONNECTOR_HOTPLUG_CTRL_UNPLUG_I2C2 (1<<18) 632# define NV50_PCONNECTOR_HOTPLUG_CTRL_UNPLUG_I2C3 (1<<19) 633# define NV50_PCONNECTOR_HOTPLUG_STATE 0x0000e104 634# define NV50_PCONNECTOR_HOTPLUG_STATE_PIN_CONNECTED_I2C0 (1<<2) 635# define NV50_PCONNECTOR_HOTPLUG_STATE_PIN_CONNECTED_I2C1 (1<<6) 636# define NV50_PCONNECTOR_HOTPLUG_STATE_PIN_CONNECTED_I2C2 (1<<10) 637# define NV50_PCONNECTOR_HOTPLUG_STATE_PIN_CONNECTED_I2C3 (1<<14) 638# define NV50_PCONNECTOR_I2C_PORT_0 0x0000e138 639# define NV50_PCONNECTOR_I2C_PORT_1 0x0000e150 640# define NV50_PCONNECTOR_I2C_PORT_2 0x0000e168 641# define NV50_PCONNECTOR_I2C_PORT_3 0x0000e180 642# define NV50_PCONNECTOR_I2C_PORT_4 0x0000e240 643# define NV50_PCONNECTOR_I2C_PORT_5 0x0000e258 644 645#define NV50_AUXCH_DATA_OUT(i, n) ((n) * 4 + (i) * 0x50 + 0x0000e4c0) 646#define NV50_AUXCH_DATA_OUT__SIZE 4 647#define NV50_AUXCH_DATA_IN(i, n) ((n) * 4 + (i) * 0x50 + 0x0000e4d0) 648#define NV50_AUXCH_DATA_IN__SIZE 4 649#define NV50_AUXCH_ADDR(i) ((i) * 0x50 + 0x0000e4e0) 650#define NV50_AUXCH_CTRL(i) ((i) * 0x50 + 0x0000e4e4) 651#define NV50_AUXCH_CTRL_LINKSTAT 0x01000000 652#define NV50_AUXCH_CTRL_LINKSTAT_NOT_READY 0x00000000 653#define NV50_AUXCH_CTRL_LINKSTAT_READY 0x01000000 654#define NV50_AUXCH_CTRL_LINKEN 0x00100000 655#define NV50_AUXCH_CTRL_LINKEN_DISABLED 0x00000000 656#define NV50_AUXCH_CTRL_LINKEN_ENABLED 0x00100000 657#define NV50_AUXCH_CTRL_EXEC 0x00010000 658#define NV50_AUXCH_CTRL_EXEC_COMPLETE 0x00000000 659#define NV50_AUXCH_CTRL_EXEC_IN_PROCESS 0x00010000 660#define NV50_AUXCH_CTRL_CMD 0x0000f000 661#define NV50_AUXCH_CTRL_CMD_SHIFT 12 662#define NV50_AUXCH_CTRL_LEN 0x0000000f 663#define NV50_AUXCH_CTRL_LEN_SHIFT 0 664#define NV50_AUXCH_STAT(i) ((i) * 0x50 + 0x0000e4e8) 665#define NV50_AUXCH_STAT_STATE 0x10000000 666#define NV50_AUXCH_STAT_STATE_NOT_READY 0x00000000 667#define NV50_AUXCH_STAT_STATE_READY 0x10000000 668#define NV50_AUXCH_STAT_REPLY 0x000f0000 669#define NV50_AUXCH_STAT_REPLY_AUX 0x00030000 670#define NV50_AUXCH_STAT_REPLY_AUX_ACK 0x00000000 671#define NV50_AUXCH_STAT_REPLY_AUX_NACK 0x00010000 672#define NV50_AUXCH_STAT_REPLY_AUX_DEFER 0x00020000 673#define NV50_AUXCH_STAT_REPLY_I2C 0x000c0000 674#define NV50_AUXCH_STAT_REPLY_I2C_ACK 0x00000000 675#define NV50_AUXCH_STAT_REPLY_I2C_NACK 0x00040000 676#define NV50_AUXCH_STAT_REPLY_I2C_DEFER 0x00080000 677#define NV50_AUXCH_STAT_COUNT 0x0000001f 678 679#define NV50_PBUS 0x00088000 680#define NV50_PBUS__LEN 0x1 681#define NV50_PBUS__ESIZE 0x1000 682# define NV50_PBUS_PCI_ID 0x00088000 683# define NV50_PBUS_PCI_ID_VENDOR_ID 0x0000ffff 684# define NV50_PBUS_PCI_ID_VENDOR_ID__SHIFT 0 685# define NV50_PBUS_PCI_ID_DEVICE_ID 0xffff0000 686# define NV50_PBUS_PCI_ID_DEVICE_ID__SHIFT 16 687 688#define NV50_PFB 0x00100000 689#define NV50_PFB__LEN 0x1 690#define NV50_PFB__ESIZE 0x1000 691 692#define NV50_PEXTDEV 0x00101000 693#define NV50_PEXTDEV__LEN 0x1 694#define NV50_PEXTDEV__ESIZE 0x1000 695 696#define NV50_PROM 0x00300000 697#define NV50_PROM__LEN 0x1 698#define NV50_PROM__ESIZE 0x10000 699 700#define NV50_PGRAPH 0x00400000 701#define NV50_PGRAPH__LEN 0x1 702#define NV50_PGRAPH__ESIZE 0x10000 703 704#define NV50_PDISPLAY 0x00610000 705#define NV50_PDISPLAY_OBJECTS 0x00610010 706#define NV50_PDISPLAY_INTR_0 0x00610020 707#define NV50_PDISPLAY_INTR_1 0x00610024 708#define NV50_PDISPLAY_INTR_1_VBLANK_CRTC 0x0000000c 709#define NV50_PDISPLAY_INTR_1_VBLANK_CRTC_SHIFT 2 710#define NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(n) (1 << ((n) + 2)) 711#define NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0 0x00000004 712#define NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1 0x00000008 713#define NV50_PDISPLAY_INTR_1_CLK_UNK10 0x00000010 714#define NV50_PDISPLAY_INTR_1_CLK_UNK20 0x00000020 715#define NV50_PDISPLAY_INTR_1_CLK_UNK40 0x00000040 716#define NV50_PDISPLAY_INTR_EN_0 0x00610028 717#define NV50_PDISPLAY_INTR_EN_1 0x0061002c 718#define NV50_PDISPLAY_INTR_EN_1_VBLANK_CRTC 0x0000000c 719#define NV50_PDISPLAY_INTR_EN_1_VBLANK_CRTC_(n) (1 << ((n) + 2)) 720#define NV50_PDISPLAY_INTR_EN_1_VBLANK_CRTC_0 0x00000004 721#define NV50_PDISPLAY_INTR_EN_1_VBLANK_CRTC_1 0x00000008 722#define NV50_PDISPLAY_INTR_EN_1_CLK_UNK10 0x00000010 723#define NV50_PDISPLAY_INTR_EN_1_CLK_UNK20 0x00000020 724#define NV50_PDISPLAY_INTR_EN_1_CLK_UNK40 0x00000040 725#define NV50_PDISPLAY_UNK30_CTRL 0x00610030 726#define NV50_PDISPLAY_UNK30_CTRL_UPDATE_VCLK0 0x00000200 727#define NV50_PDISPLAY_UNK30_CTRL_UPDATE_VCLK1 0x00000400 728#define NV50_PDISPLAY_UNK30_CTRL_PENDING 0x80000000 729#define NV50_PDISPLAY_TRAPPED_ADDR(i) ((i) * 0x08 + 0x00610080) 730#define NV50_PDISPLAY_TRAPPED_DATA(i) ((i) * 0x08 + 0x00610084) 731#define NV50_PDISPLAY_EVO_CTRL(i) ((i) * 0x10 + 0x00610200) 732#define NV50_PDISPLAY_EVO_CTRL_DMA 0x00000010 733#define NV50_PDISPLAY_EVO_CTRL_DMA_DISABLED 0x00000000 734#define NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED 0x00000010 735#define NV50_PDISPLAY_EVO_DMA_CB(i) ((i) * 0x10 + 0x00610204) 736#define NV50_PDISPLAY_EVO_DMA_CB_LOCATION 0x00000002 737#define NV50_PDISPLAY_EVO_DMA_CB_LOCATION_VRAM 0x00000000 738#define NV50_PDISPLAY_EVO_DMA_CB_LOCATION_SYSTEM 0x00000002 739#define NV50_PDISPLAY_EVO_DMA_CB_VALID 0x00000001 740#define NV50_PDISPLAY_EVO_UNK2(i) ((i) * 0x10 + 0x00610208) 741#define NV50_PDISPLAY_EVO_HASH_TAG(i) ((i) * 0x10 + 0x0061020c) 742 743#define NV50_PDISPLAY_CURSOR 0x00610270 744#define NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i) ((i) * 0x10 + 0x00610270) 745#define NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON 0x00000001 746#define NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS 0x00030000 747#define NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE 0x00010000 748 749#define NV50_PDISPLAY_PIO_CTRL 0x00610300 750#define NV50_PDISPLAY_PIO_CTRL_PENDING 0x80000000 751#define NV50_PDISPLAY_PIO_CTRL_MTHD 0x00001ffc 752#define NV50_PDISPLAY_PIO_CTRL_ENABLED 0x00000001 753#define NV50_PDISPLAY_PIO_DATA 0x00610304 754 755#define NV50_PDISPLAY_CRTC_P(i, r) ((i) * 0x540 + NV50_PDISPLAY_CRTC_##r) 756#define NV50_PDISPLAY_CRTC_C(i, r) (4 + (i) * 0x540 + NV50_PDISPLAY_CRTC_##r) 757#define NV50_PDISPLAY_CRTC_UNK_0A18 /* mthd 0x0900 */ 0x00610a18 758#define NV50_PDISPLAY_CRTC_CLUT_MODE 0x00610a24 759#define NV50_PDISPLAY_CRTC_INTERLACE 0x00610a48 760#define NV50_PDISPLAY_CRTC_SCALE_CTRL 0x00610a50 761#define NV50_PDISPLAY_CRTC_CURSOR_CTRL 0x00610a58 762#define NV50_PDISPLAY_CRTC_UNK0A78 /* mthd 0x0904 */ 0x00610a78 763#define NV50_PDISPLAY_CRTC_UNK0AB8 0x00610ab8 764#define NV50_PDISPLAY_CRTC_DEPTH 0x00610ac8 765#define NV50_PDISPLAY_CRTC_CLOCK 0x00610ad0 766#define NV50_PDISPLAY_CRTC_COLOR_CTRL 0x00610ae0 767#define NV50_PDISPLAY_CRTC_SYNC_START_TO_BLANK_END 0x00610ae8 768#define NV50_PDISPLAY_CRTC_MODE_UNK1 0x00610af0 769#define NV50_PDISPLAY_CRTC_DISPLAY_TOTAL 0x00610af8 770#define NV50_PDISPLAY_CRTC_SYNC_DURATION 0x00610b00 771#define NV50_PDISPLAY_CRTC_MODE_UNK2 0x00610b08 772#define NV50_PDISPLAY_CRTC_UNK_0B10 /* mthd 0x0828 */ 0x00610b10 773#define NV50_PDISPLAY_CRTC_FB_SIZE 0x00610b18 774#define NV50_PDISPLAY_CRTC_FB_PITCH 0x00610b20 775#define NV50_PDISPLAY_CRTC_FB_PITCH_LINEAR 0x00100000 776#define NV50_PDISPLAY_CRTC_FB_POS 0x00610b28 777#define NV50_PDISPLAY_CRTC_SCALE_CENTER_OFFSET 0x00610b38 778#define NV50_PDISPLAY_CRTC_REAL_RES 0x00610b40 779#define NV50_PDISPLAY_CRTC_SCALE_RES1 0x00610b48 780#define NV50_PDISPLAY_CRTC_SCALE_RES2 0x00610b50 781 782#define NV50_PDISPLAY_DAC_MODE_CTRL_P(i) (0x00610b58 + (i) * 0x8) 783#define NV50_PDISPLAY_DAC_MODE_CTRL_C(i) (0x00610b5c + (i) * 0x8) 784#define NV50_PDISPLAY_SOR_MODE_CTRL_P(i) (0x00610b70 + (i) * 0x8) 785#define NV50_PDISPLAY_SOR_MODE_CTRL_C(i) (0x00610b74 + (i) * 0x8) 786#define NV50_PDISPLAY_EXT_MODE_CTRL_P(i) (0x00610b80 + (i) * 0x8) 787#define NV50_PDISPLAY_EXT_MODE_CTRL_C(i) (0x00610b84 + (i) * 0x8) 788#define NV50_PDISPLAY_DAC_MODE_CTRL2_P(i) (0x00610bdc + (i) * 0x8) 789#define NV50_PDISPLAY_DAC_MODE_CTRL2_C(i) (0x00610be0 + (i) * 0x8) 790#define NV90_PDISPLAY_SOR_MODE_CTRL_P(i) (0x00610794 + (i) * 0x8) 791#define NV90_PDISPLAY_SOR_MODE_CTRL_C(i) (0x00610798 + (i) * 0x8) 792 793#define NV50_PDISPLAY_CRTC_CLK 0x00614000 794#define NV50_PDISPLAY_CRTC_CLK_CTRL1(i) ((i) * 0x800 + 0x614100) 795#define NV50_PDISPLAY_CRTC_CLK_CTRL1_CONNECTED 0x00000600 796#define NV50_PDISPLAY_CRTC_CLK_VPLL_A(i) ((i) * 0x800 + 0x614104) 797#define NV50_PDISPLAY_CRTC_CLK_VPLL_B(i) ((i) * 0x800 + 0x614108) 798#define NV50_PDISPLAY_CRTC_CLK_CTRL2(i) ((i) * 0x800 + 0x614200) 799 800#define NV50_PDISPLAY_DAC_CLK 0x00614000 801#define NV50_PDISPLAY_DAC_CLK_CTRL2(i) ((i) * 0x800 + 0x614280) 802 803#define NV50_PDISPLAY_SOR_CLK 0x00614000 804#define NV50_PDISPLAY_SOR_CLK_CTRL2(i) ((i) * 0x800 + 0x614300) 805 806#define NV50_PDISPLAY_VGACRTC(r) ((r) + 0x619400) 807 808#define NV50_PDISPLAY_DAC 0x0061a000 809#define NV50_PDISPLAY_DAC_DPMS_CTRL(i) (0x0061a004 + (i) * 0x800) 810#define NV50_PDISPLAY_DAC_DPMS_CTRL_HSYNC_OFF 0x00000001 811#define NV50_PDISPLAY_DAC_DPMS_CTRL_VSYNC_OFF 0x00000004 812#define NV50_PDISPLAY_DAC_DPMS_CTRL_BLANKED 0x00000010 813#define NV50_PDISPLAY_DAC_DPMS_CTRL_OFF 0x00000040 814#define NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING 0x80000000 815#define NV50_PDISPLAY_DAC_LOAD_CTRL(i) (0x0061a00c + (i) * 0x800) 816#define NV50_PDISPLAY_DAC_LOAD_CTRL_ACTIVE 0x00100000 817#define NV50_PDISPLAY_DAC_LOAD_CTRL_PRESENT 0x38000000 818#define NV50_PDISPLAY_DAC_LOAD_CTRL_DONE 0x80000000 819#define NV50_PDISPLAY_DAC_CLK_CTRL1(i) (0x0061a010 + (i) * 0x800) 820#define NV50_PDISPLAY_DAC_CLK_CTRL1_CONNECTED 0x00000600 821 822#define NV50_PDISPLAY_SOR 0x0061c000 823#define NV50_PDISPLAY_SOR_DPMS_CTRL(i) (0x0061c004 + (i) * 0x800) 824#define NV50_PDISPLAY_SOR_DPMS_CTRL_PENDING 0x80000000 825#define NV50_PDISPLAY_SOR_DPMS_CTRL_ON 0x00000001 826#define NV50_PDISPLAY_SOR_CLK_CTRL1(i) (0x0061c008 + (i) * 0x800) 827#define NV50_PDISPLAY_SOR_CLK_CTRL1_CONNECTED 0x00000600 828#define NV50_PDISPLAY_SOR_DPMS_STATE(i) (0x0061c030 + (i) * 0x800) 829#define NV50_PDISPLAY_SOR_DPMS_STATE_ACTIVE 0x00030000 830#define NV50_PDISPLAY_SOR_DPMS_STATE_BLANKED 0x00080000 831#define NV50_PDISPLAY_SOR_DPMS_STATE_WAIT 0x10000000 832#define NV50_PDISP_SOR_PWM_DIV(i) (0x0061c080 + (i) * 0x800) 833#define NV50_PDISP_SOR_PWM_CTL(i) (0x0061c084 + (i) * 0x800) 834#define NV50_PDISP_SOR_PWM_CTL_NEW 0x80000000 835#define NVA3_PDISP_SOR_PWM_CTL_UNK 0x40000000 836#define NV50_PDISP_SOR_PWM_CTL_VAL 0x000007ff 837#define NVA3_PDISP_SOR_PWM_CTL_VAL 0x00ffffff 838#define NV50_SOR_DP_CTRL(i, l) (0x0061c10c + (i) * 0x800 + (l) * 0x80) 839#define NV50_SOR_DP_CTRL_ENABLED 0x00000001 840#define NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED 0x00004000 841#define NV50_SOR_DP_CTRL_LANE_MASK 0x001f0000 842#define NV50_SOR_DP_CTRL_LANE_0_ENABLED 0x00010000 843#define NV50_SOR_DP_CTRL_LANE_1_ENABLED 0x00020000 844#define NV50_SOR_DP_CTRL_LANE_2_ENABLED 0x00040000 845#define NV50_SOR_DP_CTRL_LANE_3_ENABLED 0x00080000 846#define NV50_SOR_DP_CTRL_TRAINING_PATTERN 0x0f000000 847#define NV50_SOR_DP_CTRL_TRAINING_PATTERN_DISABLED 0x00000000 848#define NV50_SOR_DP_CTRL_TRAINING_PATTERN_1 0x01000000 849#define NV50_SOR_DP_CTRL_TRAINING_PATTERN_2 0x02000000 850#define NV50_SOR_DP_UNK118(i, l) (0x0061c118 + (i) * 0x800 + (l) * 0x80) 851#define NV50_SOR_DP_UNK120(i, l) (0x0061c120 + (i) * 0x800 + (l) * 0x80) 852#define NV50_SOR_DP_SCFG(i, l) (0x0061c128 + (i) * 0x800 + (l) * 0x80) 853#define NV50_SOR_DP_UNK130(i, l) (0x0061c130 + (i) * 0x800 + (l) * 0x80) 854 855#define NV50_PDISPLAY_USER(i) ((i) * 0x1000 + 0x00640000) 856#define NV50_PDISPLAY_USER_PUT(i) ((i) * 0x1000 + 0x00640000) 857#define NV50_PDISPLAY_USER_GET(i) ((i) * 0x1000 + 0x00640004) 858 859#define NV50_PDISPLAY_CURSOR_USER 0x00647000 860#define NV50_PDISPLAY_CURSOR_USER_POS_CTRL(i) ((i) * 0x1000 + 0x00647080) 861#define NV50_PDISPLAY_CURSOR_USER_POS(i) ((i) * 0x1000 + 0x00647084) 862