1/*	$NetBSD: smu_v12_0.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $	*/
2
3/*
4 * Copyright 2019 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25#ifndef __SMU_V12_0_H__
26#define __SMU_V12_0_H__
27
28#include "amdgpu_smu.h"
29
30/* MP Apertures */
31#define MP0_Public			0x03800000
32#define MP0_SRAM			0x03900000
33#define MP1_Public			0x03b00000
34#define MP1_SRAM			0x03c00004
35
36
37struct smu_12_0_cmn2aisc_mapping {
38	int	valid_mapping;
39	int	map_to;
40};
41
42int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
43					      uint16_t msg);
44
45int smu_v12_0_read_arg(struct smu_context *smu, uint32_t *arg);
46
47int smu_v12_0_wait_for_response(struct smu_context *smu);
48
49int
50smu_v12_0_send_msg_with_param(struct smu_context *smu,
51			      enum smu_message_type msg,
52			      uint32_t param);
53
54int smu_v12_0_check_fw_status(struct smu_context *smu);
55
56int smu_v12_0_check_fw_version(struct smu_context *smu);
57
58int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate);
59
60int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate);
61
62int smu_v12_0_powergate_jpeg(struct smu_context *smu, bool gate);
63
64int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable);
65
66int smu_v12_0_read_sensor(struct smu_context *smu,
67			  enum amd_pp_sensors sensor,
68			  void *data, uint32_t *size);
69
70uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu);
71
72int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable);
73
74int smu_v12_0_init_smc_tables(struct smu_context *smu);
75
76int smu_v12_0_fini_smc_tables(struct smu_context *smu);
77
78int smu_v12_0_populate_smc_tables(struct smu_context *smu);
79
80int smu_v12_0_get_enabled_mask(struct smu_context *smu,
81				      uint32_t *feature_mask, uint32_t num);
82
83int smu_v12_0_get_current_clk_freq(struct smu_context *smu,
84					  enum smu_clk_type clk_id,
85					  uint32_t *value);
86
87int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
88						 uint32_t *min, uint32_t *max);
89
90int smu_v12_0_mode2_reset(struct smu_context *smu);
91
92int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
93			    uint32_t min, uint32_t max);
94
95int smu_v12_0_set_driver_table_location(struct smu_context *smu);
96
97#endif
98