1/* $NetBSD: smu11_driver_if_arcturus.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3/* 4 * Copyright 2019 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26#ifndef SMU11_DRIVER_IF_ARCTURUS_H 27#define SMU11_DRIVER_IF_ARCTURUS_H 28 29// *** IMPORTANT *** 30// SMU TEAM: Always increment the interface version if 31// any structure is changed in this file 32//#define SMU11_DRIVER_IF_VERSION 0x09 33 34#define PPTABLE_ARCTURUS_SMU_VERSION 4 35 36#define NUM_GFXCLK_DPM_LEVELS 16 37#define NUM_VCLK_DPM_LEVELS 8 38#define NUM_DCLK_DPM_LEVELS 8 39#define NUM_MP0CLK_DPM_LEVELS 2 40#define NUM_SOCCLK_DPM_LEVELS 8 41#define NUM_UCLK_DPM_LEVELS 4 42#define NUM_FCLK_DPM_LEVELS 8 43#define NUM_XGMI_LEVELS 2 44#define NUM_XGMI_PSTATE_LEVELS 4 45 46#define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1) 47#define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1) 48#define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1) 49#define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1) 50#define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1) 51#define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) 52#define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1) 53#define MAX_XGMI_LEVEL (NUM_XGMI_LEVELS - 1) 54#define MAX_XGMI_PSTATE_LEVEL (NUM_XGMI_PSTATE_LEVELS - 1) 55 56// Feature Control Defines 57// DPM 58#define FEATURE_DPM_PREFETCHER_BIT 0 59#define FEATURE_DPM_GFXCLK_BIT 1 60#define FEATURE_DPM_UCLK_BIT 2 61#define FEATURE_DPM_SOCCLK_BIT 3 62#define FEATURE_DPM_FCLK_BIT 4 63#define FEATURE_DPM_MP0CLK_BIT 5 64#define FEATURE_DPM_XGMI_BIT 6 65// Idle 66#define FEATURE_DS_GFXCLK_BIT 7 67#define FEATURE_DS_SOCCLK_BIT 8 68#define FEATURE_DS_LCLK_BIT 9 69#define FEATURE_DS_FCLK_BIT 10 70#define FEATURE_DS_UCLK_BIT 11 71#define FEATURE_GFX_ULV_BIT 12 72#define FEATURE_DPM_VCN_BIT 13 73#define FEATURE_RSMU_SMN_CG_BIT 14 74#define FEATURE_WAFL_CG_BIT 15 75// Throttler/Response 76#define FEATURE_PPT_BIT 16 77#define FEATURE_TDC_BIT 17 78#define FEATURE_APCC_PLUS_BIT 18 79#define FEATURE_VR0HOT_BIT 19 80#define FEATURE_VR1HOT_BIT 20 81#define FEATURE_FW_CTF_BIT 21 82#define FEATURE_FAN_CONTROL_BIT 22 83#define FEATURE_THERMAL_BIT 23 84// Other 85#define FEATURE_OUT_OF_BAND_MONITOR_BIT 24 86#define FEATURE_TEMP_DEPENDENT_VMIN_BIT 25 87 88#define FEATURE_SPARE_26_BIT 26 89#define FEATURE_SPARE_27_BIT 27 90#define FEATURE_SPARE_28_BIT 28 91#define FEATURE_SPARE_29_BIT 29 92#define FEATURE_SPARE_30_BIT 30 93#define FEATURE_SPARE_31_BIT 31 94#define FEATURE_SPARE_32_BIT 32 95#define FEATURE_SPARE_33_BIT 33 96#define FEATURE_SPARE_34_BIT 34 97#define FEATURE_SPARE_35_BIT 35 98#define FEATURE_SPARE_36_BIT 36 99#define FEATURE_SPARE_37_BIT 37 100#define FEATURE_SPARE_38_BIT 38 101#define FEATURE_SPARE_39_BIT 39 102#define FEATURE_SPARE_40_BIT 40 103#define FEATURE_SPARE_41_BIT 41 104#define FEATURE_SPARE_42_BIT 42 105#define FEATURE_SPARE_43_BIT 43 106#define FEATURE_SPARE_44_BIT 44 107#define FEATURE_SPARE_45_BIT 45 108#define FEATURE_SPARE_46_BIT 46 109#define FEATURE_SPARE_47_BIT 47 110#define FEATURE_SPARE_48_BIT 48 111#define FEATURE_SPARE_49_BIT 49 112#define FEATURE_SPARE_50_BIT 50 113#define FEATURE_SPARE_51_BIT 51 114#define FEATURE_SPARE_52_BIT 52 115#define FEATURE_SPARE_53_BIT 53 116#define FEATURE_SPARE_54_BIT 54 117#define FEATURE_SPARE_55_BIT 55 118#define FEATURE_SPARE_56_BIT 56 119#define FEATURE_SPARE_57_BIT 57 120#define FEATURE_SPARE_58_BIT 58 121#define FEATURE_SPARE_59_BIT 59 122#define FEATURE_SPARE_60_BIT 60 123#define FEATURE_SPARE_61_BIT 61 124#define FEATURE_SPARE_62_BIT 62 125#define FEATURE_SPARE_63_BIT 63 126 127#define NUM_FEATURES 64 128 129 130#define FEATURE_DPM_PREFETCHER_MASK (1 << FEATURE_DPM_PREFETCHER_BIT ) 131#define FEATURE_DPM_GFXCLK_MASK (1 << FEATURE_DPM_GFXCLK_BIT ) 132#define FEATURE_DPM_UCLK_MASK (1 << FEATURE_DPM_UCLK_BIT ) 133#define FEATURE_DPM_SOCCLK_MASK (1 << FEATURE_DPM_SOCCLK_BIT ) 134#define FEATURE_DPM_FCLK_MASK (1 << FEATURE_DPM_FCLK_BIT ) 135#define FEATURE_DPM_MP0CLK_MASK (1 << FEATURE_DPM_MP0CLK_BIT ) 136#define FEATURE_DPM_XGMI_MASK (1 << FEATURE_DPM_XGMI_BIT ) 137 138#define FEATURE_DS_GFXCLK_MASK (1 << FEATURE_DS_GFXCLK_BIT ) 139#define FEATURE_DS_SOCCLK_MASK (1 << FEATURE_DS_SOCCLK_BIT ) 140#define FEATURE_DS_LCLK_MASK (1 << FEATURE_DS_LCLK_BIT ) 141#define FEATURE_DS_FCLK_MASK (1 << FEATURE_DS_FCLK_BIT ) 142#define FEATURE_DS_UCLK_MASK (1 << FEATURE_DS_UCLK_BIT ) 143#define FEATURE_GFX_ULV_MASK (1 << FEATURE_GFX_ULV_BIT ) 144#define FEATURE_DPM_VCN_MASK (1 << FEATURE_DPM_VCN_BIT ) 145#define FEATURE_RSMU_SMN_CG_MASK (1 << FEATURE_RSMU_SMN_CG_BIT ) 146#define FEATURE_WAFL_CG_MASK (1 << FEATURE_WAFL_CG_BIT ) 147 148#define FEATURE_PPT_MASK (1 << FEATURE_PPT_BIT ) 149#define FEATURE_TDC_MASK (1 << FEATURE_TDC_BIT ) 150#define FEATURE_APCC_PLUS_MASK (1 << FEATURE_APCC_PLUS_BIT ) 151#define FEATURE_VR0HOT_MASK (1 << FEATURE_VR0HOT_BIT ) 152#define FEATURE_VR1HOT_MASK (1 << FEATURE_VR1HOT_BIT ) 153#define FEATURE_FW_CTF_MASK (1 << FEATURE_FW_CTF_BIT ) 154#define FEATURE_FAN_CONTROL_MASK (1 << FEATURE_FAN_CONTROL_BIT ) 155#define FEATURE_THERMAL_MASK (1 << FEATURE_THERMAL_BIT ) 156 157#define FEATURE_OUT_OF_BAND_MONITOR_MASK (1 << FEATURE_OUT_OF_BAND_MONITOR_BIT ) 158#define FEATURE_TEMP_DEPENDENT_VMIN_MASK (1 << FEATURE_TEMP_DEPENDENT_VMIN_BIT ) 159 160 161//FIXME need updating 162// Debug Overrides Bitmask 163#define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000001 164#define DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK 0x00000002 165 166// I2C Config Bit Defines 167#define I2C_CONTROLLER_ENABLED 1 168#define I2C_CONTROLLER_DISABLED 0 169 170// VR Mapping Bit Defines 171#define VR_MAPPING_VR_SELECT_MASK 0x01 172#define VR_MAPPING_VR_SELECT_SHIFT 0x00 173 174#define VR_MAPPING_PLANE_SELECT_MASK 0x02 175#define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 176 177// PSI Bit Defines 178#define PSI_SEL_VR0_PLANE0_PSI0 0x01 179#define PSI_SEL_VR0_PLANE0_PSI1 0x02 180#define PSI_SEL_VR0_PLANE1_PSI0 0x04 181#define PSI_SEL_VR0_PLANE1_PSI1 0x08 182#define PSI_SEL_VR1_PLANE0_PSI0 0x10 183#define PSI_SEL_VR1_PLANE0_PSI1 0x20 184#define PSI_SEL_VR1_PLANE1_PSI0 0x40 185#define PSI_SEL_VR1_PLANE1_PSI1 0x80 186 187// Throttler Control/Status Bits 188#define THROTTLER_PADDING_BIT 0 189#define THROTTLER_TEMP_EDGE_BIT 1 190#define THROTTLER_TEMP_HOTSPOT_BIT 2 191#define THROTTLER_TEMP_MEM_BIT 3 192#define THROTTLER_TEMP_VR_GFX_BIT 4 193#define THROTTLER_TEMP_VR_MEM_BIT 5 194#define THROTTLER_TEMP_VR_SOC_BIT 6 195#define THROTTLER_TDC_GFX_BIT 7 196#define THROTTLER_TDC_SOC_BIT 8 197#define THROTTLER_PPT0_BIT 9 198#define THROTTLER_PPT1_BIT 10 199#define THROTTLER_PPT2_BIT 11 200#define THROTTLER_PPT3_BIT 12 201#define THROTTLER_PPM_BIT 13 202#define THROTTLER_FIT_BIT 14 203#define THROTTLER_APCC_BIT 15 204 205// Table transfer status 206#define TABLE_TRANSFER_OK 0x0 207#define TABLE_TRANSFER_FAILED 0xFF 208#define TABLE_TRANSFER_PENDING 0xAB 209 210// Workload bits 211#define WORKLOAD_PPLIB_DEFAULT_BIT 0 212#define WORKLOAD_PPLIB_POWER_SAVING_BIT 1 213#define WORKLOAD_PPLIB_VIDEO_BIT 2 214#define WORKLOAD_PPLIB_COMPUTE_BIT 3 215#define WORKLOAD_PPLIB_CUSTOM_BIT 4 216#define WORKLOAD_PPLIB_COUNT 5 217 218//XGMI performance states 219#define XGMI_STATE_D0 1 220#define XGMI_STATE_D3 0 221 222#define NUM_I2C_CONTROLLERS 8 223 224#define I2C_CONTROLLER_ENABLED 1 225#define I2C_CONTROLLER_DISABLED 0 226 227#define MAX_SW_I2C_COMMANDS 8 228 229typedef enum { 230 I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0 231 I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1 232 I2C_CONTROLLER_PORT_COUNT, 233} I2cControllerPort_e; 234 235typedef enum { 236 I2C_CONTROLLER_NAME_VR_GFX = 0, 237 I2C_CONTROLLER_NAME_VR_SOC, 238 I2C_CONTROLLER_NAME_VR_MEM, 239 I2C_CONTROLLER_NAME_SPARE, 240 I2C_CONTROLLER_NAME_COUNT, 241} I2cControllerName_e; 242 243typedef enum { 244 I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 245 I2C_CONTROLLER_THROTTLER_VR_GFX, 246 I2C_CONTROLLER_THROTTLER_VR_SOC, 247 I2C_CONTROLLER_THROTTLER_VR_MEM, 248 I2C_CONTROLLER_THROTTLER_COUNT, 249} I2cControllerThrottler_e; 250 251typedef enum { 252 I2C_CONTROLLER_PROTOCOL_VR_0, 253 I2C_CONTROLLER_PROTOCOL_VR_1, 254 I2C_CONTROLLER_PROTOCOL_TMP_0, 255 I2C_CONTROLLER_PROTOCOL_TMP_1, 256 I2C_CONTROLLER_PROTOCOL_SPARE_0, 257 I2C_CONTROLLER_PROTOCOL_SPARE_1, 258 I2C_CONTROLLER_PROTOCOL_COUNT, 259} I2cControllerProtocol_e; 260 261typedef struct { 262 uint8_t Enabled; 263 uint8_t Speed; 264 uint8_t Padding[2]; 265 uint32_t SlaveAddress; 266 uint8_t ControllerPort; 267 uint8_t ControllerName; 268 uint8_t ThermalThrotter; 269 uint8_t I2cProtocol; 270} I2cControllerConfig_t; 271 272typedef enum { 273 I2C_PORT_SVD_SCL = 0, 274 I2C_PORT_GPIO, 275} I2cPort_e; 276 277typedef enum { 278 I2C_SPEED_FAST_50K = 0, //50 Kbits/s 279 I2C_SPEED_FAST_100K, //100 Kbits/s 280 I2C_SPEED_FAST_400K, //400 Kbits/s 281 I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 282 I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) 283 I2C_SPEED_HIGH_2M, //2.3 Mbits/s 284 I2C_SPEED_COUNT, 285} I2cSpeed_e; 286 287typedef enum { 288 I2C_CMD_READ = 0, 289 I2C_CMD_WRITE, 290 I2C_CMD_COUNT, 291} I2cCmdType_e; 292 293#define CMDCONFIG_STOP_BIT 0 294#define CMDCONFIG_RESTART_BIT 1 295 296#define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 297#define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 298 299typedef struct { 300 uint8_t RegisterAddr; ////only valid for write, ignored for read 301 uint8_t Cmd; //Read(0) or Write(1) 302 uint8_t Data; //Return data for read. Data to send for write 303 uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command 304} SwI2cCmd_t; //SW I2C Command Table 305 306typedef struct { 307 uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 308 uint8_t I2CSpeed; //Slow(0) or Fast(1) 309 uint16_t SlaveAddress; 310 uint8_t NumCmds; //Number of commands 311 uint8_t Padding[3]; 312 313 SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 314 315 uint32_t MmHubPadding[8]; // SMU internal use 316 317} SwI2cRequest_t; // SW I2C Request Table 318 319//D3HOT sequences 320typedef enum { 321 BACO_SEQUENCE, 322 MSR_SEQUENCE, 323 BAMACO_SEQUENCE, 324 ULPS_SEQUENCE, 325 D3HOT_SEQUENCE_COUNT, 326}D3HOTSequence_e; 327 328//THis is aligned with RSMU PGFSM Register Mapping 329typedef enum { 330 PG_DYNAMIC_MODE = 0, 331 PG_STATIC_MODE, 332} PowerGatingMode_e; 333 334//This is aligned with RSMU PGFSM Register Mapping 335typedef enum { 336 PG_POWER_DOWN = 0, 337 PG_POWER_UP, 338} PowerGatingSettings_e; 339 340typedef struct { 341 uint32_t a; // store in IEEE float format in this variable 342 uint32_t b; // store in IEEE float format in this variable 343 uint32_t c; // store in IEEE float format in this variable 344} QuadraticInt_t; 345 346typedef struct { 347 uint32_t m; // store in IEEE float format in this variable 348 uint32_t b; // store in IEEE float format in this variable 349} LinearInt_t; 350 351typedef struct { 352 uint32_t a; // store in IEEE float format in this variable 353 uint32_t b; // store in IEEE float format in this variable 354 uint32_t c; // store in IEEE float format in this variable 355} DroopInt_t; 356 357typedef enum { 358 GFXCLK_SOURCE_PLL = 0, 359 GFXCLK_SOURCE_AFLL, 360 GFXCLK_SOURCE_COUNT, 361} GfxclkSrc_e; 362 363typedef enum { 364 PPCLK_GFXCLK, 365 PPCLK_VCLK, 366 PPCLK_DCLK, 367 PPCLK_SOCCLK, 368 PPCLK_UCLK, 369 PPCLK_FCLK, 370 PPCLK_COUNT, 371} PPCLK_e; 372 373typedef enum { 374 POWER_SOURCE_AC, 375 POWER_SOURCE_DC, 376 POWER_SOURCE_COUNT, 377} POWER_SOURCE_e; 378 379typedef enum { 380 TEMP_EDGE, 381 TEMP_HOTSPOT, 382 TEMP_MEM, 383 TEMP_VR_GFX, 384 TEMP_VR_SOC, 385 TEMP_VR_MEM, 386 TEMP_COUNT 387} TEMP_TYPE_e; 388 389typedef enum { 390 PPT_THROTTLER_PPT0, 391 PPT_THROTTLER_PPT1, 392 PPT_THROTTLER_PPT2, 393 PPT_THROTTLER_PPT3, 394 PPT_THROTTLER_COUNT 395} PPT_THROTTLER_e; 396 397typedef enum { 398 VOLTAGE_MODE_AVFS = 0, 399 VOLTAGE_MODE_AVFS_SS, 400 VOLTAGE_MODE_SS, 401 VOLTAGE_MODE_COUNT, 402} VOLTAGE_MODE_e; 403 404typedef enum { 405 AVFS_VOLTAGE_GFX = 0, 406 AVFS_VOLTAGE_SOC, 407 AVFS_VOLTAGE_COUNT, 408} AVFS_VOLTAGE_TYPE_e; 409 410typedef enum { 411 GPIO_INT_POLARITY_ACTIVE_LOW = 0, 412 GPIO_INT_POLARITY_ACTIVE_HIGH, 413} GpioIntPolarity_e; 414 415typedef enum { 416 MEMORY_TYPE_GDDR6 = 0, 417 MEMORY_TYPE_HBM, 418} MemoryType_e; 419 420typedef enum { 421 PWR_CONFIG_TDP = 0, 422 PWR_CONFIG_TGP, 423 PWR_CONFIG_TCP_ESTIMATED, 424 PWR_CONFIG_TCP_MEASURED, 425} PwrConfig_e; 426 427typedef enum { 428 XGMI_LINK_RATE_2 = 2, // 2Gbps 429 XGMI_LINK_RATE_4 = 4, // 4Gbps 430 XGMI_LINK_RATE_8 = 8, // 8Gbps 431 XGMI_LINK_RATE_12 = 12, // 12Gbps 432 XGMI_LINK_RATE_16 = 16, // 16Gbps 433 XGMI_LINK_RATE_17 = 17, // 17Gbps 434 XGMI_LINK_RATE_18 = 18, // 18Gbps 435 XGMI_LINK_RATE_19 = 19, // 19Gbps 436 XGMI_LINK_RATE_20 = 20, // 20Gbps 437 XGMI_LINK_RATE_21 = 21, // 21Gbps 438 XGMI_LINK_RATE_22 = 22, // 22Gbps 439 XGMI_LINK_RATE_23 = 23, // 23Gbps 440 XGMI_LINK_RATE_24 = 24, // 24Gbps 441 XGMI_LINK_RATE_25 = 25, // 25Gbps 442 XGMI_LINK_RATE_COUNT 443} XGMI_LINK_RATE_e; 444 445typedef enum { 446 XGMI_LINK_WIDTH_1 = 1, // x1 447 XGMI_LINK_WIDTH_2 = 2, // x2 448 XGMI_LINK_WIDTH_4 = 4, // x4 449 XGMI_LINK_WIDTH_8 = 8, // x8 450 XGMI_LINK_WIDTH_9 = 9, // x9 451 XGMI_LINK_WIDTH_16 = 16, // x16 452 XGMI_LINK_WIDTH_COUNT 453} XGMI_LINK_WIDTH_e; 454 455typedef struct { 456 uint8_t VoltageMode; // 0 - AVFS only, 1- min(AVFS,SS), 2-SS only 457 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM 458 uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used 459 uint8_t padding; 460 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 461 QuadraticInt_t SsCurve; // Slow-slow curve (GHz->V) 462 uint16_t SsFmin; // Fmin for SS curve. If SS curve is selected, will use V@SSFmin for F <= Fmin 463 uint16_t Padding16; 464} DpmDescriptor_t; 465 466typedef struct { 467 uint32_t Version; 468 469 // SECTION: Feature Enablement 470 uint32_t FeaturesToRun[2]; 471 472 // SECTION: Infrastructure Limits 473 uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; 474 uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; 475 uint16_t TdcLimitSoc; // Amps 476 uint16_t TdcLimitSocTau; // Time constant of LPF in ms 477 uint16_t TdcLimitGfx; // Amps 478 uint16_t TdcLimitGfxTau; // Time constant of LPF in ms 479 480 uint16_t TedgeLimit; // Celcius 481 uint16_t ThotspotLimit; // Celcius 482 uint16_t TmemLimit; // Celcius 483 uint16_t Tvr_gfxLimit; // Celcius 484 uint16_t Tvr_memLimit; // Celcius 485 uint16_t Tvr_socLimit; // Celcius 486 uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime) 487 488 uint16_t PpmPowerLimit; // Switch this this power limit when temperature is above PpmTempThreshold 489 uint16_t PpmTemperatureThreshold; 490 491 // SECTION: Throttler settings 492 uint32_t ThrottlerControlMask; // See Throtter masks defines 493 494 // SECTION: ULV Settings 495 uint16_t UlvVoltageOffsetGfx; // In mV(Q2) 496 uint16_t UlvPadding; // Padding 497 498 uint8_t UlvGfxclkBypass; // 1 to turn off/bypass Gfxclk during ULV, 0 to leave Gfxclk on during ULV 499 uint8_t Padding234[3]; 500 501 // SECTION: Voltage Control Parameters 502 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX 503 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC 504 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX 505 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC 506 507 uint16_t LoadLineResistanceGfx; // In mOhms with 8 fractional bits 508 uint16_t LoadLineResistanceSoc; // In mOhms with 8 fractional bits 509 510 //SECTION: DPM Config 1 511 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 512 513 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 514 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 515 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 516 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 517 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 518 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 519 520 uint32_t Paddingclks[16]; 521 522 // SECTION: DPM Config 2 523 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz 524 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) 525 526 // GFXCLK DPM 527 uint16_t GfxclkFidle; // In MHz 528 uint16_t GfxclkSlewRate; // for PLL babystepping??? 529 uint8_t Padding567[4]; 530 uint16_t GfxclkDsMaxFreq; // In MHz 531 uint8_t GfxclkSource; // 0 = PLL, 1 = AFLL 532 uint8_t Padding456; 533 534 // GFXCLK Thermal DPM (formerly 'Boost' Settings) 535 uint16_t EnableTdpm; 536 uint16_t TdpmHighHystTemperature; 537 uint16_t TdpmLowHystTemperature; 538 uint16_t GfxclkFreqHighTempLimit; // High limit on GFXCLK when temperature is high, for reliability. 539 540 // SECTION: Fan Control 541 uint16_t FanStopTemp; //Celcius 542 uint16_t FanStartTemp; //Celcius 543 544 uint16_t FanGainEdge; 545 uint16_t FanGainHotspot; 546 uint16_t FanGainVrGfx; 547 uint16_t FanGainVrSoc; 548 uint16_t FanGainVrMem; 549 uint16_t FanGainHbm; 550 uint16_t FanPwmMin; 551 uint16_t FanAcousticLimitRpm; 552 uint16_t FanThrottlingRpm; 553 uint16_t FanMaximumRpm; 554 uint16_t FanTargetTemperature; 555 uint16_t FanTargetGfxclk; 556 uint8_t FanZeroRpmEnable; 557 uint8_t FanTachEdgePerRev; 558 uint8_t FanTempInputSelect; 559 uint8_t padding8_Fan; 560 561 // The following are AFC override parameters. Leave at 0 to use FW defaults. 562 int16_t FuzzyFan_ErrorSetDelta; 563 int16_t FuzzyFan_ErrorRateSetDelta; 564 int16_t FuzzyFan_PwmSetDelta; 565 uint16_t FuzzyFan_Reserved; 566 567 568 // SECTION: AVFS 569 // Overrides 570 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 571 uint8_t Padding8_Avfs[2]; 572 573 QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve 574 DroopInt_t dBtcGbGfxPll; // GHz->V BtcGb 575 DroopInt_t dBtcGbGfxAfll; // GHz->V BtcGb 576 DroopInt_t dBtcGbSoc; // GHz->V BtcGb 577 LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V 578 579 QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V 580 581 uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2 582 583 uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT]; 584 uint8_t Padding8_GfxBtc[2]; 585 586 uint16_t DcBtcMin[AVFS_VOLTAGE_COUNT]; // mV Q2 587 uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT]; // mV Q2 588 589 uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT]; // mV Q2 590 591 // SECTION: XGMI 592 uint8_t XgmiDpmPstates[NUM_XGMI_LEVELS]; // 2 DPM states, high and low. 0-P0, 1-P1, 2-P2, 3-P3. 593 uint8_t XgmiDpmSpare[2]; 594 595 // Temperature Dependent Vmin 596 uint16_t VDDGFX_TVmin; //Celcius 597 uint16_t VDDSOC_TVmin; //Celcius 598 uint16_t VDDGFX_Vmin_HiTemp; // mV Q2 599 uint16_t VDDGFX_Vmin_LoTemp; // mV Q2 600 uint16_t VDDSOC_Vmin_HiTemp; // mV Q2 601 uint16_t VDDSOC_Vmin_LoTemp; // mV Q2 602 603 uint16_t VDDGFX_TVminHystersis; // Celcius 604 uint16_t VDDSOC_TVminHystersis; // Celcius 605 606 607 // SECTION: Advanced Options 608 uint32_t DebugOverrides; 609 QuadraticInt_t ReservedEquation0; 610 QuadraticInt_t ReservedEquation1; 611 QuadraticInt_t ReservedEquation2; 612 QuadraticInt_t ReservedEquation3; 613 614 uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode 615 uint16_t PaddingUlv; // Padding 616 617 // Total Power configuration, use defines from PwrConfig_e 618 uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured 619 uint8_t TotalPowerSpare1; 620 uint16_t TotalPowerSpare2; 621 622 // APCC Settings 623 uint16_t PccThresholdLow; 624 uint16_t PccThresholdHigh; 625 uint32_t PaddingAPCC[6]; //FIXME pending SPEC 626 627 // OOB Settings 628 uint16_t BasePerformanceCardPower; 629 uint16_t MaxPerformanceCardPower; 630 uint16_t BasePerformanceFrequencyCap; //In Mhz 631 uint16_t MaxPerformanceFrequencyCap; //In Mhz 632 633 // SECTION: Reserved 634 uint32_t Reserved[9]; 635 636 // SECTION: BOARD PARAMETERS 637 638 // SVI2 Board Parameters 639 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 640 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 641 642 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 643 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 644 uint8_t VddMemVrMapping; // Use VR_MAPPING* bitfields 645 uint8_t BoardVrMapping; // Use VR_MAPPING* bitfields 646 647 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 648 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN) 649 uint8_t Padding8_V[2]; 650 651 // Telemetry Settings 652 uint16_t GfxMaxCurrent; // in Amps 653 int8_t GfxOffset; // in Amps 654 uint8_t Padding_TelemetryGfx; 655 656 uint16_t SocMaxCurrent; // in Amps 657 int8_t SocOffset; // in Amps 658 uint8_t Padding_TelemetrySoc; 659 660 uint16_t MemMaxCurrent; // in Amps 661 int8_t MemOffset; // in Amps 662 uint8_t Padding_TelemetryMem; 663 664 uint16_t BoardMaxCurrent; // in Amps 665 int8_t BoardOffset; // in Amps 666 uint8_t Padding_TelemetryBoardInput; 667 668 // GPIO Settings 669 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 670 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 671 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 672 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 673 674 // GFXCLK PLL Spread Spectrum 675 uint8_t PllGfxclkSpreadEnabled; // on or off 676 uint8_t PllGfxclkSpreadPercent; // Q4.4 677 uint16_t PllGfxclkSpreadFreq; // kHz 678 679 // UCLK Spread Spectrum 680 uint8_t UclkSpreadEnabled; // on or off 681 uint8_t UclkSpreadPercent; // Q4.4 682 uint16_t UclkSpreadFreq; // kHz 683 684 // FCLK Spread Spectrum 685 uint8_t FclkSpreadEnabled; // on or off 686 uint8_t FclkSpreadPercent; // Q4.4 687 uint16_t FclkSpreadFreq; // kHz 688 689 // GFXCLK Fll Spread Spectrum 690 uint8_t FllGfxclkSpreadEnabled; // on or off 691 uint8_t FllGfxclkSpreadPercent; // Q4.4 692 uint16_t FllGfxclkSpreadFreq; // kHz 693 694 // I2C Controller Structure 695 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 696 697 // Memory section 698 uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. 699 700 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines 701 uint8_t PaddingMem[3]; 702 703 // Total board power 704 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 705 uint16_t BoardPadding; 706 707 // SECTION: XGMI Training 708 uint8_t XgmiLinkSpeed [NUM_XGMI_PSTATE_LEVELS]; 709 uint8_t XgmiLinkWidth [NUM_XGMI_PSTATE_LEVELS]; 710 711 uint16_t XgmiFclkFreq [NUM_XGMI_PSTATE_LEVELS]; 712 uint16_t XgmiSocVoltage [NUM_XGMI_PSTATE_LEVELS]; 713 714 // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence 715 uint8_t GpioI2cScl; // Serial Clock 716 uint8_t GpioI2cSda; // Serial Data 717 uint16_t GpioPadding; 718 719 // Platform input telemetry voltage coefficient 720 uint32_t BoardVoltageCoeffA; // decode by /1000 721 uint32_t BoardVoltageCoeffB; // decode by /1000 722 723 uint32_t BoardReserved[7]; 724 725 // Padding for MMHUB - do not modify this 726 uint32_t MmHubPadding[8]; // SMU internal use 727 728} PPTable_t; 729 730typedef struct { 731 // Time constant parameters for clock averages in ms 732 uint16_t GfxclkAverageLpfTau; 733 uint16_t SocclkAverageLpfTau; 734 uint16_t UclkAverageLpfTau; 735 uint16_t GfxActivityLpfTau; 736 uint16_t UclkActivityLpfTau; 737 738 uint16_t SocketPowerLpfTau; 739 740 // Padding - ignore 741 uint32_t MmHubPadding[8]; // SMU internal use 742} DriverSmuConfig_t; 743 744typedef struct { 745 uint16_t CurrClock[PPCLK_COUNT]; 746 uint16_t AverageGfxclkFrequency; 747 uint16_t AverageSocclkFrequency; 748 uint16_t AverageUclkFrequency ; 749 uint16_t AverageGfxActivity ; 750 uint16_t AverageUclkActivity ; 751 uint8_t CurrSocVoltageOffset ; 752 uint8_t CurrGfxVoltageOffset ; 753 uint8_t CurrMemVidOffset ; 754 uint8_t Padding8 ; 755 uint16_t AverageSocketPower ; 756 uint16_t TemperatureEdge ; 757 uint16_t TemperatureHotspot ; 758 uint16_t TemperatureHBM ; 759 uint16_t TemperatureVrGfx ; 760 uint16_t TemperatureVrSoc ; 761 uint16_t TemperatureVrMem ; 762 uint32_t ThrottlerStatus ; 763 764 uint16_t CurrFanSpeed ; 765 uint16_t Padding16; 766 767 uint32_t Padding[4]; 768 769 // Padding - ignore 770 uint32_t MmHubPadding[8]; // SMU internal use 771} SmuMetrics_t; 772 773 774typedef struct { 775 uint16_t avgPsmCount[75]; 776 uint16_t minPsmCount[75]; 777 float avgPsmVoltage[75]; 778 float minPsmVoltage[75]; 779 780 uint32_t MmHubPadding[8]; // SMU internal use 781} AvfsDebugTable_t; 782 783typedef struct { 784 uint8_t AvfsVersion; 785 uint8_t Padding; 786 uint8_t AvfsEn[AVFS_VOLTAGE_COUNT]; 787 788 uint8_t OverrideVFT[AVFS_VOLTAGE_COUNT]; 789 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 790 791 uint8_t OverrideTemperatures[AVFS_VOLTAGE_COUNT]; 792 uint8_t OverrideVInversion[AVFS_VOLTAGE_COUNT]; 793 uint8_t OverrideP2V[AVFS_VOLTAGE_COUNT]; 794 uint8_t OverrideP2VCharzFreq[AVFS_VOLTAGE_COUNT]; 795 796 int32_t VFT0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 797 int32_t VFT0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 798 int32_t VFT0_b[AVFS_VOLTAGE_COUNT]; // Q32 799 800 int32_t VFT1_m1[AVFS_VOLTAGE_COUNT]; // Q8.16 801 int32_t VFT1_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 802 int32_t VFT1_b[AVFS_VOLTAGE_COUNT]; // Q32 803 804 int32_t VFT2_m1[AVFS_VOLTAGE_COUNT]; // Q8.16 805 int32_t VFT2_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 806 int32_t VFT2_b[AVFS_VOLTAGE_COUNT]; // Q32 807 808 int32_t AvfsGb0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 809 int32_t AvfsGb0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 810 int32_t AvfsGb0_b[AVFS_VOLTAGE_COUNT]; // Q32 811 812 int32_t AcBtcGb_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 813 int32_t AcBtcGb_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 814 int32_t AcBtcGb_b[AVFS_VOLTAGE_COUNT]; // Q32 815 816 uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT]; 817 uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT]; 818 uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT]; 819 820 uint32_t VInversion[AVFS_VOLTAGE_COUNT]; // in mV with 2 fractional bits 821 822 823 int32_t P2V_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 824 int32_t P2V_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 825 int32_t P2V_b[AVFS_VOLTAGE_COUNT]; // Q32 826 827 uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; // in 10KHz units 828 829 uint32_t EnabledAvfsModules[3]; 830 831 uint32_t MmHubPadding[8]; // SMU internal use 832} AvfsFuseOverride_t; 833 834typedef struct { 835 uint8_t Gfx_ActiveHystLimit; 836 uint8_t Gfx_IdleHystLimit; 837 uint8_t Gfx_FPS; 838 uint8_t Gfx_MinActiveFreqType; 839 uint8_t Gfx_BoosterFreqType; 840 uint8_t Gfx_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 841 uint8_t Gfx_UseRlcBusy; 842 uint8_t PaddingGfx[3]; 843 uint16_t Gfx_MinActiveFreq; // MHz 844 uint16_t Gfx_BoosterFreq; // MHz 845 uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms 846 uint32_t Gfx_PD_Data_limit_a; // Q16 847 uint32_t Gfx_PD_Data_limit_b; // Q16 848 uint32_t Gfx_PD_Data_limit_c; // Q16 849 uint32_t Gfx_PD_Data_error_coeff; // Q16 850 uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 851 852 uint8_t Mem_ActiveHystLimit; 853 uint8_t Mem_IdleHystLimit; 854 uint8_t Mem_FPS; 855 uint8_t Mem_MinActiveFreqType; 856 uint8_t Mem_BoosterFreqType; 857 uint8_t Mem_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 858 uint8_t Mem_UseRlcBusy; 859 uint8_t PaddingMem[3]; 860 uint16_t Mem_MinActiveFreq; // MHz 861 uint16_t Mem_BoosterFreq; // MHz 862 uint16_t Mem_PD_Data_time_constant; // Time constant of PD controller in ms 863 uint32_t Mem_PD_Data_limit_a; // Q16 864 uint32_t Mem_PD_Data_limit_b; // Q16 865 uint32_t Mem_PD_Data_limit_c; // Q16 866 uint32_t Mem_PD_Data_error_coeff; // Q16 867 uint32_t Mem_PD_Data_error_rate_coeff; // Q16 868 869 uint32_t Mem_UpThreshold_Limit; // Q16 870 uint8_t Mem_UpHystLimit; 871 uint8_t Mem_DownHystLimit; 872 uint16_t Mem_Fps; 873 874 uint32_t MmHubPadding[8]; // SMU internal use 875} DpmActivityMonitorCoeffInt_t; 876 877// These defines are used with the following messages: 878// SMC_MSG_TransferTableDram2Smu 879// SMC_MSG_TransferTableSmu2Dram 880#define TABLE_PPTABLE 0 881#define TABLE_AVFS 1 882#define TABLE_AVFS_PSM_DEBUG 2 883#define TABLE_AVFS_FUSE_OVERRIDE 3 884#define TABLE_PMSTATUSLOG 4 885#define TABLE_SMU_METRICS 5 886#define TABLE_DRIVER_SMU_CONFIG 6 887#define TABLE_OVERDRIVE 7 888#define TABLE_WAFL_XGMI_TOPOLOGY 8 889#define TABLE_I2C_COMMANDS 9 890#define TABLE_ACTIVITY_MONITOR_COEFF 10 891#define TABLE_COUNT 11 892 893// These defines are used with the SMC_MSG_SetUclkFastSwitch message. 894typedef enum { 895 DF_SWITCH_TYPE_FAST = 0, 896 DF_SWITCH_TYPE_SLOW, 897 DF_SWITCH_TYPE_COUNT, 898} DF_SWITCH_TYPE_e; 899 900typedef enum { 901 DRAM_BIT_WIDTH_DISABLED = 0, 902 DRAM_BIT_WIDTH_X_8, 903 DRAM_BIT_WIDTH_X_16, 904 DRAM_BIT_WIDTH_X_32, 905 DRAM_BIT_WIDTH_X_64, // NOT USED. 906 DRAM_BIT_WIDTH_X_128, 907 DRAM_BIT_WIDTH_COUNT, 908} DRAM_BIT_WIDTH_TYPE_e; 909 910#define REMOVE_FMAX_MARGIN_BIT 0x0 911#define REMOVE_DCTOL_MARGIN_BIT 0x1 912#define REMOVE_PLATFORM_MARGIN_BIT 0x2 913 914#endif 915