1/* $NetBSD: soc15_hw_ip.h,v 1.2 2021/12/18 23:45:08 riastradh Exp $ */ 2 3/* 4 * Copyright (C) 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#ifndef _soc15_hw_ip_HEADER 24#define _soc15_hw_ip_HEADER 25 26// HW ID 27#define MP1_HWID 1 28#define MP2_HWID 2 29#define THM_HWID 3 30#define SMUIO_HWID 4 31#define FUSE_HWID 5 32#define CLKA_HWID 6 33#define PWR_HWID 10 34#define GC_HWID 11 35#define UVD_HWID 12 36#define VCN_HWID UVD_HWID 37#define AUDIO_AZ_HWID 13 38#define ACP_HWID 14 39#define DCI_HWID 15 40#define DMU_HWID 271 41#define DCO_HWID 16 42#define DIO_HWID 272 43#define XDMA_HWID 17 44#define DCEAZ_HWID 18 45#define DAZ_HWID 274 46#define SDPMUX_HWID 19 47#define NTB_HWID 20 48#define IOHC_HWID 24 49#define L2IMU_HWID 28 50#define VCE_HWID 32 51#define MMHUB_HWID 34 52#define ATHUB_HWID 35 53#define DBGU_NBIO_HWID 36 54#define DFX_HWID 37 55#define DBGU0_HWID 38 56#define DBGU1_HWID 39 57#define OSSSYS_HWID 40 58#define HDP_HWID 41 59#define SDMA0_HWID 42 60#define SDMA1_HWID 43 61#define ISP_HWID 44 62#define DBGU_IO_HWID 45 63#define DF_HWID 46 64#define CLKB_HWID 47 65#define FCH_HWID 48 66#define DFX_DAP_HWID 49 67#define L1IMU_PCIE_HWID 50 68#define L1IMU_NBIF_HWID 51 69#define L1IMU_IOAGR_HWID 52 70#define L1IMU3_HWID 53 71#define L1IMU4_HWID 54 72#define L1IMU5_HWID 55 73#define L1IMU6_HWID 56 74#define L1IMU7_HWID 57 75#define L1IMU8_HWID 58 76#define L1IMU9_HWID 59 77#define L1IMU10_HWID 60 78#define L1IMU11_HWID 61 79#define L1IMU12_HWID 62 80#define L1IMU13_HWID 63 81#define L1IMU14_HWID 64 82#define L1IMU15_HWID 65 83#define WAFLC_HWID 66 84#define FCH_USB_PD_HWID 67 85#define PCIE_HWID 70 86#define PCS_HWID 80 87#define DDCL_HWID 89 88#define SST_HWID 90 89#define IOAGR_HWID 100 90#define NBIF_HWID 108 91#define IOAPIC_HWID 124 92#define SYSTEMHUB_HWID 128 93#define NTBCCP_HWID 144 94#define UMC_HWID 150 95#define SATA_HWID 168 96#define USB_HWID 170 97#define CCXSEC_HWID 176 98#define XGMI_HWID 200 99#define XGBE_HWID 216 100#define MP0_HWID 255 101 102#endif 103