1/* $NetBSD: uvd_6_0_enum.h,v 1.3 2021/12/18 23:45:24 riastradh Exp $ */ 2 3/* 4 * UVD_6_0 Register documentation 5 * 6 * Copyright (C) 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included 16 * in all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 22 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26#ifndef UVD_6_0_ENUM_H 27#define UVD_6_0_ENUM_H 28 29typedef enum UVDFirmwareCommand { 30 UVDFC_FENCE = 0x0, 31 UVDFC_TRAP = 0x1, 32 UVDFC_DECODED_ADDR = 0x2, 33 UVDFC_MBLOCK_ADDR = 0x3, 34 UVDFC_ITBUF_ADDR = 0x4, 35 UVDFC_DISPLAY_ADDR = 0x5, 36 UVDFC_EOD = 0x6, 37 UVDFC_DISPLAY_PITCH = 0x7, 38 UVDFC_DISPLAY_TILING = 0x8, 39 UVDFC_BITSTREAM_ADDR = 0x9, 40 UVDFC_BITSTREAM_SIZE = 0xa, 41} UVDFirmwareCommand; 42typedef enum DebugBlockId { 43 DBG_BLOCK_ID_RESERVED = 0x0, 44 DBG_BLOCK_ID_DBG = 0x1, 45 DBG_BLOCK_ID_VMC = 0x2, 46 DBG_BLOCK_ID_PDMA = 0x3, 47 DBG_BLOCK_ID_CG = 0x4, 48 DBG_BLOCK_ID_SRBM = 0x5, 49 DBG_BLOCK_ID_GRBM = 0x6, 50 DBG_BLOCK_ID_RLC = 0x7, 51 DBG_BLOCK_ID_CSC = 0x8, 52 DBG_BLOCK_ID_SEM = 0x9, 53 DBG_BLOCK_ID_IH = 0xa, 54 DBG_BLOCK_ID_SC = 0xb, 55 DBG_BLOCK_ID_SQ = 0xc, 56 DBG_BLOCK_ID_UVDU = 0xd, 57 DBG_BLOCK_ID_SQA = 0xe, 58 DBG_BLOCK_ID_SDMA0 = 0xf, 59 DBG_BLOCK_ID_SDMA1 = 0x10, 60 DBG_BLOCK_ID_SPIM = 0x11, 61 DBG_BLOCK_ID_GDS = 0x12, 62 DBG_BLOCK_ID_VC0 = 0x13, 63 DBG_BLOCK_ID_VC1 = 0x14, 64 DBG_BLOCK_ID_PA0 = 0x15, 65 DBG_BLOCK_ID_PA1 = 0x16, 66 DBG_BLOCK_ID_CP0 = 0x17, 67 DBG_BLOCK_ID_CP1 = 0x18, 68 DBG_BLOCK_ID_CP2 = 0x19, 69 DBG_BLOCK_ID_XBR = 0x1a, 70 DBG_BLOCK_ID_UVDM = 0x1b, 71 DBG_BLOCK_ID_VGT0 = 0x1c, 72 DBG_BLOCK_ID_VGT1 = 0x1d, 73 DBG_BLOCK_ID_IA = 0x1e, 74 DBG_BLOCK_ID_SXM0 = 0x1f, 75 DBG_BLOCK_ID_SXM1 = 0x20, 76 DBG_BLOCK_ID_SCT0 = 0x21, 77 DBG_BLOCK_ID_SCT1 = 0x22, 78 DBG_BLOCK_ID_SPM0 = 0x23, 79 DBG_BLOCK_ID_SPM1 = 0x24, 80 DBG_BLOCK_ID_UNUSED0 = 0x25, 81 DBG_BLOCK_ID_UNUSED1 = 0x26, 82 DBG_BLOCK_ID_TCAA = 0x27, 83 DBG_BLOCK_ID_TCAB = 0x28, 84 DBG_BLOCK_ID_TCCA = 0x29, 85 DBG_BLOCK_ID_TCCB = 0x2a, 86 DBG_BLOCK_ID_MCC0 = 0x2b, 87 DBG_BLOCK_ID_MCC1 = 0x2c, 88 DBG_BLOCK_ID_MCC2 = 0x2d, 89 DBG_BLOCK_ID_MCC3 = 0x2e, 90 DBG_BLOCK_ID_SXS0 = 0x2f, 91 DBG_BLOCK_ID_SXS1 = 0x30, 92 DBG_BLOCK_ID_SXS2 = 0x31, 93 DBG_BLOCK_ID_SXS3 = 0x32, 94 DBG_BLOCK_ID_SXS4 = 0x33, 95 DBG_BLOCK_ID_SXS5 = 0x34, 96 DBG_BLOCK_ID_SXS6 = 0x35, 97 DBG_BLOCK_ID_SXS7 = 0x36, 98 DBG_BLOCK_ID_SXS8 = 0x37, 99 DBG_BLOCK_ID_SXS9 = 0x38, 100 DBG_BLOCK_ID_BCI0 = 0x39, 101 DBG_BLOCK_ID_BCI1 = 0x3a, 102 DBG_BLOCK_ID_BCI2 = 0x3b, 103 DBG_BLOCK_ID_BCI3 = 0x3c, 104 DBG_BLOCK_ID_MCB = 0x3d, 105 DBG_BLOCK_ID_UNUSED6 = 0x3e, 106 DBG_BLOCK_ID_SQA00 = 0x3f, 107 DBG_BLOCK_ID_SQA01 = 0x40, 108 DBG_BLOCK_ID_SQA02 = 0x41, 109 DBG_BLOCK_ID_SQA10 = 0x42, 110 DBG_BLOCK_ID_SQA11 = 0x43, 111 DBG_BLOCK_ID_SQA12 = 0x44, 112 DBG_BLOCK_ID_UNUSED7 = 0x45, 113 DBG_BLOCK_ID_UNUSED8 = 0x46, 114 DBG_BLOCK_ID_SQB00 = 0x47, 115 DBG_BLOCK_ID_SQB01 = 0x48, 116 DBG_BLOCK_ID_SQB10 = 0x49, 117 DBG_BLOCK_ID_SQB11 = 0x4a, 118 DBG_BLOCK_ID_SQ00 = 0x4b, 119 DBG_BLOCK_ID_SQ01 = 0x4c, 120 DBG_BLOCK_ID_SQ10 = 0x4d, 121 DBG_BLOCK_ID_SQ11 = 0x4e, 122 DBG_BLOCK_ID_CB00 = 0x4f, 123 DBG_BLOCK_ID_CB01 = 0x50, 124 DBG_BLOCK_ID_CB02 = 0x51, 125 DBG_BLOCK_ID_CB03 = 0x52, 126 DBG_BLOCK_ID_CB04 = 0x53, 127 DBG_BLOCK_ID_UNUSED9 = 0x54, 128 DBG_BLOCK_ID_UNUSED10 = 0x55, 129 DBG_BLOCK_ID_UNUSED11 = 0x56, 130 DBG_BLOCK_ID_CB10 = 0x57, 131 DBG_BLOCK_ID_CB11 = 0x58, 132 DBG_BLOCK_ID_CB12 = 0x59, 133 DBG_BLOCK_ID_CB13 = 0x5a, 134 DBG_BLOCK_ID_CB14 = 0x5b, 135 DBG_BLOCK_ID_UNUSED12 = 0x5c, 136 DBG_BLOCK_ID_UNUSED13 = 0x5d, 137 DBG_BLOCK_ID_UNUSED14 = 0x5e, 138 DBG_BLOCK_ID_TCP0 = 0x5f, 139 DBG_BLOCK_ID_TCP1 = 0x60, 140 DBG_BLOCK_ID_TCP2 = 0x61, 141 DBG_BLOCK_ID_TCP3 = 0x62, 142 DBG_BLOCK_ID_TCP4 = 0x63, 143 DBG_BLOCK_ID_TCP5 = 0x64, 144 DBG_BLOCK_ID_TCP6 = 0x65, 145 DBG_BLOCK_ID_TCP7 = 0x66, 146 DBG_BLOCK_ID_TCP8 = 0x67, 147 DBG_BLOCK_ID_TCP9 = 0x68, 148 DBG_BLOCK_ID_TCP10 = 0x69, 149 DBG_BLOCK_ID_TCP11 = 0x6a, 150 DBG_BLOCK_ID_TCP12 = 0x6b, 151 DBG_BLOCK_ID_TCP13 = 0x6c, 152 DBG_BLOCK_ID_TCP14 = 0x6d, 153 DBG_BLOCK_ID_TCP15 = 0x6e, 154 DBG_BLOCK_ID_TCP16 = 0x6f, 155 DBG_BLOCK_ID_TCP17 = 0x70, 156 DBG_BLOCK_ID_TCP18 = 0x71, 157 DBG_BLOCK_ID_TCP19 = 0x72, 158 DBG_BLOCK_ID_TCP20 = 0x73, 159 DBG_BLOCK_ID_TCP21 = 0x74, 160 DBG_BLOCK_ID_TCP22 = 0x75, 161 DBG_BLOCK_ID_TCP23 = 0x76, 162 DBG_BLOCK_ID_TCP_RESERVED0 = 0x77, 163 DBG_BLOCK_ID_TCP_RESERVED1 = 0x78, 164 DBG_BLOCK_ID_TCP_RESERVED2 = 0x79, 165 DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a, 166 DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b, 167 DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c, 168 DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d, 169 DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e, 170 DBG_BLOCK_ID_DB00 = 0x7f, 171 DBG_BLOCK_ID_DB01 = 0x80, 172 DBG_BLOCK_ID_DB02 = 0x81, 173 DBG_BLOCK_ID_DB03 = 0x82, 174 DBG_BLOCK_ID_DB04 = 0x83, 175 DBG_BLOCK_ID_UNUSED15 = 0x84, 176 DBG_BLOCK_ID_UNUSED16 = 0x85, 177 DBG_BLOCK_ID_UNUSED17 = 0x86, 178 DBG_BLOCK_ID_DB10 = 0x87, 179 DBG_BLOCK_ID_DB11 = 0x88, 180 DBG_BLOCK_ID_DB12 = 0x89, 181 DBG_BLOCK_ID_DB13 = 0x8a, 182 DBG_BLOCK_ID_DB14 = 0x8b, 183 DBG_BLOCK_ID_UNUSED18 = 0x8c, 184 DBG_BLOCK_ID_UNUSED19 = 0x8d, 185 DBG_BLOCK_ID_UNUSED20 = 0x8e, 186 DBG_BLOCK_ID_TCC0 = 0x8f, 187 DBG_BLOCK_ID_TCC1 = 0x90, 188 DBG_BLOCK_ID_TCC2 = 0x91, 189 DBG_BLOCK_ID_TCC3 = 0x92, 190 DBG_BLOCK_ID_TCC4 = 0x93, 191 DBG_BLOCK_ID_TCC5 = 0x94, 192 DBG_BLOCK_ID_TCC6 = 0x95, 193 DBG_BLOCK_ID_TCC7 = 0x96, 194 DBG_BLOCK_ID_SPS00 = 0x97, 195 DBG_BLOCK_ID_SPS01 = 0x98, 196 DBG_BLOCK_ID_SPS02 = 0x99, 197 DBG_BLOCK_ID_SPS10 = 0x9a, 198 DBG_BLOCK_ID_SPS11 = 0x9b, 199 DBG_BLOCK_ID_SPS12 = 0x9c, 200 DBG_BLOCK_ID_UNUSED21 = 0x9d, 201 DBG_BLOCK_ID_UNUSED22 = 0x9e, 202 DBG_BLOCK_ID_TA00 = 0x9f, 203 DBG_BLOCK_ID_TA01 = 0xa0, 204 DBG_BLOCK_ID_TA02 = 0xa1, 205 DBG_BLOCK_ID_TA03 = 0xa2, 206 DBG_BLOCK_ID_TA04 = 0xa3, 207 DBG_BLOCK_ID_TA05 = 0xa4, 208 DBG_BLOCK_ID_TA06 = 0xa5, 209 DBG_BLOCK_ID_TA07 = 0xa6, 210 DBG_BLOCK_ID_TA08 = 0xa7, 211 DBG_BLOCK_ID_TA09 = 0xa8, 212 DBG_BLOCK_ID_TA0A = 0xa9, 213 DBG_BLOCK_ID_TA0B = 0xaa, 214 DBG_BLOCK_ID_UNUSED23 = 0xab, 215 DBG_BLOCK_ID_UNUSED24 = 0xac, 216 DBG_BLOCK_ID_UNUSED25 = 0xad, 217 DBG_BLOCK_ID_UNUSED26 = 0xae, 218 DBG_BLOCK_ID_TA10 = 0xaf, 219 DBG_BLOCK_ID_TA11 = 0xb0, 220 DBG_BLOCK_ID_TA12 = 0xb1, 221 DBG_BLOCK_ID_TA13 = 0xb2, 222 DBG_BLOCK_ID_TA14 = 0xb3, 223 DBG_BLOCK_ID_TA15 = 0xb4, 224 DBG_BLOCK_ID_TA16 = 0xb5, 225 DBG_BLOCK_ID_TA17 = 0xb6, 226 DBG_BLOCK_ID_TA18 = 0xb7, 227 DBG_BLOCK_ID_TA19 = 0xb8, 228 DBG_BLOCK_ID_TA1A = 0xb9, 229 DBG_BLOCK_ID_TA1B = 0xba, 230 DBG_BLOCK_ID_UNUSED27 = 0xbb, 231 DBG_BLOCK_ID_UNUSED28 = 0xbc, 232 DBG_BLOCK_ID_UNUSED29 = 0xbd, 233 DBG_BLOCK_ID_UNUSED30 = 0xbe, 234 DBG_BLOCK_ID_TD00 = 0xbf, 235 DBG_BLOCK_ID_TD01 = 0xc0, 236 DBG_BLOCK_ID_TD02 = 0xc1, 237 DBG_BLOCK_ID_TD03 = 0xc2, 238 DBG_BLOCK_ID_TD04 = 0xc3, 239 DBG_BLOCK_ID_TD05 = 0xc4, 240 DBG_BLOCK_ID_TD06 = 0xc5, 241 DBG_BLOCK_ID_TD07 = 0xc6, 242 DBG_BLOCK_ID_TD08 = 0xc7, 243 DBG_BLOCK_ID_TD09 = 0xc8, 244 DBG_BLOCK_ID_TD0A = 0xc9, 245 DBG_BLOCK_ID_TD0B = 0xca, 246 DBG_BLOCK_ID_UNUSED31 = 0xcb, 247 DBG_BLOCK_ID_UNUSED32 = 0xcc, 248 DBG_BLOCK_ID_UNUSED33 = 0xcd, 249 DBG_BLOCK_ID_UNUSED34 = 0xce, 250 DBG_BLOCK_ID_TD10 = 0xcf, 251 DBG_BLOCK_ID_TD11 = 0xd0, 252 DBG_BLOCK_ID_TD12 = 0xd1, 253 DBG_BLOCK_ID_TD13 = 0xd2, 254 DBG_BLOCK_ID_TD14 = 0xd3, 255 DBG_BLOCK_ID_TD15 = 0xd4, 256 DBG_BLOCK_ID_TD16 = 0xd5, 257 DBG_BLOCK_ID_TD17 = 0xd6, 258 DBG_BLOCK_ID_TD18 = 0xd7, 259 DBG_BLOCK_ID_TD19 = 0xd8, 260 DBG_BLOCK_ID_TD1A = 0xd9, 261 DBG_BLOCK_ID_TD1B = 0xda, 262 DBG_BLOCK_ID_UNUSED35 = 0xdb, 263 DBG_BLOCK_ID_UNUSED36 = 0xdc, 264 DBG_BLOCK_ID_UNUSED37 = 0xdd, 265 DBG_BLOCK_ID_UNUSED38 = 0xde, 266 DBG_BLOCK_ID_LDS00 = 0xdf, 267 DBG_BLOCK_ID_LDS01 = 0xe0, 268 DBG_BLOCK_ID_LDS02 = 0xe1, 269 DBG_BLOCK_ID_LDS03 = 0xe2, 270 DBG_BLOCK_ID_LDS04 = 0xe3, 271 DBG_BLOCK_ID_LDS05 = 0xe4, 272 DBG_BLOCK_ID_LDS06 = 0xe5, 273 DBG_BLOCK_ID_LDS07 = 0xe6, 274 DBG_BLOCK_ID_LDS08 = 0xe7, 275 DBG_BLOCK_ID_LDS09 = 0xe8, 276 DBG_BLOCK_ID_LDS0A = 0xe9, 277 DBG_BLOCK_ID_LDS0B = 0xea, 278 DBG_BLOCK_ID_UNUSED39 = 0xeb, 279 DBG_BLOCK_ID_UNUSED40 = 0xec, 280 DBG_BLOCK_ID_UNUSED41 = 0xed, 281 DBG_BLOCK_ID_UNUSED42 = 0xee, 282 DBG_BLOCK_ID_LDS10 = 0xef, 283 DBG_BLOCK_ID_LDS11 = 0xf0, 284 DBG_BLOCK_ID_LDS12 = 0xf1, 285 DBG_BLOCK_ID_LDS13 = 0xf2, 286 DBG_BLOCK_ID_LDS14 = 0xf3, 287 DBG_BLOCK_ID_LDS15 = 0xf4, 288 DBG_BLOCK_ID_LDS16 = 0xf5, 289 DBG_BLOCK_ID_LDS17 = 0xf6, 290 DBG_BLOCK_ID_LDS18 = 0xf7, 291 DBG_BLOCK_ID_LDS19 = 0xf8, 292 DBG_BLOCK_ID_LDS1A = 0xf9, 293 DBG_BLOCK_ID_LDS1B = 0xfa, 294 DBG_BLOCK_ID_UNUSED43 = 0xfb, 295 DBG_BLOCK_ID_UNUSED44 = 0xfc, 296 DBG_BLOCK_ID_UNUSED45 = 0xfd, 297 DBG_BLOCK_ID_UNUSED46 = 0xfe, 298} DebugBlockId; 299typedef enum DebugBlockId_BY2 { 300 DBG_BLOCK_ID_RESERVED_BY2 = 0x0, 301 DBG_BLOCK_ID_VMC_BY2 = 0x1, 302 DBG_BLOCK_ID_UNUSED0_BY2 = 0x2, 303 DBG_BLOCK_ID_GRBM_BY2 = 0x3, 304 DBG_BLOCK_ID_CSC_BY2 = 0x4, 305 DBG_BLOCK_ID_IH_BY2 = 0x5, 306 DBG_BLOCK_ID_SQ_BY2 = 0x6, 307 DBG_BLOCK_ID_UVD_BY2 = 0x7, 308 DBG_BLOCK_ID_SDMA0_BY2 = 0x8, 309 DBG_BLOCK_ID_SPIM_BY2 = 0x9, 310 DBG_BLOCK_ID_VC0_BY2 = 0xa, 311 DBG_BLOCK_ID_PA_BY2 = 0xb, 312 DBG_BLOCK_ID_CP0_BY2 = 0xc, 313 DBG_BLOCK_ID_CP2_BY2 = 0xd, 314 DBG_BLOCK_ID_PC0_BY2 = 0xe, 315 DBG_BLOCK_ID_BCI0_BY2 = 0xf, 316 DBG_BLOCK_ID_SXM0_BY2 = 0x10, 317 DBG_BLOCK_ID_SCT0_BY2 = 0x11, 318 DBG_BLOCK_ID_SPM0_BY2 = 0x12, 319 DBG_BLOCK_ID_BCI2_BY2 = 0x13, 320 DBG_BLOCK_ID_TCA_BY2 = 0x14, 321 DBG_BLOCK_ID_TCCA_BY2 = 0x15, 322 DBG_BLOCK_ID_MCC_BY2 = 0x16, 323 DBG_BLOCK_ID_MCC2_BY2 = 0x17, 324 DBG_BLOCK_ID_MCD_BY2 = 0x18, 325 DBG_BLOCK_ID_MCD2_BY2 = 0x19, 326 DBG_BLOCK_ID_MCD4_BY2 = 0x1a, 327 DBG_BLOCK_ID_MCB_BY2 = 0x1b, 328 DBG_BLOCK_ID_SQA_BY2 = 0x1c, 329 DBG_BLOCK_ID_SQA02_BY2 = 0x1d, 330 DBG_BLOCK_ID_SQA11_BY2 = 0x1e, 331 DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f, 332 DBG_BLOCK_ID_SQB_BY2 = 0x20, 333 DBG_BLOCK_ID_SQB10_BY2 = 0x21, 334 DBG_BLOCK_ID_UNUSED10_BY2 = 0x22, 335 DBG_BLOCK_ID_UNUSED12_BY2 = 0x23, 336 DBG_BLOCK_ID_CB_BY2 = 0x24, 337 DBG_BLOCK_ID_CB02_BY2 = 0x25, 338 DBG_BLOCK_ID_CB10_BY2 = 0x26, 339 DBG_BLOCK_ID_CB12_BY2 = 0x27, 340 DBG_BLOCK_ID_SXS_BY2 = 0x28, 341 DBG_BLOCK_ID_SXS2_BY2 = 0x29, 342 DBG_BLOCK_ID_SXS4_BY2 = 0x2a, 343 DBG_BLOCK_ID_SXS6_BY2 = 0x2b, 344 DBG_BLOCK_ID_DB_BY2 = 0x2c, 345 DBG_BLOCK_ID_DB02_BY2 = 0x2d, 346 DBG_BLOCK_ID_DB10_BY2 = 0x2e, 347 DBG_BLOCK_ID_DB12_BY2 = 0x2f, 348 DBG_BLOCK_ID_TCP_BY2 = 0x30, 349 DBG_BLOCK_ID_TCP2_BY2 = 0x31, 350 DBG_BLOCK_ID_TCP4_BY2 = 0x32, 351 DBG_BLOCK_ID_TCP6_BY2 = 0x33, 352 DBG_BLOCK_ID_TCP8_BY2 = 0x34, 353 DBG_BLOCK_ID_TCP10_BY2 = 0x35, 354 DBG_BLOCK_ID_TCP12_BY2 = 0x36, 355 DBG_BLOCK_ID_TCP14_BY2 = 0x37, 356 DBG_BLOCK_ID_TCP16_BY2 = 0x38, 357 DBG_BLOCK_ID_TCP18_BY2 = 0x39, 358 DBG_BLOCK_ID_TCP20_BY2 = 0x3a, 359 DBG_BLOCK_ID_TCP22_BY2 = 0x3b, 360 DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, 361 DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, 362 DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, 363 DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, 364 DBG_BLOCK_ID_TCC_BY2 = 0x40, 365 DBG_BLOCK_ID_TCC2_BY2 = 0x41, 366 DBG_BLOCK_ID_TCC4_BY2 = 0x42, 367 DBG_BLOCK_ID_TCC6_BY2 = 0x43, 368 DBG_BLOCK_ID_SPS_BY2 = 0x44, 369 DBG_BLOCK_ID_SPS02_BY2 = 0x45, 370 DBG_BLOCK_ID_SPS11_BY2 = 0x46, 371 DBG_BLOCK_ID_UNUSED14_BY2 = 0x47, 372 DBG_BLOCK_ID_TA_BY2 = 0x48, 373 DBG_BLOCK_ID_TA02_BY2 = 0x49, 374 DBG_BLOCK_ID_TA04_BY2 = 0x4a, 375 DBG_BLOCK_ID_TA06_BY2 = 0x4b, 376 DBG_BLOCK_ID_TA08_BY2 = 0x4c, 377 DBG_BLOCK_ID_TA0A_BY2 = 0x4d, 378 DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e, 379 DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f, 380 DBG_BLOCK_ID_TA10_BY2 = 0x50, 381 DBG_BLOCK_ID_TA12_BY2 = 0x51, 382 DBG_BLOCK_ID_TA14_BY2 = 0x52, 383 DBG_BLOCK_ID_TA16_BY2 = 0x53, 384 DBG_BLOCK_ID_TA18_BY2 = 0x54, 385 DBG_BLOCK_ID_TA1A_BY2 = 0x55, 386 DBG_BLOCK_ID_UNUSED24_BY2 = 0x56, 387 DBG_BLOCK_ID_UNUSED26_BY2 = 0x57, 388 DBG_BLOCK_ID_TD_BY2 = 0x58, 389 DBG_BLOCK_ID_TD02_BY2 = 0x59, 390 DBG_BLOCK_ID_TD04_BY2 = 0x5a, 391 DBG_BLOCK_ID_TD06_BY2 = 0x5b, 392 DBG_BLOCK_ID_TD08_BY2 = 0x5c, 393 DBG_BLOCK_ID_TD0A_BY2 = 0x5d, 394 DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e, 395 DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f, 396 DBG_BLOCK_ID_TD10_BY2 = 0x60, 397 DBG_BLOCK_ID_TD12_BY2 = 0x61, 398 DBG_BLOCK_ID_TD14_BY2 = 0x62, 399 DBG_BLOCK_ID_TD16_BY2 = 0x63, 400 DBG_BLOCK_ID_TD18_BY2 = 0x64, 401 DBG_BLOCK_ID_TD1A_BY2 = 0x65, 402 DBG_BLOCK_ID_UNUSED32_BY2 = 0x66, 403 DBG_BLOCK_ID_UNUSED34_BY2 = 0x67, 404 DBG_BLOCK_ID_LDS_BY2 = 0x68, 405 DBG_BLOCK_ID_LDS02_BY2 = 0x69, 406 DBG_BLOCK_ID_LDS04_BY2 = 0x6a, 407 DBG_BLOCK_ID_LDS06_BY2 = 0x6b, 408 DBG_BLOCK_ID_LDS08_BY2 = 0x6c, 409 DBG_BLOCK_ID_LDS0A_BY2 = 0x6d, 410 DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e, 411 DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f, 412 DBG_BLOCK_ID_LDS10_BY2 = 0x70, 413 DBG_BLOCK_ID_LDS12_BY2 = 0x71, 414 DBG_BLOCK_ID_LDS14_BY2 = 0x72, 415 DBG_BLOCK_ID_LDS16_BY2 = 0x73, 416 DBG_BLOCK_ID_LDS18_BY2 = 0x74, 417 DBG_BLOCK_ID_LDS1A_BY2 = 0x75, 418 DBG_BLOCK_ID_UNUSED40_BY2 = 0x76, 419 DBG_BLOCK_ID_UNUSED42_BY2 = 0x77, 420} DebugBlockId_BY2; 421typedef enum DebugBlockId_BY4 { 422 DBG_BLOCK_ID_RESERVED_BY4 = 0x0, 423 DBG_BLOCK_ID_UNUSED0_BY4 = 0x1, 424 DBG_BLOCK_ID_CSC_BY4 = 0x2, 425 DBG_BLOCK_ID_SQ_BY4 = 0x3, 426 DBG_BLOCK_ID_SDMA0_BY4 = 0x4, 427 DBG_BLOCK_ID_VC0_BY4 = 0x5, 428 DBG_BLOCK_ID_CP0_BY4 = 0x6, 429 DBG_BLOCK_ID_UNUSED1_BY4 = 0x7, 430 DBG_BLOCK_ID_SXM0_BY4 = 0x8, 431 DBG_BLOCK_ID_SPM0_BY4 = 0x9, 432 DBG_BLOCK_ID_TCAA_BY4 = 0xa, 433 DBG_BLOCK_ID_MCC_BY4 = 0xb, 434 DBG_BLOCK_ID_MCD_BY4 = 0xc, 435 DBG_BLOCK_ID_MCD4_BY4 = 0xd, 436 DBG_BLOCK_ID_SQA_BY4 = 0xe, 437 DBG_BLOCK_ID_SQA11_BY4 = 0xf, 438 DBG_BLOCK_ID_SQB_BY4 = 0x10, 439 DBG_BLOCK_ID_UNUSED10_BY4 = 0x11, 440 DBG_BLOCK_ID_CB_BY4 = 0x12, 441 DBG_BLOCK_ID_CB10_BY4 = 0x13, 442 DBG_BLOCK_ID_SXS_BY4 = 0x14, 443 DBG_BLOCK_ID_SXS4_BY4 = 0x15, 444 DBG_BLOCK_ID_DB_BY4 = 0x16, 445 DBG_BLOCK_ID_DB10_BY4 = 0x17, 446 DBG_BLOCK_ID_TCP_BY4 = 0x18, 447 DBG_BLOCK_ID_TCP4_BY4 = 0x19, 448 DBG_BLOCK_ID_TCP8_BY4 = 0x1a, 449 DBG_BLOCK_ID_TCP12_BY4 = 0x1b, 450 DBG_BLOCK_ID_TCP16_BY4 = 0x1c, 451 DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 452 DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, 453 DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, 454 DBG_BLOCK_ID_TCC_BY4 = 0x20, 455 DBG_BLOCK_ID_TCC4_BY4 = 0x21, 456 DBG_BLOCK_ID_SPS_BY4 = 0x22, 457 DBG_BLOCK_ID_SPS11_BY4 = 0x23, 458 DBG_BLOCK_ID_TA_BY4 = 0x24, 459 DBG_BLOCK_ID_TA04_BY4 = 0x25, 460 DBG_BLOCK_ID_TA08_BY4 = 0x26, 461 DBG_BLOCK_ID_UNUSED20_BY4 = 0x27, 462 DBG_BLOCK_ID_TA10_BY4 = 0x28, 463 DBG_BLOCK_ID_TA14_BY4 = 0x29, 464 DBG_BLOCK_ID_TA18_BY4 = 0x2a, 465 DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b, 466 DBG_BLOCK_ID_TD_BY4 = 0x2c, 467 DBG_BLOCK_ID_TD04_BY4 = 0x2d, 468 DBG_BLOCK_ID_TD08_BY4 = 0x2e, 469 DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f, 470 DBG_BLOCK_ID_TD10_BY4 = 0x30, 471 DBG_BLOCK_ID_TD14_BY4 = 0x31, 472 DBG_BLOCK_ID_TD18_BY4 = 0x32, 473 DBG_BLOCK_ID_UNUSED32_BY4 = 0x33, 474 DBG_BLOCK_ID_LDS_BY4 = 0x34, 475 DBG_BLOCK_ID_LDS04_BY4 = 0x35, 476 DBG_BLOCK_ID_LDS08_BY4 = 0x36, 477 DBG_BLOCK_ID_UNUSED36_BY4 = 0x37, 478 DBG_BLOCK_ID_LDS10_BY4 = 0x38, 479 DBG_BLOCK_ID_LDS14_BY4 = 0x39, 480 DBG_BLOCK_ID_LDS18_BY4 = 0x3a, 481 DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b, 482} DebugBlockId_BY4; 483typedef enum DebugBlockId_BY8 { 484 DBG_BLOCK_ID_RESERVED_BY8 = 0x0, 485 DBG_BLOCK_ID_CSC_BY8 = 0x1, 486 DBG_BLOCK_ID_SDMA0_BY8 = 0x2, 487 DBG_BLOCK_ID_CP0_BY8 = 0x3, 488 DBG_BLOCK_ID_SXM0_BY8 = 0x4, 489 DBG_BLOCK_ID_TCA_BY8 = 0x5, 490 DBG_BLOCK_ID_MCD_BY8 = 0x6, 491 DBG_BLOCK_ID_SQA_BY8 = 0x7, 492 DBG_BLOCK_ID_SQB_BY8 = 0x8, 493 DBG_BLOCK_ID_CB_BY8 = 0x9, 494 DBG_BLOCK_ID_SXS_BY8 = 0xa, 495 DBG_BLOCK_ID_DB_BY8 = 0xb, 496 DBG_BLOCK_ID_TCP_BY8 = 0xc, 497 DBG_BLOCK_ID_TCP8_BY8 = 0xd, 498 DBG_BLOCK_ID_TCP16_BY8 = 0xe, 499 DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, 500 DBG_BLOCK_ID_TCC_BY8 = 0x10, 501 DBG_BLOCK_ID_SPS_BY8 = 0x11, 502 DBG_BLOCK_ID_TA_BY8 = 0x12, 503 DBG_BLOCK_ID_TA08_BY8 = 0x13, 504 DBG_BLOCK_ID_TA10_BY8 = 0x14, 505 DBG_BLOCK_ID_TA18_BY8 = 0x15, 506 DBG_BLOCK_ID_TD_BY8 = 0x16, 507 DBG_BLOCK_ID_TD08_BY8 = 0x17, 508 DBG_BLOCK_ID_TD10_BY8 = 0x18, 509 DBG_BLOCK_ID_TD18_BY8 = 0x19, 510 DBG_BLOCK_ID_LDS_BY8 = 0x1a, 511 DBG_BLOCK_ID_LDS08_BY8 = 0x1b, 512 DBG_BLOCK_ID_LDS10_BY8 = 0x1c, 513 DBG_BLOCK_ID_LDS18_BY8 = 0x1d, 514} DebugBlockId_BY8; 515typedef enum DebugBlockId_BY16 { 516 DBG_BLOCK_ID_RESERVED_BY16 = 0x0, 517 DBG_BLOCK_ID_SDMA0_BY16 = 0x1, 518 DBG_BLOCK_ID_SXM_BY16 = 0x2, 519 DBG_BLOCK_ID_MCD_BY16 = 0x3, 520 DBG_BLOCK_ID_SQB_BY16 = 0x4, 521 DBG_BLOCK_ID_SXS_BY16 = 0x5, 522 DBG_BLOCK_ID_TCP_BY16 = 0x6, 523 DBG_BLOCK_ID_TCP16_BY16 = 0x7, 524 DBG_BLOCK_ID_TCC_BY16 = 0x8, 525 DBG_BLOCK_ID_TA_BY16 = 0x9, 526 DBG_BLOCK_ID_TA10_BY16 = 0xa, 527 DBG_BLOCK_ID_TD_BY16 = 0xb, 528 DBG_BLOCK_ID_TD10_BY16 = 0xc, 529 DBG_BLOCK_ID_LDS_BY16 = 0xd, 530 DBG_BLOCK_ID_LDS10_BY16 = 0xe, 531} DebugBlockId_BY16; 532typedef enum SurfaceEndian { 533 ENDIAN_NONE = 0x0, 534 ENDIAN_8IN16 = 0x1, 535 ENDIAN_8IN32 = 0x2, 536 ENDIAN_8IN64 = 0x3, 537} SurfaceEndian; 538typedef enum ArrayMode { 539 ARRAY_LINEAR_GENERAL = 0x0, 540 ARRAY_LINEAR_ALIGNED = 0x1, 541 ARRAY_1D_TILED_THIN1 = 0x2, 542 ARRAY_1D_TILED_THICK = 0x3, 543 ARRAY_2D_TILED_THIN1 = 0x4, 544 ARRAY_PRT_TILED_THIN1 = 0x5, 545 ARRAY_PRT_2D_TILED_THIN1 = 0x6, 546 ARRAY_2D_TILED_THICK = 0x7, 547 ARRAY_2D_TILED_XTHICK = 0x8, 548 ARRAY_PRT_TILED_THICK = 0x9, 549 ARRAY_PRT_2D_TILED_THICK = 0xa, 550 ARRAY_PRT_3D_TILED_THIN1 = 0xb, 551 ARRAY_3D_TILED_THIN1 = 0xc, 552 ARRAY_3D_TILED_THICK = 0xd, 553 ARRAY_3D_TILED_XTHICK = 0xe, 554 ARRAY_PRT_3D_TILED_THICK = 0xf, 555} ArrayMode; 556typedef enum PipeTiling { 557 CONFIG_1_PIPE = 0x0, 558 CONFIG_2_PIPE = 0x1, 559 CONFIG_4_PIPE = 0x2, 560 CONFIG_8_PIPE = 0x3, 561} PipeTiling; 562typedef enum BankTiling { 563 CONFIG_4_BANK = 0x0, 564 CONFIG_8_BANK = 0x1, 565} BankTiling; 566typedef enum GroupInterleave { 567 CONFIG_256B_GROUP = 0x0, 568 CONFIG_512B_GROUP = 0x1, 569} GroupInterleave; 570typedef enum RowTiling { 571 CONFIG_1KB_ROW = 0x0, 572 CONFIG_2KB_ROW = 0x1, 573 CONFIG_4KB_ROW = 0x2, 574 CONFIG_8KB_ROW = 0x3, 575 CONFIG_1KB_ROW_OPT = 0x4, 576 CONFIG_2KB_ROW_OPT = 0x5, 577 CONFIG_4KB_ROW_OPT = 0x6, 578 CONFIG_8KB_ROW_OPT = 0x7, 579} RowTiling; 580typedef enum BankSwapBytes { 581 CONFIG_128B_SWAPS = 0x0, 582 CONFIG_256B_SWAPS = 0x1, 583 CONFIG_512B_SWAPS = 0x2, 584 CONFIG_1KB_SWAPS = 0x3, 585} BankSwapBytes; 586typedef enum SampleSplitBytes { 587 CONFIG_1KB_SPLIT = 0x0, 588 CONFIG_2KB_SPLIT = 0x1, 589 CONFIG_4KB_SPLIT = 0x2, 590 CONFIG_8KB_SPLIT = 0x3, 591} SampleSplitBytes; 592typedef enum NumPipes { 593 ADDR_CONFIG_1_PIPE = 0x0, 594 ADDR_CONFIG_2_PIPE = 0x1, 595 ADDR_CONFIG_4_PIPE = 0x2, 596 ADDR_CONFIG_8_PIPE = 0x3, 597} NumPipes; 598typedef enum PipeInterleaveSize { 599 ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, 600 ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, 601} PipeInterleaveSize; 602typedef enum BankInterleaveSize { 603 ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, 604 ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, 605 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, 606 ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, 607} BankInterleaveSize; 608typedef enum NumShaderEngines { 609 ADDR_CONFIG_1_SHADER_ENGINE = 0x0, 610 ADDR_CONFIG_2_SHADER_ENGINE = 0x1, 611} NumShaderEngines; 612typedef enum ShaderEngineTileSize { 613 ADDR_CONFIG_SE_TILE_16 = 0x0, 614 ADDR_CONFIG_SE_TILE_32 = 0x1, 615} ShaderEngineTileSize; 616typedef enum NumGPUs { 617 ADDR_CONFIG_1_GPU = 0x0, 618 ADDR_CONFIG_2_GPU = 0x1, 619 ADDR_CONFIG_4_GPU = 0x2, 620} NumGPUs; 621typedef enum MultiGPUTileSize { 622 ADDR_CONFIG_GPU_TILE_16 = 0x0, 623 ADDR_CONFIG_GPU_TILE_32 = 0x1, 624 ADDR_CONFIG_GPU_TILE_64 = 0x2, 625 ADDR_CONFIG_GPU_TILE_128 = 0x3, 626} MultiGPUTileSize; 627typedef enum RowSize { 628 ADDR_CONFIG_1KB_ROW = 0x0, 629 ADDR_CONFIG_2KB_ROW = 0x1, 630 ADDR_CONFIG_4KB_ROW = 0x2, 631} RowSize; 632typedef enum NumLowerPipes { 633 ADDR_CONFIG_1_LOWER_PIPES = 0x0, 634 ADDR_CONFIG_2_LOWER_PIPES = 0x1, 635} NumLowerPipes; 636typedef enum ColorTransform { 637 DCC_CT_AUTO = 0x0, 638 DCC_CT_NONE = 0x1, 639 ABGR_TO_A_BG_G_RB = 0x2, 640 BGRA_TO_BG_G_RB_A = 0x3, 641} ColorTransform; 642typedef enum CompareRef { 643 REF_NEVER = 0x0, 644 REF_LESS = 0x1, 645 REF_EQUAL = 0x2, 646 REF_LEQUAL = 0x3, 647 REF_GREATER = 0x4, 648 REF_NOTEQUAL = 0x5, 649 REF_GEQUAL = 0x6, 650 REF_ALWAYS = 0x7, 651} CompareRef; 652typedef enum ReadSize { 653 READ_256_BITS = 0x0, 654 READ_512_BITS = 0x1, 655} ReadSize; 656typedef enum DepthFormat { 657 DEPTH_INVALID = 0x0, 658 DEPTH_16 = 0x1, 659 DEPTH_X8_24 = 0x2, 660 DEPTH_8_24 = 0x3, 661 DEPTH_X8_24_FLOAT = 0x4, 662 DEPTH_8_24_FLOAT = 0x5, 663 DEPTH_32_FLOAT = 0x6, 664 DEPTH_X24_8_32_FLOAT = 0x7, 665} DepthFormat; 666typedef enum ZFormat { 667 Z_INVALID = 0x0, 668 Z_16 = 0x1, 669 Z_24 = 0x2, 670 Z_32_FLOAT = 0x3, 671} ZFormat; 672typedef enum StencilFormat { 673 STENCIL_INVALID = 0x0, 674 STENCIL_8 = 0x1, 675} StencilFormat; 676typedef enum CmaskMode { 677 CMASK_CLEAR_NONE = 0x0, 678 CMASK_CLEAR_ONE = 0x1, 679 CMASK_CLEAR_ALL = 0x2, 680 CMASK_ANY_EXPANDED = 0x3, 681 CMASK_ALPHA0_FRAG1 = 0x4, 682 CMASK_ALPHA0_FRAG2 = 0x5, 683 CMASK_ALPHA0_FRAG4 = 0x6, 684 CMASK_ALPHA0_FRAGS = 0x7, 685 CMASK_ALPHA1_FRAG1 = 0x8, 686 CMASK_ALPHA1_FRAG2 = 0x9, 687 CMASK_ALPHA1_FRAG4 = 0xa, 688 CMASK_ALPHA1_FRAGS = 0xb, 689 CMASK_ALPHAX_FRAG1 = 0xc, 690 CMASK_ALPHAX_FRAG2 = 0xd, 691 CMASK_ALPHAX_FRAG4 = 0xe, 692 CMASK_ALPHAX_FRAGS = 0xf, 693} CmaskMode; 694typedef enum QuadExportFormat { 695 EXPORT_UNUSED = 0x0, 696 EXPORT_32_R = 0x1, 697 EXPORT_32_GR = 0x2, 698 EXPORT_32_AR = 0x3, 699 EXPORT_FP16_ABGR = 0x4, 700 EXPORT_UNSIGNED16_ABGR = 0x5, 701 EXPORT_SIGNED16_ABGR = 0x6, 702 EXPORT_32_ABGR = 0x7, 703} QuadExportFormat; 704typedef enum QuadExportFormatOld { 705 EXPORT_4P_32BPC_ABGR = 0x0, 706 EXPORT_4P_16BPC_ABGR = 0x1, 707 EXPORT_4P_32BPC_GR = 0x2, 708 EXPORT_4P_32BPC_AR = 0x3, 709 EXPORT_2P_32BPC_ABGR = 0x4, 710 EXPORT_8P_32BPC_R = 0x5, 711} QuadExportFormatOld; 712typedef enum ColorFormat { 713 COLOR_INVALID = 0x0, 714 COLOR_8 = 0x1, 715 COLOR_16 = 0x2, 716 COLOR_8_8 = 0x3, 717 COLOR_32 = 0x4, 718 COLOR_16_16 = 0x5, 719 COLOR_10_11_11 = 0x6, 720 COLOR_11_11_10 = 0x7, 721 COLOR_10_10_10_2 = 0x8, 722 COLOR_2_10_10_10 = 0x9, 723 COLOR_8_8_8_8 = 0xa, 724 COLOR_32_32 = 0xb, 725 COLOR_16_16_16_16 = 0xc, 726 COLOR_RESERVED_13 = 0xd, 727 COLOR_32_32_32_32 = 0xe, 728 COLOR_RESERVED_15 = 0xf, 729 COLOR_5_6_5 = 0x10, 730 COLOR_1_5_5_5 = 0x11, 731 COLOR_5_5_5_1 = 0x12, 732 COLOR_4_4_4_4 = 0x13, 733 COLOR_8_24 = 0x14, 734 COLOR_24_8 = 0x15, 735 COLOR_X24_8_32_FLOAT = 0x16, 736 COLOR_RESERVED_23 = 0x17, 737} ColorFormat; 738typedef enum SurfaceFormat { 739 FMT_INVALID = 0x0, 740 FMT_8 = 0x1, 741 FMT_16 = 0x2, 742 FMT_8_8 = 0x3, 743 FMT_32 = 0x4, 744 FMT_16_16 = 0x5, 745 FMT_10_11_11 = 0x6, 746 FMT_11_11_10 = 0x7, 747 FMT_10_10_10_2 = 0x8, 748 FMT_2_10_10_10 = 0x9, 749 FMT_8_8_8_8 = 0xa, 750 FMT_32_32 = 0xb, 751 FMT_16_16_16_16 = 0xc, 752 FMT_32_32_32 = 0xd, 753 FMT_32_32_32_32 = 0xe, 754 FMT_RESERVED_4 = 0xf, 755 FMT_5_6_5 = 0x10, 756 FMT_1_5_5_5 = 0x11, 757 FMT_5_5_5_1 = 0x12, 758 FMT_4_4_4_4 = 0x13, 759 FMT_8_24 = 0x14, 760 FMT_24_8 = 0x15, 761 FMT_X24_8_32_FLOAT = 0x16, 762 FMT_RESERVED_33 = 0x17, 763 FMT_11_11_10_FLOAT = 0x18, 764 FMT_16_FLOAT = 0x19, 765 FMT_32_FLOAT = 0x1a, 766 FMT_16_16_FLOAT = 0x1b, 767 FMT_8_24_FLOAT = 0x1c, 768 FMT_24_8_FLOAT = 0x1d, 769 FMT_32_32_FLOAT = 0x1e, 770 FMT_10_11_11_FLOAT = 0x1f, 771 FMT_16_16_16_16_FLOAT = 0x20, 772 FMT_3_3_2 = 0x21, 773 FMT_6_5_5 = 0x22, 774 FMT_32_32_32_32_FLOAT = 0x23, 775 FMT_RESERVED_36 = 0x24, 776 FMT_1 = 0x25, 777 FMT_1_REVERSED = 0x26, 778 FMT_GB_GR = 0x27, 779 FMT_BG_RG = 0x28, 780 FMT_32_AS_8 = 0x29, 781 FMT_32_AS_8_8 = 0x2a, 782 FMT_5_9_9_9_SHAREDEXP = 0x2b, 783 FMT_8_8_8 = 0x2c, 784 FMT_16_16_16 = 0x2d, 785 FMT_16_16_16_FLOAT = 0x2e, 786 FMT_4_4 = 0x2f, 787 FMT_32_32_32_FLOAT = 0x30, 788 FMT_BC1 = 0x31, 789 FMT_BC2 = 0x32, 790 FMT_BC3 = 0x33, 791 FMT_BC4 = 0x34, 792 FMT_BC5 = 0x35, 793 FMT_BC6 = 0x36, 794 FMT_BC7 = 0x37, 795 FMT_32_AS_32_32_32_32 = 0x38, 796 FMT_APC3 = 0x39, 797 FMT_APC4 = 0x3a, 798 FMT_APC5 = 0x3b, 799 FMT_APC6 = 0x3c, 800 FMT_APC7 = 0x3d, 801 FMT_CTX1 = 0x3e, 802 FMT_RESERVED_63 = 0x3f, 803} SurfaceFormat; 804typedef enum BUF_DATA_FORMAT { 805 BUF_DATA_FORMAT_INVALID = 0x0, 806 BUF_DATA_FORMAT_8 = 0x1, 807 BUF_DATA_FORMAT_16 = 0x2, 808 BUF_DATA_FORMAT_8_8 = 0x3, 809 BUF_DATA_FORMAT_32 = 0x4, 810 BUF_DATA_FORMAT_16_16 = 0x5, 811 BUF_DATA_FORMAT_10_11_11 = 0x6, 812 BUF_DATA_FORMAT_11_11_10 = 0x7, 813 BUF_DATA_FORMAT_10_10_10_2 = 0x8, 814 BUF_DATA_FORMAT_2_10_10_10 = 0x9, 815 BUF_DATA_FORMAT_8_8_8_8 = 0xa, 816 BUF_DATA_FORMAT_32_32 = 0xb, 817 BUF_DATA_FORMAT_16_16_16_16 = 0xc, 818 BUF_DATA_FORMAT_32_32_32 = 0xd, 819 BUF_DATA_FORMAT_32_32_32_32 = 0xe, 820 BUF_DATA_FORMAT_RESERVED_15 = 0xf, 821} BUF_DATA_FORMAT; 822typedef enum IMG_DATA_FORMAT { 823 IMG_DATA_FORMAT_INVALID = 0x0, 824 IMG_DATA_FORMAT_8 = 0x1, 825 IMG_DATA_FORMAT_16 = 0x2, 826 IMG_DATA_FORMAT_8_8 = 0x3, 827 IMG_DATA_FORMAT_32 = 0x4, 828 IMG_DATA_FORMAT_16_16 = 0x5, 829 IMG_DATA_FORMAT_10_11_11 = 0x6, 830 IMG_DATA_FORMAT_11_11_10 = 0x7, 831 IMG_DATA_FORMAT_10_10_10_2 = 0x8, 832 IMG_DATA_FORMAT_2_10_10_10 = 0x9, 833 IMG_DATA_FORMAT_8_8_8_8 = 0xa, 834 IMG_DATA_FORMAT_32_32 = 0xb, 835 IMG_DATA_FORMAT_16_16_16_16 = 0xc, 836 IMG_DATA_FORMAT_32_32_32 = 0xd, 837 IMG_DATA_FORMAT_32_32_32_32 = 0xe, 838 IMG_DATA_FORMAT_RESERVED_15 = 0xf, 839 IMG_DATA_FORMAT_5_6_5 = 0x10, 840 IMG_DATA_FORMAT_1_5_5_5 = 0x11, 841 IMG_DATA_FORMAT_5_5_5_1 = 0x12, 842 IMG_DATA_FORMAT_4_4_4_4 = 0x13, 843 IMG_DATA_FORMAT_8_24 = 0x14, 844 IMG_DATA_FORMAT_24_8 = 0x15, 845 IMG_DATA_FORMAT_X24_8_32 = 0x16, 846 IMG_DATA_FORMAT_RESERVED_23 = 0x17, 847 IMG_DATA_FORMAT_RESERVED_24 = 0x18, 848 IMG_DATA_FORMAT_RESERVED_25 = 0x19, 849 IMG_DATA_FORMAT_RESERVED_26 = 0x1a, 850 IMG_DATA_FORMAT_RESERVED_27 = 0x1b, 851 IMG_DATA_FORMAT_RESERVED_28 = 0x1c, 852 IMG_DATA_FORMAT_RESERVED_29 = 0x1d, 853 IMG_DATA_FORMAT_RESERVED_30 = 0x1e, 854 IMG_DATA_FORMAT_RESERVED_31 = 0x1f, 855 IMG_DATA_FORMAT_GB_GR = 0x20, 856 IMG_DATA_FORMAT_BG_RG = 0x21, 857 IMG_DATA_FORMAT_5_9_9_9 = 0x22, 858 IMG_DATA_FORMAT_BC1 = 0x23, 859 IMG_DATA_FORMAT_BC2 = 0x24, 860 IMG_DATA_FORMAT_BC3 = 0x25, 861 IMG_DATA_FORMAT_BC4 = 0x26, 862 IMG_DATA_FORMAT_BC5 = 0x27, 863 IMG_DATA_FORMAT_BC6 = 0x28, 864 IMG_DATA_FORMAT_BC7 = 0x29, 865 IMG_DATA_FORMAT_RESERVED_42 = 0x2a, 866 IMG_DATA_FORMAT_RESERVED_43 = 0x2b, 867 IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, 868 IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, 869 IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, 870 IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, 871 IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, 872 IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, 873 IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, 874 IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, 875 IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, 876 IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, 877 IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, 878 IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, 879 IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, 880 IMG_DATA_FORMAT_4_4 = 0x39, 881 IMG_DATA_FORMAT_6_5_5 = 0x3a, 882 IMG_DATA_FORMAT_1 = 0x3b, 883 IMG_DATA_FORMAT_1_REVERSED = 0x3c, 884 IMG_DATA_FORMAT_32_AS_8 = 0x3d, 885 IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, 886 IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, 887} IMG_DATA_FORMAT; 888typedef enum BUF_NUM_FORMAT { 889 BUF_NUM_FORMAT_UNORM = 0x0, 890 BUF_NUM_FORMAT_SNORM = 0x1, 891 BUF_NUM_FORMAT_USCALED = 0x2, 892 BUF_NUM_FORMAT_SSCALED = 0x3, 893 BUF_NUM_FORMAT_UINT = 0x4, 894 BUF_NUM_FORMAT_SINT = 0x5, 895 BUF_NUM_FORMAT_RESERVED_6 = 0x6, 896 BUF_NUM_FORMAT_FLOAT = 0x7, 897} BUF_NUM_FORMAT; 898typedef enum IMG_NUM_FORMAT { 899 IMG_NUM_FORMAT_UNORM = 0x0, 900 IMG_NUM_FORMAT_SNORM = 0x1, 901 IMG_NUM_FORMAT_USCALED = 0x2, 902 IMG_NUM_FORMAT_SSCALED = 0x3, 903 IMG_NUM_FORMAT_UINT = 0x4, 904 IMG_NUM_FORMAT_SINT = 0x5, 905 IMG_NUM_FORMAT_RESERVED_6 = 0x6, 906 IMG_NUM_FORMAT_FLOAT = 0x7, 907 IMG_NUM_FORMAT_RESERVED_8 = 0x8, 908 IMG_NUM_FORMAT_SRGB = 0x9, 909 IMG_NUM_FORMAT_RESERVED_10 = 0xa, 910 IMG_NUM_FORMAT_RESERVED_11 = 0xb, 911 IMG_NUM_FORMAT_RESERVED_12 = 0xc, 912 IMG_NUM_FORMAT_RESERVED_13 = 0xd, 913 IMG_NUM_FORMAT_RESERVED_14 = 0xe, 914 IMG_NUM_FORMAT_RESERVED_15 = 0xf, 915} IMG_NUM_FORMAT; 916typedef enum TileType { 917 ARRAY_COLOR_TILE = 0x0, 918 ARRAY_DEPTH_TILE = 0x1, 919} TileType; 920typedef enum NonDispTilingOrder { 921 ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, 922 ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, 923} NonDispTilingOrder; 924typedef enum MicroTileMode { 925 ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, 926 ADDR_SURF_THIN_MICRO_TILING = 0x1, 927 ADDR_SURF_DEPTH_MICRO_TILING = 0x2, 928 ADDR_SURF_ROTATED_MICRO_TILING = 0x3, 929 ADDR_SURF_THICK_MICRO_TILING = 0x4, 930} MicroTileMode; 931typedef enum TileSplit { 932 ADDR_SURF_TILE_SPLIT_64B = 0x0, 933 ADDR_SURF_TILE_SPLIT_128B = 0x1, 934 ADDR_SURF_TILE_SPLIT_256B = 0x2, 935 ADDR_SURF_TILE_SPLIT_512B = 0x3, 936 ADDR_SURF_TILE_SPLIT_1KB = 0x4, 937 ADDR_SURF_TILE_SPLIT_2KB = 0x5, 938 ADDR_SURF_TILE_SPLIT_4KB = 0x6, 939} TileSplit; 940typedef enum SampleSplit { 941 ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, 942 ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, 943 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, 944 ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, 945} SampleSplit; 946typedef enum PipeConfig { 947 ADDR_SURF_P2 = 0x0, 948 ADDR_SURF_P2_RESERVED0 = 0x1, 949 ADDR_SURF_P2_RESERVED1 = 0x2, 950 ADDR_SURF_P2_RESERVED2 = 0x3, 951 ADDR_SURF_P4_8x16 = 0x4, 952 ADDR_SURF_P4_16x16 = 0x5, 953 ADDR_SURF_P4_16x32 = 0x6, 954 ADDR_SURF_P4_32x32 = 0x7, 955 ADDR_SURF_P8_16x16_8x16 = 0x8, 956 ADDR_SURF_P8_16x32_8x16 = 0x9, 957 ADDR_SURF_P8_32x32_8x16 = 0xa, 958 ADDR_SURF_P8_16x32_16x16 = 0xb, 959 ADDR_SURF_P8_32x32_16x16 = 0xc, 960 ADDR_SURF_P8_32x32_16x32 = 0xd, 961 ADDR_SURF_P8_32x64_32x32 = 0xe, 962 ADDR_SURF_P8_RESERVED0 = 0xf, 963 ADDR_SURF_P16_32x32_8x16 = 0x10, 964 ADDR_SURF_P16_32x32_16x16 = 0x11, 965} PipeConfig; 966typedef enum NumBanks { 967 ADDR_SURF_2_BANK = 0x0, 968 ADDR_SURF_4_BANK = 0x1, 969 ADDR_SURF_8_BANK = 0x2, 970 ADDR_SURF_16_BANK = 0x3, 971} NumBanks; 972typedef enum BankWidth { 973 ADDR_SURF_BANK_WIDTH_1 = 0x0, 974 ADDR_SURF_BANK_WIDTH_2 = 0x1, 975 ADDR_SURF_BANK_WIDTH_4 = 0x2, 976 ADDR_SURF_BANK_WIDTH_8 = 0x3, 977} BankWidth; 978typedef enum BankHeight { 979 ADDR_SURF_BANK_HEIGHT_1 = 0x0, 980 ADDR_SURF_BANK_HEIGHT_2 = 0x1, 981 ADDR_SURF_BANK_HEIGHT_4 = 0x2, 982 ADDR_SURF_BANK_HEIGHT_8 = 0x3, 983} BankHeight; 984typedef enum BankWidthHeight { 985 ADDR_SURF_BANK_WH_1 = 0x0, 986 ADDR_SURF_BANK_WH_2 = 0x1, 987 ADDR_SURF_BANK_WH_4 = 0x2, 988 ADDR_SURF_BANK_WH_8 = 0x3, 989} BankWidthHeight; 990typedef enum MacroTileAspect { 991 ADDR_SURF_MACRO_ASPECT_1 = 0x0, 992 ADDR_SURF_MACRO_ASPECT_2 = 0x1, 993 ADDR_SURF_MACRO_ASPECT_4 = 0x2, 994 ADDR_SURF_MACRO_ASPECT_8 = 0x3, 995} MacroTileAspect; 996typedef enum GATCL1RequestType { 997 GATCL1_TYPE_NORMAL = 0x0, 998 GATCL1_TYPE_SHOOTDOWN = 0x1, 999 GATCL1_TYPE_BYPASS = 0x2, 1000} GATCL1RequestType; 1001typedef enum TCC_CACHE_POLICIES { 1002 TCC_CACHE_POLICY_LRU = 0x0, 1003 TCC_CACHE_POLICY_STREAM = 0x1, 1004} TCC_CACHE_POLICIES; 1005typedef enum MTYPE { 1006 MTYPE_NC_NV = 0x0, 1007 MTYPE_NC = 0x1, 1008 MTYPE_CC = 0x2, 1009 MTYPE_UC = 0x3, 1010} MTYPE; 1011typedef enum PERFMON_COUNTER_MODE { 1012 PERFMON_COUNTER_MODE_ACCUM = 0x0, 1013 PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, 1014 PERFMON_COUNTER_MODE_MAX = 0x2, 1015 PERFMON_COUNTER_MODE_DIRTY = 0x3, 1016 PERFMON_COUNTER_MODE_SAMPLE = 0x4, 1017 PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, 1018 PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, 1019 PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, 1020 PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, 1021 PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, 1022 PERFMON_COUNTER_MODE_RESERVED = 0xf, 1023} PERFMON_COUNTER_MODE; 1024typedef enum PERFMON_SPM_MODE { 1025 PERFMON_SPM_MODE_OFF = 0x0, 1026 PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, 1027 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, 1028 PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, 1029 PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, 1030 PERFMON_SPM_MODE_RESERVED_5 = 0x5, 1031 PERFMON_SPM_MODE_RESERVED_6 = 0x6, 1032 PERFMON_SPM_MODE_RESERVED_7 = 0x7, 1033 PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, 1034 PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, 1035 PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, 1036} PERFMON_SPM_MODE; 1037typedef enum SurfaceTiling { 1038 ARRAY_LINEAR = 0x0, 1039 ARRAY_TILED = 0x1, 1040} SurfaceTiling; 1041typedef enum SurfaceArray { 1042 ARRAY_1D = 0x0, 1043 ARRAY_2D = 0x1, 1044 ARRAY_3D = 0x2, 1045 ARRAY_3D_SLICE = 0x3, 1046} SurfaceArray; 1047typedef enum ColorArray { 1048 ARRAY_2D_ALT_COLOR = 0x0, 1049 ARRAY_2D_COLOR = 0x1, 1050 ARRAY_3D_SLICE_COLOR = 0x3, 1051} ColorArray; 1052typedef enum DepthArray { 1053 ARRAY_2D_ALT_DEPTH = 0x0, 1054 ARRAY_2D_DEPTH = 0x1, 1055} DepthArray; 1056typedef enum ENUM_NUM_SIMD_PER_CU { 1057 NUM_SIMD_PER_CU = 0x4, 1058} ENUM_NUM_SIMD_PER_CU; 1059typedef enum MEM_PWR_FORCE_CTRL { 1060 NO_FORCE_REQUEST = 0x0, 1061 FORCE_LIGHT_SLEEP_REQUEST = 0x1, 1062 FORCE_DEEP_SLEEP_REQUEST = 0x2, 1063 FORCE_SHUT_DOWN_REQUEST = 0x3, 1064} MEM_PWR_FORCE_CTRL; 1065typedef enum MEM_PWR_FORCE_CTRL2 { 1066 NO_FORCE_REQ = 0x0, 1067 FORCE_LIGHT_SLEEP_REQ = 0x1, 1068} MEM_PWR_FORCE_CTRL2; 1069typedef enum MEM_PWR_DIS_CTRL { 1070 ENABLE_MEM_PWR_CTRL = 0x0, 1071 DISABLE_MEM_PWR_CTRL = 0x1, 1072} MEM_PWR_DIS_CTRL; 1073typedef enum MEM_PWR_SEL_CTRL { 1074 DYNAMIC_SHUT_DOWN_ENABLE = 0x0, 1075 DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, 1076 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, 1077} MEM_PWR_SEL_CTRL; 1078typedef enum MEM_PWR_SEL_CTRL2 { 1079 DYNAMIC_DEEP_SLEEP_EN = 0x0, 1080 DYNAMIC_LIGHT_SLEEP_EN = 0x1, 1081} MEM_PWR_SEL_CTRL2; 1082 1083#endif /* UVD_6_0_ENUM_H */ 1084