1/* $NetBSD: uvd_4_2_d.h,v 1.3 2021/12/18 23:45:24 riastradh Exp $ */ 2 3/* 4 * UVD_4_2 Register documentation 5 * 6 * Copyright (C) 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included 16 * in all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 22 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26#ifndef UVD_4_2_D_H 27#define UVD_4_2_D_H 28 29#define mmUVD_SEMA_ADDR_LOW 0x3bc0 30#define mmUVD_SEMA_ADDR_HIGH 0x3bc1 31#define mmUVD_SEMA_CMD 0x3bc2 32#define mmUVD_GPCOM_VCPU_CMD 0x3bc3 33#define mmUVD_GPCOM_VCPU_DATA0 0x3bc4 34#define mmUVD_GPCOM_VCPU_DATA1 0x3bc5 35#define mmUVD_ENGINE_CNTL 0x3bc6 36#define mmUVD_UDEC_ADDR_CONFIG 0x3bd3 37#define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4 38#define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 39#define mmUVD_NO_OP 0x3bff 40#define mmUVD_SEMA_CNTL 0x3d00 41#define mmUVD_LMI_EXT40_ADDR 0x3d26 42#define mmUVD_CTX_INDEX 0x3d28 43#define mmUVD_CTX_DATA 0x3d29 44#define mmUVD_CGC_GATE 0x3d2a 45#define mmUVD_CGC_STATUS 0x3d2b 46#define mmUVD_CGC_CTRL 0x3d2c 47#define mmUVD_CGC_UDEC_STATUS 0x3d2d 48#define mmUVD_LMI_CTRL2 0x3d3d 49#define mmUVD_MASTINT_EN 0x3d40 50#define mmUVD_LMI_ADDR_EXT 0x3d65 51#define mmUVD_LMI_CTRL 0x3d66 52#define mmUVD_LMI_STATUS 0x3d67 53#define mmUVD_LMI_SWAP_CNTL 0x3d6d 54#define mmUVD_MP_SWAP_CNTL 0x3d6f 55#define mmUVD_MPC_CNTL 0x3d77 56#define mmUVD_MPC_SET_MUXA0 0x3d79 57#define mmUVD_MPC_SET_MUXA1 0x3d7a 58#define mmUVD_MPC_SET_MUXB0 0x3d7b 59#define mmUVD_MPC_SET_MUXB1 0x3d7c 60#define mmUVD_MPC_SET_MUX 0x3d7d 61#define mmUVD_MPC_SET_ALU 0x3d7e 62#define mmUVD_VCPU_CACHE_OFFSET0 0x3d82 63#define mmUVD_VCPU_CACHE_SIZE0 0x3d83 64#define mmUVD_VCPU_CACHE_OFFSET1 0x3d84 65#define mmUVD_VCPU_CACHE_SIZE1 0x3d85 66#define mmUVD_VCPU_CACHE_OFFSET2 0x3d86 67#define mmUVD_VCPU_CACHE_SIZE2 0x3d87 68#define mmUVD_VCPU_CNTL 0x3d98 69#define mmUVD_SOFT_RESET 0x3da0 70#define mmUVD_RBC_IB_BASE 0x3da1 71#define mmUVD_RBC_IB_SIZE 0x3da2 72#define mmUVD_RBC_RB_BASE 0x3da3 73#define mmUVD_RBC_RB_RPTR 0x3da4 74#define mmUVD_RBC_RB_WPTR 0x3da5 75#define mmUVD_RBC_RB_WPTR_CNTL 0x3da6 76#define mmUVD_RBC_RB_CNTL 0x3da9 77#define mmUVD_RBC_RB_RPTR_ADDR 0x3daa 78#define mmUVD_STATUS 0x3daf 79#define mmUVD_SEMA_TIMEOUT_STATUS 0x3db0 80#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x3db1 81#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x3db2 82#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x3db3 83#define mmUVD_CONTEXT_ID 0x3dbd 84#define mmUVD_RBC_IB_SIZE_UPDATE 0x3df1 85#define ixUVD_LMI_CACHE_CTRL 0x9b 86#define ixUVD_LMI_SWAP_CNTL2 0xaa 87#define ixUVD_LMI_ADDR_EXT2 0xab 88#define ixUVD_CGC_MEM_CTRL 0xc0 89#define ixUVD_CGC_CTRL2 0xc1 90#define mmUVD_PGFSM_CONFIG 0x38f8 91#define mmUVD_PGFSM_READ_TILE1 0x38fa 92#define mmUVD_PGFSM_READ_TILE2 0x38fb 93#define mmUVD_POWER_STATUS 0x38fc 94#define ixUVD_MIF_CURR_ADDR_CONFIG 0x48 95#define ixUVD_MIF_REF_ADDR_CONFIG 0x4c 96#define ixUVD_MIF_RECON1_ADDR_CONFIG 0x114 97 98#endif /* UVD_4_2_D_H */ 99