1/* $NetBSD: smu_7_1_1_sh_mask.h,v 1.3 2021/12/18 23:45:23 riastradh Exp $ */ 2 3/* 4 * SMU_7_1_1 Register documentation 5 * 6 * Copyright (C) 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included 16 * in all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 22 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26#ifndef SMU_7_1_1_SH_MASK_H 27#define SMU_7_1_1_SH_MASK_H 28 29#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 30#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 31#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 32#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 33#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f 34#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0 35#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100 36#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8 37#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200 38#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9 39#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 40#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa 41#define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1 42#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0 43#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2 44#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1 45#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f 46#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0 47#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100 48#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8 49#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200 50#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9 51#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 52#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa 53#define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1 54#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0 55#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2 56#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1 57#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f 58#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0 59#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100 60#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8 61#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200 62#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9 63#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 64#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa 65#define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1 66#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0 67#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2 68#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1 69#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f 70#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0 71#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100 72#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8 73#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200 74#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9 75#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 76#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa 77#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1 78#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0 79#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2 80#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1 81#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4 82#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2 83#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8 84#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3 85#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10 86#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4 87#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20 88#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5 89#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40 90#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6 91#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80 92#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7 93#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100 94#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8 95#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200 96#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9 97#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400 98#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa 99#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800 100#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb 101#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000 102#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc 103#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1 104#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0 105#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2 106#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1 107#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4 108#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2 109#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8 110#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3 111#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10 112#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4 113#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0 114#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5 115#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800 116#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb 117#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000 118#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc 119#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x7f00000 120#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x14 121#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK_MASK 0x8000000 122#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK__SHIFT 0x1b 123#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000 124#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c 125#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff 126#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0 127#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800 128#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb 129#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000 130#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16 131#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000 132#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17 133#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000 134#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18 135#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000 136#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19 137#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000 138#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a 139#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000 140#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b 141#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000 142#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c 143#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000 144#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e 145#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff 146#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0 147#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000 148#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c 149#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf 150#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0 151#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60 152#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5 153#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180 154#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7 155#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0x7fe00 156#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0x9 157#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000 158#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15 159#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000 160#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17 161#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000 162#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18 163#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000 164#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19 165#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000 166#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a 167#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000 168#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c 169#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000 170#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f 171#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1 172#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0 173#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2 174#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1 175#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc 176#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2 177#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30 178#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4 179#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0 180#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6 181#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100 182#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8 183#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200 184#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9 185#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff 186#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0 187#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00 188#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8 189#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000 190#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10 191#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000 192#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11 193#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000 194#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15 195#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000 196#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19 197#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff 198#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0 199#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1 200#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0 201#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2 202#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1 203#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4 204#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2 205#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8 206#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3 207#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10 208#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4 209#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00 210#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa 211#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000 212#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc 213#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000 214#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c 215#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000 216#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d 217#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1 218#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0 219#define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0 220#define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4 221#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff 222#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0 223#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00 224#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8 225#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2 226#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1 227#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4 228#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2 229#define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1 230#define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0 231#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8 232#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3 233#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100 234#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8 235#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000 236#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe 237#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000 238#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf 239#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000 240#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10 241#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000 242#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11 243#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000 244#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12 245#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000 246#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13 247#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000 248#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14 249#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000 250#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15 251#define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000 252#define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16 253#define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000 254#define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18 255#define CG_CLKPIN_CNTL_DC__OSC_EN_MASK 0x1 256#define CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT 0x0 257#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN_MASK 0x6 258#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN__SHIFT 0x1 259#define CG_CLKPIN_CNTL_DC__XTL_XOCLK_DRV_R_EN_MASK 0x200 260#define CG_CLKPIN_CNTL_DC__XTL_XOCLK_DRV_R_EN__SHIFT 0x9 261#define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00 262#define CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT 0xa 263#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff 264#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0 265#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00 266#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8 267#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000 268#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10 269#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff 270#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0 271#define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00 272#define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8 273#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000 274#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10 275#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f 276#define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0 277#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0 278#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5 279#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00 280#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa 281#define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000 282#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11 283#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000 284#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12 285#define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000 286#define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11 287#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7 288#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0 289#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38 290#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3 291#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0 292#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6 293#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00 294#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9 295#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000 296#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc 297#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000 298#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf 299#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000 300#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12 301#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000 302#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15 303#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000 304#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18 305#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000 306#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b 307#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 308#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 309#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 310#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 311#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff 312#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0 313#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff 314#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0 315#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff 316#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0 317#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff 318#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0 319#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff 320#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0 321#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff 322#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0 323#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff 324#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0 325#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff 326#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0 327#define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff 328#define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0 329#define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff 330#define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0 331#define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff 332#define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0 333#define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff 334#define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0 335#define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff 336#define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0 337#define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff 338#define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0 339#define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff 340#define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0 341#define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff 342#define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0 343#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1 344#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0 345#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2 346#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1 347#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4 348#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2 349#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8 350#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3 351#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10 352#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4 353#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20 354#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5 355#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40 356#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6 357#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80 358#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7 359#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8_MASK 0x100 360#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8__SHIFT 0x8 361#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9_MASK 0x200 362#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9__SHIFT 0x9 363#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10_MASK 0x400 364#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10__SHIFT 0xa 365#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11_MASK 0x800 366#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11__SHIFT 0xb 367#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12_MASK 0x1000 368#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12__SHIFT 0xc 369#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13_MASK 0x2000 370#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13__SHIFT 0xd 371#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14_MASK 0x4000 372#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14__SHIFT 0xe 373#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15_MASK 0x8000 374#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15__SHIFT 0xf 375#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff 376#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0 377#define SMC_RESP_0__SMC_RESP_MASK 0xffff 378#define SMC_RESP_0__SMC_RESP__SHIFT 0x0 379#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff 380#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0 381#define SMC_RESP_1__SMC_RESP_MASK 0xffff 382#define SMC_RESP_1__SMC_RESP__SHIFT 0x0 383#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff 384#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0 385#define SMC_RESP_2__SMC_RESP_MASK 0xffff 386#define SMC_RESP_2__SMC_RESP__SHIFT 0x0 387#define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff 388#define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0 389#define SMC_RESP_3__SMC_RESP_MASK 0xffff 390#define SMC_RESP_3__SMC_RESP__SHIFT 0x0 391#define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff 392#define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0 393#define SMC_RESP_4__SMC_RESP_MASK 0xffff 394#define SMC_RESP_4__SMC_RESP__SHIFT 0x0 395#define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff 396#define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0 397#define SMC_RESP_5__SMC_RESP_MASK 0xffff 398#define SMC_RESP_5__SMC_RESP__SHIFT 0x0 399#define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff 400#define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0 401#define SMC_RESP_6__SMC_RESP_MASK 0xffff 402#define SMC_RESP_6__SMC_RESP__SHIFT 0x0 403#define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff 404#define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0 405#define SMC_RESP_7__SMC_RESP_MASK 0xffff 406#define SMC_RESP_7__SMC_RESP__SHIFT 0x0 407#define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff 408#define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0 409#define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff 410#define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0 411#define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff 412#define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0 413#define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff 414#define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0 415#define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff 416#define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0 417#define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff 418#define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0 419#define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff 420#define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0 421#define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff 422#define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0 423#define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff 424#define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0 425#define SMC_RESP_8__SMC_RESP_MASK 0xffff 426#define SMC_RESP_8__SMC_RESP__SHIFT 0x0 427#define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff 428#define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0 429#define SMC_RESP_9__SMC_RESP_MASK 0xffff 430#define SMC_RESP_9__SMC_RESP__SHIFT 0x0 431#define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff 432#define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0 433#define SMC_RESP_10__SMC_RESP_MASK 0xffff 434#define SMC_RESP_10__SMC_RESP__SHIFT 0x0 435#define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff 436#define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0 437#define SMC_RESP_11__SMC_RESP_MASK 0xffff 438#define SMC_RESP_11__SMC_RESP__SHIFT 0x0 439#define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff 440#define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0 441#define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff 442#define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0 443#define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff 444#define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0 445#define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff 446#define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0 447#define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1 448#define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0 449#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2 450#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1 451#define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000 452#define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e 453#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1 454#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0 455#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2 456#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1 457#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00 458#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8 459#define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000 460#define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18 461#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1 462#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0 463#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff 464#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0 465#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff 466#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0 467#define SMC_PC_C__smc_pc_c_MASK 0xffffffff 468#define SMC_PC_C__smc_pc_c__SHIFT 0x0 469#define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff 470#define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0 471#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x1 472#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0 473#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0xf 474#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x0 475#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0xf0 476#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x4 477#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffff 478#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0 479#define GPIOPAD_A__GPIO_A_MASK 0x7fffffff 480#define GPIOPAD_A__GPIO_A__SHIFT 0x0 481#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffff 482#define GPIOPAD_EN__GPIO_EN__SHIFT 0x0 483#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffff 484#define GPIOPAD_Y__GPIO_Y__SHIFT 0x0 485#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x1 486#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0 487#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x2 488#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1 489#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x4 490#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2 491#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x8 492#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3 493#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x10 494#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4 495#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x20 496#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5 497#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x40 498#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6 499#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x80 500#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7 501#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100 502#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8 503#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x200 504#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9 505#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x400 506#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa 507#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x800 508#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb 509#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x1000 510#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc 511#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x2000 512#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd 513#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x4000 514#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe 515#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x8000 516#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf 517#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x10000 518#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10 519#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x20000 520#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11 521#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x40000 522#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12 523#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x80000 524#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13 525#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x100000 526#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14 527#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x200000 528#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15 529#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x400000 530#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16 531#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x800000 532#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17 533#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x1000000 534#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18 535#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x2000000 536#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19 537#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x4000000 538#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a 539#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x8000000 540#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b 541#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000 542#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c 543#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000 544#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d 545#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000 546#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e 547#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffff 548#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0 549#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000 550#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f 551#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffff 552#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0 553#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000 554#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f 555#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x1 556#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0 557#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x2 558#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1 559#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x4 560#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2 561#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x8 562#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3 563#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x10 564#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4 565#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x20 566#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5 567#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x40 568#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6 569#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x80 570#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7 571#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100 572#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8 573#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x200 574#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9 575#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x400 576#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa 577#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x800 578#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb 579#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x1000 580#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc 581#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x2000 582#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd 583#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x4000 584#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe 585#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x8000 586#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf 587#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x10000 588#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10 589#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x20000 590#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11 591#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x40000 592#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12 593#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x80000 594#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13 595#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x100000 596#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14 597#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x200000 598#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15 599#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x400000 600#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16 601#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x800000 602#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17 603#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x1000000 604#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18 605#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x2000000 606#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19 607#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x4000000 608#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a 609#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x8000000 610#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b 611#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000 612#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c 613#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000 614#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f 615#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffff 616#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0 617#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000 618#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f 619#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffff 620#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0 621#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000 622#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f 623#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffff 624#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0 625#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000 626#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f 627#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x1f 628#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x0 629#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x20 630#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x5 631#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x40 632#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x6 633#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffff 634#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x0 635#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffff 636#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0 637#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffff 638#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0 639#define CG_FPS_CNT__FPS_CNT_MASK 0xffffffff 640#define CG_FPS_CNT__FPS_CNT__SHIFT 0x0 641#define SMU_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff 642#define SMU_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0 643#define SMU_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff 644#define SMU_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0 645#define SMU_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff 646#define SMU_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0 647#define SMU_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff 648#define SMU_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0 649#define SMU_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff 650#define SMU_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0 651#define SMU_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff 652#define SMU_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0 653#define SMU_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff 654#define SMU_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0 655#define SMU_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff 656#define SMU_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0 657#define SMU_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff 658#define SMU_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0 659#define SMU_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff 660#define SMU_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0 661#define SMU_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff 662#define SMU_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0 663#define SMU_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff 664#define SMU_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0 665#define SMU_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff 666#define SMU_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0 667#define SMU_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff 668#define SMU_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0 669#define SMU_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff 670#define SMU_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0 671#define SMU_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff 672#define SMU_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0 673#define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 674#define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 675#define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 676#define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 677#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1 678#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0 679#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2 680#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1 681#define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4 682#define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2 683#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid_MASK 0x8 684#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid__SHIFT 0x3 685#define RCU_UC_EVENTS__TP_Tester_MASK 0x40 686#define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6 687#define RCU_UC_EVENTS__boot_seq_done_MASK 0x80 688#define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7 689#define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100 690#define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8 691#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200 692#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9 693#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400 694#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa 695#define RCU_UC_EVENTS__FCH_HALT_MASK 0x800 696#define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb 697#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000 698#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd 699#define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000 700#define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10 701#define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000 702#define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11 703#define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000 704#define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12 705#define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000 706#define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13 707#define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000 708#define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18 709#define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2 710#define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1 711#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8 712#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3 713#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10 714#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4 715#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20 716#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5 717#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100 718#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8 719#define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000 720#define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10 721#define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000 722#define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11 723#define RCU_MISC_CTRL__SAMU_START_MASK 0x400000 724#define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16 725#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000 726#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17 727#define CC_RCU_FUSES__GPU_DIS_MASK 0x2 728#define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1 729#define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4 730#define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2 731#define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10 732#define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4 733#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20 734#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5 735#define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40 736#define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6 737#define CC_RCU_FUSES__ROM_DIS_MASK 0x80 738#define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7 739#define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100 740#define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8 741#define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200 742#define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9 743#define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400 744#define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa 745#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x4000 746#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xe 747#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x8000 748#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0xf 749#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x10000 750#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x10 751#define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x20000 752#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x11 753#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x40000 754#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x12 755#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x80000 756#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x13 757#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x200000 758#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x15 759#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x400000 760#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x16 761#define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x800000 762#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x17 763#define CC_RCU_FUSES__WRP_FUSE_VALID_MASK 0x1000000 764#define CC_RCU_FUSES__WRP_FUSE_VALID__SHIFT 0x18 765#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x2000000 766#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0x19 767#define CC_RCU_FUSES__RCU_SPARE_MASK 0xfc000000 768#define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x1a 769#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2 770#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1 771#define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc 772#define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2 773#define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600 774#define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9 775#define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800 776#define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb 777#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000 778#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12 779#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000 780#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13 781#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000 782#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14 783#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000 784#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15 785#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000 786#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16 787#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000 788#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17 789#define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000 790#define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b 791#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000 792#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c 793#define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000 794#define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d 795#define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff 796#define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0 797#define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00 798#define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8 799#define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000 800#define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10 801#define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000 802#define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18 803#define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe 804#define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1 805#define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3e 806#define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1 807#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e 808#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1 809#define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40 810#define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6 811#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80 812#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7 813#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100 814#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8 815#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200 816#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9 817#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400 818#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa 819#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800 820#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb 821#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000 822#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc 823#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000 824#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd 825#define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000 826#define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe 827#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000 828#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16 829#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000 830#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17 831#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000 832#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18 833#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000 834#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19 835#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000 836#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a 837#define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0 838#define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4 839#define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000 840#define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14 841#define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000 842#define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18 843#define CC_TST_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000 844#define CC_TST_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c 845#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2 846#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1 847#define CC_HARVEST_FUSES__VCE_DISABLE_MASK 0x6 848#define CC_HARVEST_FUSES__VCE_DISABLE__SHIFT 0x1 849#define CC_HARVEST_FUSES__UVD_DISABLE_MASK 0x10 850#define CC_HARVEST_FUSES__UVD_DISABLE__SHIFT 0x4 851#define CC_HARVEST_FUSES__ACP_EXISTS_MASK 0x40 852#define CC_HARVEST_FUSES__ACP_EXISTS__SHIFT 0x6 853#define CC_HARVEST_FUSES__DC_DISABLE_MASK 0x3f00 854#define CC_HARVEST_FUSES__DC_DISABLE__SHIFT 0x8 855#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff 856#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0 857#define SMU_STATUS__SMU_DONE_MASK 0x1 858#define SMU_STATUS__SMU_DONE__SHIFT 0x0 859#define SMU_STATUS__SMU_PASS_MASK 0x2 860#define SMU_STATUS__SMU_PASS__SHIFT 0x1 861#define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1 862#define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0 863#define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6 864#define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1 865#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8 866#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3 867#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10 868#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4 869#define SMU_FIRMWARE__SMU_counter_MASK 0xf00 870#define SMU_FIRMWARE__SMU_counter__SHIFT 0x8 871#define SMU_FIRMWARE__SMU_MODE_MASK 0x10000 872#define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10 873#define SMU_FIRMWARE__SMU_SEL_MASK 0x20000 874#define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11 875#define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff 876#define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0 877#define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000 878#define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f 879#define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff 880#define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0 881#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming_MASK 0xffffffff 882#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming__SHIFT 0x0 883#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2_MASK 0xffffffff 884#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2__SHIFT 0x0 885#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2_MASK 0xff 886#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2__SHIFT 0x0 887#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1_MASK 0xff00 888#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1__SHIFT 0x8 889#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0_MASK 0xff0000 890#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0__SHIFT 0x10 891#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime_MASK 0xff000000 892#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime__SHIFT 0x18 893#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming_MASK 0xffffffff 894#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming__SHIFT 0x0 895#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2_MASK 0xffffffff 896#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2__SHIFT 0x0 897#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2_MASK 0xff 898#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2__SHIFT 0x0 899#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1_MASK 0xff00 900#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1__SHIFT 0x8 901#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0_MASK 0xff0000 902#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0__SHIFT 0x10 903#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime_MASK 0xff000000 904#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime__SHIFT 0x18 905#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming_MASK 0xffffffff 906#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming__SHIFT 0x0 907#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2_MASK 0xffffffff 908#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2__SHIFT 0x0 909#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2_MASK 0xff 910#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2__SHIFT 0x0 911#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1_MASK 0xff00 912#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1__SHIFT 0x8 913#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0_MASK 0xff0000 914#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0__SHIFT 0x10 915#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime_MASK 0xff000000 916#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime__SHIFT 0x18 917#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming_MASK 0xffffffff 918#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming__SHIFT 0x0 919#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2_MASK 0xffffffff 920#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2__SHIFT 0x0 921#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2_MASK 0xff 922#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2__SHIFT 0x0 923#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1_MASK 0xff00 924#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1__SHIFT 0x8 925#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0_MASK 0xff0000 926#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0__SHIFT 0x10 927#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime_MASK 0xff000000 928#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime__SHIFT 0x18 929#define MCARB_DRAM_TIMING_TABLE_13__entries_1_0_McArbDramTiming_MASK 0xffffffff 930#define MCARB_DRAM_TIMING_TABLE_13__entries_1_0_McArbDramTiming__SHIFT 0x0 931#define MCARB_DRAM_TIMING_TABLE_14__entries_1_0_McArbDramTiming2_MASK 0xffffffff 932#define MCARB_DRAM_TIMING_TABLE_14__entries_1_0_McArbDramTiming2__SHIFT 0x0 933#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_2_MASK 0xff 934#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_2__SHIFT 0x0 935#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_1_MASK 0xff00 936#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_1__SHIFT 0x8 937#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_0_MASK 0xff0000 938#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_0__SHIFT 0x10 939#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_McArbBurstTime_MASK 0xff000000 940#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_McArbBurstTime__SHIFT 0x18 941#define MCARB_DRAM_TIMING_TABLE_16__entries_1_1_McArbDramTiming_MASK 0xffffffff 942#define MCARB_DRAM_TIMING_TABLE_16__entries_1_1_McArbDramTiming__SHIFT 0x0 943#define MCARB_DRAM_TIMING_TABLE_17__entries_1_1_McArbDramTiming2_MASK 0xffffffff 944#define MCARB_DRAM_TIMING_TABLE_17__entries_1_1_McArbDramTiming2__SHIFT 0x0 945#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_2_MASK 0xff 946#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_2__SHIFT 0x0 947#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_1_MASK 0xff00 948#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_1__SHIFT 0x8 949#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_0_MASK 0xff0000 950#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_0__SHIFT 0x10 951#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_McArbBurstTime_MASK 0xff000000 952#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_McArbBurstTime__SHIFT 0x18 953#define MCARB_DRAM_TIMING_TABLE_19__entries_1_2_McArbDramTiming_MASK 0xffffffff 954#define MCARB_DRAM_TIMING_TABLE_19__entries_1_2_McArbDramTiming__SHIFT 0x0 955#define MCARB_DRAM_TIMING_TABLE_20__entries_1_2_McArbDramTiming2_MASK 0xffffffff 956#define MCARB_DRAM_TIMING_TABLE_20__entries_1_2_McArbDramTiming2__SHIFT 0x0 957#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_2_MASK 0xff 958#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_2__SHIFT 0x0 959#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_1_MASK 0xff00 960#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_1__SHIFT 0x8 961#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_0_MASK 0xff0000 962#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_0__SHIFT 0x10 963#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_McArbBurstTime_MASK 0xff000000 964#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_McArbBurstTime__SHIFT 0x18 965#define MCARB_DRAM_TIMING_TABLE_22__entries_1_3_McArbDramTiming_MASK 0xffffffff 966#define MCARB_DRAM_TIMING_TABLE_22__entries_1_3_McArbDramTiming__SHIFT 0x0 967#define MCARB_DRAM_TIMING_TABLE_23__entries_1_3_McArbDramTiming2_MASK 0xffffffff 968#define MCARB_DRAM_TIMING_TABLE_23__entries_1_3_McArbDramTiming2__SHIFT 0x0 969#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_2_MASK 0xff 970#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_2__SHIFT 0x0 971#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_1_MASK 0xff00 972#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_1__SHIFT 0x8 973#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_0_MASK 0xff0000 974#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_0__SHIFT 0x10 975#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_McArbBurstTime_MASK 0xff000000 976#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_McArbBurstTime__SHIFT 0x18 977#define MCARB_DRAM_TIMING_TABLE_25__entries_2_0_McArbDramTiming_MASK 0xffffffff 978#define MCARB_DRAM_TIMING_TABLE_25__entries_2_0_McArbDramTiming__SHIFT 0x0 979#define MCARB_DRAM_TIMING_TABLE_26__entries_2_0_McArbDramTiming2_MASK 0xffffffff 980#define MCARB_DRAM_TIMING_TABLE_26__entries_2_0_McArbDramTiming2__SHIFT 0x0 981#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_2_MASK 0xff 982#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_2__SHIFT 0x0 983#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_1_MASK 0xff00 984#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_1__SHIFT 0x8 985#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_0_MASK 0xff0000 986#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_0__SHIFT 0x10 987#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_McArbBurstTime_MASK 0xff000000 988#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_McArbBurstTime__SHIFT 0x18 989#define MCARB_DRAM_TIMING_TABLE_28__entries_2_1_McArbDramTiming_MASK 0xffffffff 990#define MCARB_DRAM_TIMING_TABLE_28__entries_2_1_McArbDramTiming__SHIFT 0x0 991#define MCARB_DRAM_TIMING_TABLE_29__entries_2_1_McArbDramTiming2_MASK 0xffffffff 992#define MCARB_DRAM_TIMING_TABLE_29__entries_2_1_McArbDramTiming2__SHIFT 0x0 993#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_2_MASK 0xff 994#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_2__SHIFT 0x0 995#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_1_MASK 0xff00 996#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_1__SHIFT 0x8 997#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_0_MASK 0xff0000 998#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_0__SHIFT 0x10 999#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_McArbBurstTime_MASK 0xff000000 1000#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_McArbBurstTime__SHIFT 0x18 1001#define MCARB_DRAM_TIMING_TABLE_31__entries_2_2_McArbDramTiming_MASK 0xffffffff 1002#define MCARB_DRAM_TIMING_TABLE_31__entries_2_2_McArbDramTiming__SHIFT 0x0 1003#define MCARB_DRAM_TIMING_TABLE_32__entries_2_2_McArbDramTiming2_MASK 0xffffffff 1004#define MCARB_DRAM_TIMING_TABLE_32__entries_2_2_McArbDramTiming2__SHIFT 0x0 1005#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_2_MASK 0xff 1006#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_2__SHIFT 0x0 1007#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_1_MASK 0xff00 1008#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_1__SHIFT 0x8 1009#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_0_MASK 0xff0000 1010#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_0__SHIFT 0x10 1011#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_McArbBurstTime_MASK 0xff000000 1012#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_McArbBurstTime__SHIFT 0x18 1013#define MCARB_DRAM_TIMING_TABLE_34__entries_2_3_McArbDramTiming_MASK 0xffffffff 1014#define MCARB_DRAM_TIMING_TABLE_34__entries_2_3_McArbDramTiming__SHIFT 0x0 1015#define MCARB_DRAM_TIMING_TABLE_35__entries_2_3_McArbDramTiming2_MASK 0xffffffff 1016#define MCARB_DRAM_TIMING_TABLE_35__entries_2_3_McArbDramTiming2__SHIFT 0x0 1017#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_2_MASK 0xff 1018#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_2__SHIFT 0x0 1019#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_1_MASK 0xff00 1020#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_1__SHIFT 0x8 1021#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_0_MASK 0xff0000 1022#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_0__SHIFT 0x10 1023#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_McArbBurstTime_MASK 0xff000000 1024#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_McArbBurstTime__SHIFT 0x18 1025#define MCARB_DRAM_TIMING_TABLE_37__entries_3_0_McArbDramTiming_MASK 0xffffffff 1026#define MCARB_DRAM_TIMING_TABLE_37__entries_3_0_McArbDramTiming__SHIFT 0x0 1027#define MCARB_DRAM_TIMING_TABLE_38__entries_3_0_McArbDramTiming2_MASK 0xffffffff 1028#define MCARB_DRAM_TIMING_TABLE_38__entries_3_0_McArbDramTiming2__SHIFT 0x0 1029#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_2_MASK 0xff 1030#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_2__SHIFT 0x0 1031#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_1_MASK 0xff00 1032#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_1__SHIFT 0x8 1033#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_0_MASK 0xff0000 1034#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_0__SHIFT 0x10 1035#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_McArbBurstTime_MASK 0xff000000 1036#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_McArbBurstTime__SHIFT 0x18 1037#define MCARB_DRAM_TIMING_TABLE_40__entries_3_1_McArbDramTiming_MASK 0xffffffff 1038#define MCARB_DRAM_TIMING_TABLE_40__entries_3_1_McArbDramTiming__SHIFT 0x0 1039#define MCARB_DRAM_TIMING_TABLE_41__entries_3_1_McArbDramTiming2_MASK 0xffffffff 1040#define MCARB_DRAM_TIMING_TABLE_41__entries_3_1_McArbDramTiming2__SHIFT 0x0 1041#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_2_MASK 0xff 1042#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_2__SHIFT 0x0 1043#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_1_MASK 0xff00 1044#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_1__SHIFT 0x8 1045#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_0_MASK 0xff0000 1046#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_0__SHIFT 0x10 1047#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_McArbBurstTime_MASK 0xff000000 1048#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_McArbBurstTime__SHIFT 0x18 1049#define MCARB_DRAM_TIMING_TABLE_43__entries_3_2_McArbDramTiming_MASK 0xffffffff 1050#define MCARB_DRAM_TIMING_TABLE_43__entries_3_2_McArbDramTiming__SHIFT 0x0 1051#define MCARB_DRAM_TIMING_TABLE_44__entries_3_2_McArbDramTiming2_MASK 0xffffffff 1052#define MCARB_DRAM_TIMING_TABLE_44__entries_3_2_McArbDramTiming2__SHIFT 0x0 1053#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_2_MASK 0xff 1054#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_2__SHIFT 0x0 1055#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_1_MASK 0xff00 1056#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_1__SHIFT 0x8 1057#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_0_MASK 0xff0000 1058#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_0__SHIFT 0x10 1059#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_McArbBurstTime_MASK 0xff000000 1060#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_McArbBurstTime__SHIFT 0x18 1061#define MCARB_DRAM_TIMING_TABLE_46__entries_3_3_McArbDramTiming_MASK 0xffffffff 1062#define MCARB_DRAM_TIMING_TABLE_46__entries_3_3_McArbDramTiming__SHIFT 0x0 1063#define MCARB_DRAM_TIMING_TABLE_47__entries_3_3_McArbDramTiming2_MASK 0xffffffff 1064#define MCARB_DRAM_TIMING_TABLE_47__entries_3_3_McArbDramTiming2__SHIFT 0x0 1065#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_2_MASK 0xff 1066#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_2__SHIFT 0x0 1067#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_1_MASK 0xff00 1068#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_1__SHIFT 0x8 1069#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_0_MASK 0xff0000 1070#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_0__SHIFT 0x10 1071#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_McArbBurstTime_MASK 0xff000000 1072#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_McArbBurstTime__SHIFT 0x18 1073#define MCARB_DRAM_TIMING_TABLE_49__entries_4_0_McArbDramTiming_MASK 0xffffffff 1074#define MCARB_DRAM_TIMING_TABLE_49__entries_4_0_McArbDramTiming__SHIFT 0x0 1075#define MCARB_DRAM_TIMING_TABLE_50__entries_4_0_McArbDramTiming2_MASK 0xffffffff 1076#define MCARB_DRAM_TIMING_TABLE_50__entries_4_0_McArbDramTiming2__SHIFT 0x0 1077#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_2_MASK 0xff 1078#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_2__SHIFT 0x0 1079#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_1_MASK 0xff00 1080#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_1__SHIFT 0x8 1081#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_0_MASK 0xff0000 1082#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_0__SHIFT 0x10 1083#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_McArbBurstTime_MASK 0xff000000 1084#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_McArbBurstTime__SHIFT 0x18 1085#define MCARB_DRAM_TIMING_TABLE_52__entries_4_1_McArbDramTiming_MASK 0xffffffff 1086#define MCARB_DRAM_TIMING_TABLE_52__entries_4_1_McArbDramTiming__SHIFT 0x0 1087#define MCARB_DRAM_TIMING_TABLE_53__entries_4_1_McArbDramTiming2_MASK 0xffffffff 1088#define MCARB_DRAM_TIMING_TABLE_53__entries_4_1_McArbDramTiming2__SHIFT 0x0 1089#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_2_MASK 0xff 1090#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_2__SHIFT 0x0 1091#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_1_MASK 0xff00 1092#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_1__SHIFT 0x8 1093#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_0_MASK 0xff0000 1094#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_0__SHIFT 0x10 1095#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_McArbBurstTime_MASK 0xff000000 1096#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_McArbBurstTime__SHIFT 0x18 1097#define MCARB_DRAM_TIMING_TABLE_55__entries_4_2_McArbDramTiming_MASK 0xffffffff 1098#define MCARB_DRAM_TIMING_TABLE_55__entries_4_2_McArbDramTiming__SHIFT 0x0 1099#define MCARB_DRAM_TIMING_TABLE_56__entries_4_2_McArbDramTiming2_MASK 0xffffffff 1100#define MCARB_DRAM_TIMING_TABLE_56__entries_4_2_McArbDramTiming2__SHIFT 0x0 1101#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_2_MASK 0xff 1102#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_2__SHIFT 0x0 1103#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_1_MASK 0xff00 1104#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_1__SHIFT 0x8 1105#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_0_MASK 0xff0000 1106#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_0__SHIFT 0x10 1107#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_McArbBurstTime_MASK 0xff000000 1108#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_McArbBurstTime__SHIFT 0x18 1109#define MCARB_DRAM_TIMING_TABLE_58__entries_4_3_McArbDramTiming_MASK 0xffffffff 1110#define MCARB_DRAM_TIMING_TABLE_58__entries_4_3_McArbDramTiming__SHIFT 0x0 1111#define MCARB_DRAM_TIMING_TABLE_59__entries_4_3_McArbDramTiming2_MASK 0xffffffff 1112#define MCARB_DRAM_TIMING_TABLE_59__entries_4_3_McArbDramTiming2__SHIFT 0x0 1113#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_2_MASK 0xff 1114#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_2__SHIFT 0x0 1115#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_1_MASK 0xff00 1116#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_1__SHIFT 0x8 1117#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_0_MASK 0xff0000 1118#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_0__SHIFT 0x10 1119#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_McArbBurstTime_MASK 0xff000000 1120#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_McArbBurstTime__SHIFT 0x18 1121#define MCARB_DRAM_TIMING_TABLE_61__entries_5_0_McArbDramTiming_MASK 0xffffffff 1122#define MCARB_DRAM_TIMING_TABLE_61__entries_5_0_McArbDramTiming__SHIFT 0x0 1123#define MCARB_DRAM_TIMING_TABLE_62__entries_5_0_McArbDramTiming2_MASK 0xffffffff 1124#define MCARB_DRAM_TIMING_TABLE_62__entries_5_0_McArbDramTiming2__SHIFT 0x0 1125#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_2_MASK 0xff 1126#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_2__SHIFT 0x0 1127#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_1_MASK 0xff00 1128#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_1__SHIFT 0x8 1129#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_0_MASK 0xff0000 1130#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_0__SHIFT 0x10 1131#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_McArbBurstTime_MASK 0xff000000 1132#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_McArbBurstTime__SHIFT 0x18 1133#define MCARB_DRAM_TIMING_TABLE_64__entries_5_1_McArbDramTiming_MASK 0xffffffff 1134#define MCARB_DRAM_TIMING_TABLE_64__entries_5_1_McArbDramTiming__SHIFT 0x0 1135#define MCARB_DRAM_TIMING_TABLE_65__entries_5_1_McArbDramTiming2_MASK 0xffffffff 1136#define MCARB_DRAM_TIMING_TABLE_65__entries_5_1_McArbDramTiming2__SHIFT 0x0 1137#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_2_MASK 0xff 1138#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_2__SHIFT 0x0 1139#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_1_MASK 0xff00 1140#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_1__SHIFT 0x8 1141#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_0_MASK 0xff0000 1142#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_0__SHIFT 0x10 1143#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_McArbBurstTime_MASK 0xff000000 1144#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_McArbBurstTime__SHIFT 0x18 1145#define MCARB_DRAM_TIMING_TABLE_67__entries_5_2_McArbDramTiming_MASK 0xffffffff 1146#define MCARB_DRAM_TIMING_TABLE_67__entries_5_2_McArbDramTiming__SHIFT 0x0 1147#define MCARB_DRAM_TIMING_TABLE_68__entries_5_2_McArbDramTiming2_MASK 0xffffffff 1148#define MCARB_DRAM_TIMING_TABLE_68__entries_5_2_McArbDramTiming2__SHIFT 0x0 1149#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_2_MASK 0xff 1150#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_2__SHIFT 0x0 1151#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_1_MASK 0xff00 1152#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_1__SHIFT 0x8 1153#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_0_MASK 0xff0000 1154#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_0__SHIFT 0x10 1155#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_McArbBurstTime_MASK 0xff000000 1156#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_McArbBurstTime__SHIFT 0x18 1157#define MCARB_DRAM_TIMING_TABLE_70__entries_5_3_McArbDramTiming_MASK 0xffffffff 1158#define MCARB_DRAM_TIMING_TABLE_70__entries_5_3_McArbDramTiming__SHIFT 0x0 1159#define MCARB_DRAM_TIMING_TABLE_71__entries_5_3_McArbDramTiming2_MASK 0xffffffff 1160#define MCARB_DRAM_TIMING_TABLE_71__entries_5_3_McArbDramTiming2__SHIFT 0x0 1161#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_2_MASK 0xff 1162#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_2__SHIFT 0x0 1163#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_1_MASK 0xff00 1164#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_1__SHIFT 0x8 1165#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_0_MASK 0xff0000 1166#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_0__SHIFT 0x10 1167#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_McArbBurstTime_MASK 0xff000000 1168#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_McArbBurstTime__SHIFT 0x18 1169#define MCARB_DRAM_TIMING_TABLE_73__entries_6_0_McArbDramTiming_MASK 0xffffffff 1170#define MCARB_DRAM_TIMING_TABLE_73__entries_6_0_McArbDramTiming__SHIFT 0x0 1171#define MCARB_DRAM_TIMING_TABLE_74__entries_6_0_McArbDramTiming2_MASK 0xffffffff 1172#define MCARB_DRAM_TIMING_TABLE_74__entries_6_0_McArbDramTiming2__SHIFT 0x0 1173#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_2_MASK 0xff 1174#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_2__SHIFT 0x0 1175#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_1_MASK 0xff00 1176#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_1__SHIFT 0x8 1177#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_0_MASK 0xff0000 1178#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_0__SHIFT 0x10 1179#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_McArbBurstTime_MASK 0xff000000 1180#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_McArbBurstTime__SHIFT 0x18 1181#define MCARB_DRAM_TIMING_TABLE_76__entries_6_1_McArbDramTiming_MASK 0xffffffff 1182#define MCARB_DRAM_TIMING_TABLE_76__entries_6_1_McArbDramTiming__SHIFT 0x0 1183#define MCARB_DRAM_TIMING_TABLE_77__entries_6_1_McArbDramTiming2_MASK 0xffffffff 1184#define MCARB_DRAM_TIMING_TABLE_77__entries_6_1_McArbDramTiming2__SHIFT 0x0 1185#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_2_MASK 0xff 1186#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_2__SHIFT 0x0 1187#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_1_MASK 0xff00 1188#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_1__SHIFT 0x8 1189#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_0_MASK 0xff0000 1190#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_0__SHIFT 0x10 1191#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_McArbBurstTime_MASK 0xff000000 1192#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_McArbBurstTime__SHIFT 0x18 1193#define MCARB_DRAM_TIMING_TABLE_79__entries_6_2_McArbDramTiming_MASK 0xffffffff 1194#define MCARB_DRAM_TIMING_TABLE_79__entries_6_2_McArbDramTiming__SHIFT 0x0 1195#define MCARB_DRAM_TIMING_TABLE_80__entries_6_2_McArbDramTiming2_MASK 0xffffffff 1196#define MCARB_DRAM_TIMING_TABLE_80__entries_6_2_McArbDramTiming2__SHIFT 0x0 1197#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_2_MASK 0xff 1198#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_2__SHIFT 0x0 1199#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_1_MASK 0xff00 1200#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_1__SHIFT 0x8 1201#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_0_MASK 0xff0000 1202#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_0__SHIFT 0x10 1203#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_McArbBurstTime_MASK 0xff000000 1204#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_McArbBurstTime__SHIFT 0x18 1205#define MCARB_DRAM_TIMING_TABLE_82__entries_6_3_McArbDramTiming_MASK 0xffffffff 1206#define MCARB_DRAM_TIMING_TABLE_82__entries_6_3_McArbDramTiming__SHIFT 0x0 1207#define MCARB_DRAM_TIMING_TABLE_83__entries_6_3_McArbDramTiming2_MASK 0xffffffff 1208#define MCARB_DRAM_TIMING_TABLE_83__entries_6_3_McArbDramTiming2__SHIFT 0x0 1209#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_2_MASK 0xff 1210#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_2__SHIFT 0x0 1211#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_1_MASK 0xff00 1212#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_1__SHIFT 0x8 1213#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_0_MASK 0xff0000 1214#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_0__SHIFT 0x10 1215#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_McArbBurstTime_MASK 0xff000000 1216#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_McArbBurstTime__SHIFT 0x18 1217#define MCARB_DRAM_TIMING_TABLE_85__entries_7_0_McArbDramTiming_MASK 0xffffffff 1218#define MCARB_DRAM_TIMING_TABLE_85__entries_7_0_McArbDramTiming__SHIFT 0x0 1219#define MCARB_DRAM_TIMING_TABLE_86__entries_7_0_McArbDramTiming2_MASK 0xffffffff 1220#define MCARB_DRAM_TIMING_TABLE_86__entries_7_0_McArbDramTiming2__SHIFT 0x0 1221#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_2_MASK 0xff 1222#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_2__SHIFT 0x0 1223#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_1_MASK 0xff00 1224#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_1__SHIFT 0x8 1225#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_0_MASK 0xff0000 1226#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_0__SHIFT 0x10 1227#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_McArbBurstTime_MASK 0xff000000 1228#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_McArbBurstTime__SHIFT 0x18 1229#define MCARB_DRAM_TIMING_TABLE_88__entries_7_1_McArbDramTiming_MASK 0xffffffff 1230#define MCARB_DRAM_TIMING_TABLE_88__entries_7_1_McArbDramTiming__SHIFT 0x0 1231#define MCARB_DRAM_TIMING_TABLE_89__entries_7_1_McArbDramTiming2_MASK 0xffffffff 1232#define MCARB_DRAM_TIMING_TABLE_89__entries_7_1_McArbDramTiming2__SHIFT 0x0 1233#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_2_MASK 0xff 1234#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_2__SHIFT 0x0 1235#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_1_MASK 0xff00 1236#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_1__SHIFT 0x8 1237#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_0_MASK 0xff0000 1238#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_0__SHIFT 0x10 1239#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_McArbBurstTime_MASK 0xff000000 1240#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_McArbBurstTime__SHIFT 0x18 1241#define MCARB_DRAM_TIMING_TABLE_91__entries_7_2_McArbDramTiming_MASK 0xffffffff 1242#define MCARB_DRAM_TIMING_TABLE_91__entries_7_2_McArbDramTiming__SHIFT 0x0 1243#define MCARB_DRAM_TIMING_TABLE_92__entries_7_2_McArbDramTiming2_MASK 0xffffffff 1244#define MCARB_DRAM_TIMING_TABLE_92__entries_7_2_McArbDramTiming2__SHIFT 0x0 1245#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_2_MASK 0xff 1246#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_2__SHIFT 0x0 1247#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_1_MASK 0xff00 1248#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_1__SHIFT 0x8 1249#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_0_MASK 0xff0000 1250#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_0__SHIFT 0x10 1251#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_McArbBurstTime_MASK 0xff000000 1252#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_McArbBurstTime__SHIFT 0x18 1253#define MCARB_DRAM_TIMING_TABLE_94__entries_7_3_McArbDramTiming_MASK 0xffffffff 1254#define MCARB_DRAM_TIMING_TABLE_94__entries_7_3_McArbDramTiming__SHIFT 0x0 1255#define MCARB_DRAM_TIMING_TABLE_95__entries_7_3_McArbDramTiming2_MASK 0xffffffff 1256#define MCARB_DRAM_TIMING_TABLE_95__entries_7_3_McArbDramTiming2__SHIFT 0x0 1257#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_2_MASK 0xff 1258#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_2__SHIFT 0x0 1259#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_1_MASK 0xff00 1260#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_1__SHIFT 0x8 1261#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_0_MASK 0xff0000 1262#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_0__SHIFT 0x10 1263#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_McArbBurstTime_MASK 0xff000000 1264#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_McArbBurstTime__SHIFT 0x18 1265#define MC_REGISTERS_TABLE_1__reserved_2_MASK 0xff 1266#define MC_REGISTERS_TABLE_1__reserved_2__SHIFT 0x0 1267#define MC_REGISTERS_TABLE_1__reserved_1_MASK 0xff00 1268#define MC_REGISTERS_TABLE_1__reserved_1__SHIFT 0x8 1269#define MC_REGISTERS_TABLE_1__reserved_0_MASK 0xff0000 1270#define MC_REGISTERS_TABLE_1__reserved_0__SHIFT 0x10 1271#define MC_REGISTERS_TABLE_1__last_MASK 0xff000000 1272#define MC_REGISTERS_TABLE_1__last__SHIFT 0x18 1273#define MC_REGISTERS_TABLE_2__address_0_s1_MASK 0xffff 1274#define MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 0x0 1275#define MC_REGISTERS_TABLE_2__address_0_s0_MASK 0xffff0000 1276#define MC_REGISTERS_TABLE_2__address_0_s0__SHIFT 0x10 1277#define MC_REGISTERS_TABLE_3__address_1_s1_MASK 0xffff 1278#define MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 0x0 1279#define MC_REGISTERS_TABLE_3__address_1_s0_MASK 0xffff0000 1280#define MC_REGISTERS_TABLE_3__address_1_s0__SHIFT 0x10 1281#define MC_REGISTERS_TABLE_4__address_2_s1_MASK 0xffff 1282#define MC_REGISTERS_TABLE_4__address_2_s1__SHIFT 0x0 1283#define MC_REGISTERS_TABLE_4__address_2_s0_MASK 0xffff0000 1284#define MC_REGISTERS_TABLE_4__address_2_s0__SHIFT 0x10 1285#define MC_REGISTERS_TABLE_5__address_3_s1_MASK 0xffff 1286#define MC_REGISTERS_TABLE_5__address_3_s1__SHIFT 0x0 1287#define MC_REGISTERS_TABLE_5__address_3_s0_MASK 0xffff0000 1288#define MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 0x10 1289#define MC_REGISTERS_TABLE_6__address_4_s1_MASK 0xffff 1290#define MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 0x0 1291#define MC_REGISTERS_TABLE_6__address_4_s0_MASK 0xffff0000 1292#define MC_REGISTERS_TABLE_6__address_4_s0__SHIFT 0x10 1293#define MC_REGISTERS_TABLE_7__address_5_s1_MASK 0xffff 1294#define MC_REGISTERS_TABLE_7__address_5_s1__SHIFT 0x0 1295#define MC_REGISTERS_TABLE_7__address_5_s0_MASK 0xffff0000 1296#define MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 0x10 1297#define MC_REGISTERS_TABLE_8__address_6_s1_MASK 0xffff 1298#define MC_REGISTERS_TABLE_8__address_6_s1__SHIFT 0x0 1299#define MC_REGISTERS_TABLE_8__address_6_s0_MASK 0xffff0000 1300#define MC_REGISTERS_TABLE_8__address_6_s0__SHIFT 0x10 1301#define MC_REGISTERS_TABLE_9__address_7_s1_MASK 0xffff 1302#define MC_REGISTERS_TABLE_9__address_7_s1__SHIFT 0x0 1303#define MC_REGISTERS_TABLE_9__address_7_s0_MASK 0xffff0000 1304#define MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 0x10 1305#define MC_REGISTERS_TABLE_10__address_8_s1_MASK 0xffff 1306#define MC_REGISTERS_TABLE_10__address_8_s1__SHIFT 0x0 1307#define MC_REGISTERS_TABLE_10__address_8_s0_MASK 0xffff0000 1308#define MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 0x10 1309#define MC_REGISTERS_TABLE_11__address_9_s1_MASK 0xffff 1310#define MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 0x0 1311#define MC_REGISTERS_TABLE_11__address_9_s0_MASK 0xffff0000 1312#define MC_REGISTERS_TABLE_11__address_9_s0__SHIFT 0x10 1313#define MC_REGISTERS_TABLE_12__address_10_s1_MASK 0xffff 1314#define MC_REGISTERS_TABLE_12__address_10_s1__SHIFT 0x0 1315#define MC_REGISTERS_TABLE_12__address_10_s0_MASK 0xffff0000 1316#define MC_REGISTERS_TABLE_12__address_10_s0__SHIFT 0x10 1317#define MC_REGISTERS_TABLE_13__address_11_s1_MASK 0xffff 1318#define MC_REGISTERS_TABLE_13__address_11_s1__SHIFT 0x0 1319#define MC_REGISTERS_TABLE_13__address_11_s0_MASK 0xffff0000 1320#define MC_REGISTERS_TABLE_13__address_11_s0__SHIFT 0x10 1321#define MC_REGISTERS_TABLE_14__address_12_s1_MASK 0xffff 1322#define MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 0x0 1323#define MC_REGISTERS_TABLE_14__address_12_s0_MASK 0xffff0000 1324#define MC_REGISTERS_TABLE_14__address_12_s0__SHIFT 0x10 1325#define MC_REGISTERS_TABLE_15__address_13_s1_MASK 0xffff 1326#define MC_REGISTERS_TABLE_15__address_13_s1__SHIFT 0x0 1327#define MC_REGISTERS_TABLE_15__address_13_s0_MASK 0xffff0000 1328#define MC_REGISTERS_TABLE_15__address_13_s0__SHIFT 0x10 1329#define MC_REGISTERS_TABLE_16__address_14_s1_MASK 0xffff 1330#define MC_REGISTERS_TABLE_16__address_14_s1__SHIFT 0x0 1331#define MC_REGISTERS_TABLE_16__address_14_s0_MASK 0xffff0000 1332#define MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 0x10 1333#define MC_REGISTERS_TABLE_17__address_15_s1_MASK 0xffff 1334#define MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 0x0 1335#define MC_REGISTERS_TABLE_17__address_15_s0_MASK 0xffff0000 1336#define MC_REGISTERS_TABLE_17__address_15_s0__SHIFT 0x10 1337#define MC_REGISTERS_TABLE_18__data_0_value_0_MASK 0xffffffff 1338#define MC_REGISTERS_TABLE_18__data_0_value_0__SHIFT 0x0 1339#define MC_REGISTERS_TABLE_19__data_0_value_1_MASK 0xffffffff 1340#define MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 0x0 1341#define MC_REGISTERS_TABLE_20__data_0_value_2_MASK 0xffffffff 1342#define MC_REGISTERS_TABLE_20__data_0_value_2__SHIFT 0x0 1343#define MC_REGISTERS_TABLE_21__data_0_value_3_MASK 0xffffffff 1344#define MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 0x0 1345#define MC_REGISTERS_TABLE_22__data_0_value_4_MASK 0xffffffff 1346#define MC_REGISTERS_TABLE_22__data_0_value_4__SHIFT 0x0 1347#define MC_REGISTERS_TABLE_23__data_0_value_5_MASK 0xffffffff 1348#define MC_REGISTERS_TABLE_23__data_0_value_5__SHIFT 0x0 1349#define MC_REGISTERS_TABLE_24__data_0_value_6_MASK 0xffffffff 1350#define MC_REGISTERS_TABLE_24__data_0_value_6__SHIFT 0x0 1351#define MC_REGISTERS_TABLE_25__data_0_value_7_MASK 0xffffffff 1352#define MC_REGISTERS_TABLE_25__data_0_value_7__SHIFT 0x0 1353#define MC_REGISTERS_TABLE_26__data_0_value_8_MASK 0xffffffff 1354#define MC_REGISTERS_TABLE_26__data_0_value_8__SHIFT 0x0 1355#define MC_REGISTERS_TABLE_27__data_0_value_9_MASK 0xffffffff 1356#define MC_REGISTERS_TABLE_27__data_0_value_9__SHIFT 0x0 1357#define MC_REGISTERS_TABLE_28__data_0_value_10_MASK 0xffffffff 1358#define MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 0x0 1359#define MC_REGISTERS_TABLE_29__data_0_value_11_MASK 0xffffffff 1360#define MC_REGISTERS_TABLE_29__data_0_value_11__SHIFT 0x0 1361#define MC_REGISTERS_TABLE_30__data_0_value_12_MASK 0xffffffff 1362#define MC_REGISTERS_TABLE_30__data_0_value_12__SHIFT 0x0 1363#define MC_REGISTERS_TABLE_31__data_0_value_13_MASK 0xffffffff 1364#define MC_REGISTERS_TABLE_31__data_0_value_13__SHIFT 0x0 1365#define MC_REGISTERS_TABLE_32__data_0_value_14_MASK 0xffffffff 1366#define MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 0x0 1367#define MC_REGISTERS_TABLE_33__data_0_value_15_MASK 0xffffffff 1368#define MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 0x0 1369#define MC_REGISTERS_TABLE_34__data_1_value_0_MASK 0xffffffff 1370#define MC_REGISTERS_TABLE_34__data_1_value_0__SHIFT 0x0 1371#define MC_REGISTERS_TABLE_35__data_1_value_1_MASK 0xffffffff 1372#define MC_REGISTERS_TABLE_35__data_1_value_1__SHIFT 0x0 1373#define MC_REGISTERS_TABLE_36__data_1_value_2_MASK 0xffffffff 1374#define MC_REGISTERS_TABLE_36__data_1_value_2__SHIFT 0x0 1375#define MC_REGISTERS_TABLE_37__data_1_value_3_MASK 0xffffffff 1376#define MC_REGISTERS_TABLE_37__data_1_value_3__SHIFT 0x0 1377#define MC_REGISTERS_TABLE_38__data_1_value_4_MASK 0xffffffff 1378#define MC_REGISTERS_TABLE_38__data_1_value_4__SHIFT 0x0 1379#define MC_REGISTERS_TABLE_39__data_1_value_5_MASK 0xffffffff 1380#define MC_REGISTERS_TABLE_39__data_1_value_5__SHIFT 0x0 1381#define MC_REGISTERS_TABLE_40__data_1_value_6_MASK 0xffffffff 1382#define MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 0x0 1383#define MC_REGISTERS_TABLE_41__data_1_value_7_MASK 0xffffffff 1384#define MC_REGISTERS_TABLE_41__data_1_value_7__SHIFT 0x0 1385#define MC_REGISTERS_TABLE_42__data_1_value_8_MASK 0xffffffff 1386#define MC_REGISTERS_TABLE_42__data_1_value_8__SHIFT 0x0 1387#define MC_REGISTERS_TABLE_43__data_1_value_9_MASK 0xffffffff 1388#define MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 0x0 1389#define MC_REGISTERS_TABLE_44__data_1_value_10_MASK 0xffffffff 1390#define MC_REGISTERS_TABLE_44__data_1_value_10__SHIFT 0x0 1391#define MC_REGISTERS_TABLE_45__data_1_value_11_MASK 0xffffffff 1392#define MC_REGISTERS_TABLE_45__data_1_value_11__SHIFT 0x0 1393#define MC_REGISTERS_TABLE_46__data_1_value_12_MASK 0xffffffff 1394#define MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 0x0 1395#define MC_REGISTERS_TABLE_47__data_1_value_13_MASK 0xffffffff 1396#define MC_REGISTERS_TABLE_47__data_1_value_13__SHIFT 0x0 1397#define MC_REGISTERS_TABLE_48__data_1_value_14_MASK 0xffffffff 1398#define MC_REGISTERS_TABLE_48__data_1_value_14__SHIFT 0x0 1399#define MC_REGISTERS_TABLE_49__data_1_value_15_MASK 0xffffffff 1400#define MC_REGISTERS_TABLE_49__data_1_value_15__SHIFT 0x0 1401#define MC_REGISTERS_TABLE_50__data_2_value_0_MASK 0xffffffff 1402#define MC_REGISTERS_TABLE_50__data_2_value_0__SHIFT 0x0 1403#define MC_REGISTERS_TABLE_51__data_2_value_1_MASK 0xffffffff 1404#define MC_REGISTERS_TABLE_51__data_2_value_1__SHIFT 0x0 1405#define MC_REGISTERS_TABLE_52__data_2_value_2_MASK 0xffffffff 1406#define MC_REGISTERS_TABLE_52__data_2_value_2__SHIFT 0x0 1407#define MC_REGISTERS_TABLE_53__data_2_value_3_MASK 0xffffffff 1408#define MC_REGISTERS_TABLE_53__data_2_value_3__SHIFT 0x0 1409#define MC_REGISTERS_TABLE_54__data_2_value_4_MASK 0xffffffff 1410#define MC_REGISTERS_TABLE_54__data_2_value_4__SHIFT 0x0 1411#define MC_REGISTERS_TABLE_55__data_2_value_5_MASK 0xffffffff 1412#define MC_REGISTERS_TABLE_55__data_2_value_5__SHIFT 0x0 1413#define MC_REGISTERS_TABLE_56__data_2_value_6_MASK 0xffffffff 1414#define MC_REGISTERS_TABLE_56__data_2_value_6__SHIFT 0x0 1415#define MC_REGISTERS_TABLE_57__data_2_value_7_MASK 0xffffffff 1416#define MC_REGISTERS_TABLE_57__data_2_value_7__SHIFT 0x0 1417#define MC_REGISTERS_TABLE_58__data_2_value_8_MASK 0xffffffff 1418#define MC_REGISTERS_TABLE_58__data_2_value_8__SHIFT 0x0 1419#define MC_REGISTERS_TABLE_59__data_2_value_9_MASK 0xffffffff 1420#define MC_REGISTERS_TABLE_59__data_2_value_9__SHIFT 0x0 1421#define MC_REGISTERS_TABLE_60__data_2_value_10_MASK 0xffffffff 1422#define MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 0x0 1423#define MC_REGISTERS_TABLE_61__data_2_value_11_MASK 0xffffffff 1424#define MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 0x0 1425#define MC_REGISTERS_TABLE_62__data_2_value_12_MASK 0xffffffff 1426#define MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 0x0 1427#define MC_REGISTERS_TABLE_63__data_2_value_13_MASK 0xffffffff 1428#define MC_REGISTERS_TABLE_63__data_2_value_13__SHIFT 0x0 1429#define MC_REGISTERS_TABLE_64__data_2_value_14_MASK 0xffffffff 1430#define MC_REGISTERS_TABLE_64__data_2_value_14__SHIFT 0x0 1431#define MC_REGISTERS_TABLE_65__data_2_value_15_MASK 0xffffffff 1432#define MC_REGISTERS_TABLE_65__data_2_value_15__SHIFT 0x0 1433#define MC_REGISTERS_TABLE_66__data_3_value_0_MASK 0xffffffff 1434#define MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 0x0 1435#define MC_REGISTERS_TABLE_67__data_3_value_1_MASK 0xffffffff 1436#define MC_REGISTERS_TABLE_67__data_3_value_1__SHIFT 0x0 1437#define MC_REGISTERS_TABLE_68__data_3_value_2_MASK 0xffffffff 1438#define MC_REGISTERS_TABLE_68__data_3_value_2__SHIFT 0x0 1439#define MC_REGISTERS_TABLE_69__data_3_value_3_MASK 0xffffffff 1440#define MC_REGISTERS_TABLE_69__data_3_value_3__SHIFT 0x0 1441#define MC_REGISTERS_TABLE_70__data_3_value_4_MASK 0xffffffff 1442#define MC_REGISTERS_TABLE_70__data_3_value_4__SHIFT 0x0 1443#define MC_REGISTERS_TABLE_71__data_3_value_5_MASK 0xffffffff 1444#define MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 0x0 1445#define MC_REGISTERS_TABLE_72__data_3_value_6_MASK 0xffffffff 1446#define MC_REGISTERS_TABLE_72__data_3_value_6__SHIFT 0x0 1447#define MC_REGISTERS_TABLE_73__data_3_value_7_MASK 0xffffffff 1448#define MC_REGISTERS_TABLE_73__data_3_value_7__SHIFT 0x0 1449#define MC_REGISTERS_TABLE_74__data_3_value_8_MASK 0xffffffff 1450#define MC_REGISTERS_TABLE_74__data_3_value_8__SHIFT 0x0 1451#define MC_REGISTERS_TABLE_75__data_3_value_9_MASK 0xffffffff 1452#define MC_REGISTERS_TABLE_75__data_3_value_9__SHIFT 0x0 1453#define MC_REGISTERS_TABLE_76__data_3_value_10_MASK 0xffffffff 1454#define MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 0x0 1455#define MC_REGISTERS_TABLE_77__data_3_value_11_MASK 0xffffffff 1456#define MC_REGISTERS_TABLE_77__data_3_value_11__SHIFT 0x0 1457#define MC_REGISTERS_TABLE_78__data_3_value_12_MASK 0xffffffff 1458#define MC_REGISTERS_TABLE_78__data_3_value_12__SHIFT 0x0 1459#define MC_REGISTERS_TABLE_79__data_3_value_13_MASK 0xffffffff 1460#define MC_REGISTERS_TABLE_79__data_3_value_13__SHIFT 0x0 1461#define MC_REGISTERS_TABLE_80__data_3_value_14_MASK 0xffffffff 1462#define MC_REGISTERS_TABLE_80__data_3_value_14__SHIFT 0x0 1463#define MC_REGISTERS_TABLE_81__data_3_value_15_MASK 0xffffffff 1464#define MC_REGISTERS_TABLE_81__data_3_value_15__SHIFT 0x0 1465#define DPM_TABLE_1__GraphicsPIDController_Ki_MASK 0xffffffff 1466#define DPM_TABLE_1__GraphicsPIDController_Ki__SHIFT 0x0 1467#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff 1468#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0 1469#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff 1470#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0 1471#define DPM_TABLE_4__GraphicsPIDController_StatePrecision_MASK 0xffffffff 1472#define DPM_TABLE_4__GraphicsPIDController_StatePrecision__SHIFT 0x0 1473#define DPM_TABLE_5__GraphicsPIDController_LfPrecision_MASK 0xffffffff 1474#define DPM_TABLE_5__GraphicsPIDController_LfPrecision__SHIFT 0x0 1475#define DPM_TABLE_6__GraphicsPIDController_LfOffset_MASK 0xffffffff 1476#define DPM_TABLE_6__GraphicsPIDController_LfOffset__SHIFT 0x0 1477#define DPM_TABLE_7__GraphicsPIDController_MaxState_MASK 0xffffffff 1478#define DPM_TABLE_7__GraphicsPIDController_MaxState__SHIFT 0x0 1479#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff 1480#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction__SHIFT 0x0 1481#define DPM_TABLE_9__GraphicsPIDController_StateShift_MASK 0xffffffff 1482#define DPM_TABLE_9__GraphicsPIDController_StateShift__SHIFT 0x0 1483#define DPM_TABLE_10__MemoryPIDController_Ki_MASK 0xffffffff 1484#define DPM_TABLE_10__MemoryPIDController_Ki__SHIFT 0x0 1485#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim_MASK 0xffffffff 1486#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim__SHIFT 0x0 1487#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim_MASK 0xffffffff 1488#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim__SHIFT 0x0 1489#define DPM_TABLE_13__MemoryPIDController_StatePrecision_MASK 0xffffffff 1490#define DPM_TABLE_13__MemoryPIDController_StatePrecision__SHIFT 0x0 1491#define DPM_TABLE_14__MemoryPIDController_LfPrecision_MASK 0xffffffff 1492#define DPM_TABLE_14__MemoryPIDController_LfPrecision__SHIFT 0x0 1493#define DPM_TABLE_15__MemoryPIDController_LfOffset_MASK 0xffffffff 1494#define DPM_TABLE_15__MemoryPIDController_LfOffset__SHIFT 0x0 1495#define DPM_TABLE_16__MemoryPIDController_MaxState_MASK 0xffffffff 1496#define DPM_TABLE_16__MemoryPIDController_MaxState__SHIFT 0x0 1497#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction_MASK 0xffffffff 1498#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction__SHIFT 0x0 1499#define DPM_TABLE_18__MemoryPIDController_StateShift_MASK 0xffffffff 1500#define DPM_TABLE_18__MemoryPIDController_StateShift__SHIFT 0x0 1501#define DPM_TABLE_19__LinkPIDController_Ki_MASK 0xffffffff 1502#define DPM_TABLE_19__LinkPIDController_Ki__SHIFT 0x0 1503#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim_MASK 0xffffffff 1504#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim__SHIFT 0x0 1505#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim_MASK 0xffffffff 1506#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim__SHIFT 0x0 1507#define DPM_TABLE_22__LinkPIDController_StatePrecision_MASK 0xffffffff 1508#define DPM_TABLE_22__LinkPIDController_StatePrecision__SHIFT 0x0 1509#define DPM_TABLE_23__LinkPIDController_LfPrecision_MASK 0xffffffff 1510#define DPM_TABLE_23__LinkPIDController_LfPrecision__SHIFT 0x0 1511#define DPM_TABLE_24__LinkPIDController_LfOffset_MASK 0xffffffff 1512#define DPM_TABLE_24__LinkPIDController_LfOffset__SHIFT 0x0 1513#define DPM_TABLE_25__LinkPIDController_MaxState_MASK 0xffffffff 1514#define DPM_TABLE_25__LinkPIDController_MaxState__SHIFT 0x0 1515#define DPM_TABLE_26__LinkPIDController_MaxLfFraction_MASK 0xffffffff 1516#define DPM_TABLE_26__LinkPIDController_MaxLfFraction__SHIFT 0x0 1517#define DPM_TABLE_27__LinkPIDController_StateShift_MASK 0xffffffff 1518#define DPM_TABLE_27__LinkPIDController_StateShift__SHIFT 0x0 1519#define DPM_TABLE_28__SystemFlags_MASK 0xffffffff 1520#define DPM_TABLE_28__SystemFlags__SHIFT 0x0 1521#define DPM_TABLE_29__SmioMaskVddcVid_MASK 0xffffffff 1522#define DPM_TABLE_29__SmioMaskVddcVid__SHIFT 0x0 1523#define DPM_TABLE_30__SmioMaskVddcPhase_MASK 0xffffffff 1524#define DPM_TABLE_30__SmioMaskVddcPhase__SHIFT 0x0 1525#define DPM_TABLE_31__SmioMaskVddciVid_MASK 0xffffffff 1526#define DPM_TABLE_31__SmioMaskVddciVid__SHIFT 0x0 1527#define DPM_TABLE_32__SmioMaskMvddVid_MASK 0xffffffff 1528#define DPM_TABLE_32__SmioMaskMvddVid__SHIFT 0x0 1529#define DPM_TABLE_33__VddcLevelCount_MASK 0xffffffff 1530#define DPM_TABLE_33__VddcLevelCount__SHIFT 0x0 1531#define DPM_TABLE_34__VddciLevelCount_MASK 0xffffffff 1532#define DPM_TABLE_34__VddciLevelCount__SHIFT 0x0 1533#define DPM_TABLE_35__MvddLevelCount_MASK 0xffffffff 1534#define DPM_TABLE_35__MvddLevelCount__SHIFT 0x0 1535#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd_MASK 0xffff 1536#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd__SHIFT 0x0 1537#define DPM_TABLE_36__VddcLevel_0_Voltage_MASK 0xffff0000 1538#define DPM_TABLE_36__VddcLevel_0_Voltage__SHIFT 0x10 1539#define DPM_TABLE_37__VddcLevel_0_padding_MASK 0xff 1540#define DPM_TABLE_37__VddcLevel_0_padding__SHIFT 0x0 1541#define DPM_TABLE_37__VddcLevel_0_Smio_MASK 0xff00 1542#define DPM_TABLE_37__VddcLevel_0_Smio__SHIFT 0x8 1543#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd_MASK 0xffff0000 1544#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd__SHIFT 0x10 1545#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd_MASK 0xffff 1546#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd__SHIFT 0x0 1547#define DPM_TABLE_38__VddcLevel_1_Voltage_MASK 0xffff0000 1548#define DPM_TABLE_38__VddcLevel_1_Voltage__SHIFT 0x10 1549#define DPM_TABLE_39__VddcLevel_1_padding_MASK 0xff 1550#define DPM_TABLE_39__VddcLevel_1_padding__SHIFT 0x0 1551#define DPM_TABLE_39__VddcLevel_1_Smio_MASK 0xff00 1552#define DPM_TABLE_39__VddcLevel_1_Smio__SHIFT 0x8 1553#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd_MASK 0xffff0000 1554#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd__SHIFT 0x10 1555#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd_MASK 0xffff 1556#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd__SHIFT 0x0 1557#define DPM_TABLE_40__VddcLevel_2_Voltage_MASK 0xffff0000 1558#define DPM_TABLE_40__VddcLevel_2_Voltage__SHIFT 0x10 1559#define DPM_TABLE_41__VddcLevel_2_padding_MASK 0xff 1560#define DPM_TABLE_41__VddcLevel_2_padding__SHIFT 0x0 1561#define DPM_TABLE_41__VddcLevel_2_Smio_MASK 0xff00 1562#define DPM_TABLE_41__VddcLevel_2_Smio__SHIFT 0x8 1563#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd_MASK 0xffff0000 1564#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd__SHIFT 0x10 1565#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd_MASK 0xffff 1566#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd__SHIFT 0x0 1567#define DPM_TABLE_42__VddcLevel_3_Voltage_MASK 0xffff0000 1568#define DPM_TABLE_42__VddcLevel_3_Voltage__SHIFT 0x10 1569#define DPM_TABLE_43__VddcLevel_3_padding_MASK 0xff 1570#define DPM_TABLE_43__VddcLevel_3_padding__SHIFT 0x0 1571#define DPM_TABLE_43__VddcLevel_3_Smio_MASK 0xff00 1572#define DPM_TABLE_43__VddcLevel_3_Smio__SHIFT 0x8 1573#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd_MASK 0xffff0000 1574#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd__SHIFT 0x10 1575#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd_MASK 0xffff 1576#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd__SHIFT 0x0 1577#define DPM_TABLE_44__VddcLevel_4_Voltage_MASK 0xffff0000 1578#define DPM_TABLE_44__VddcLevel_4_Voltage__SHIFT 0x10 1579#define DPM_TABLE_45__VddcLevel_4_padding_MASK 0xff 1580#define DPM_TABLE_45__VddcLevel_4_padding__SHIFT 0x0 1581#define DPM_TABLE_45__VddcLevel_4_Smio_MASK 0xff00 1582#define DPM_TABLE_45__VddcLevel_4_Smio__SHIFT 0x8 1583#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd_MASK 0xffff0000 1584#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd__SHIFT 0x10 1585#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd_MASK 0xffff 1586#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd__SHIFT 0x0 1587#define DPM_TABLE_46__VddcLevel_5_Voltage_MASK 0xffff0000 1588#define DPM_TABLE_46__VddcLevel_5_Voltage__SHIFT 0x10 1589#define DPM_TABLE_47__VddcLevel_5_padding_MASK 0xff 1590#define DPM_TABLE_47__VddcLevel_5_padding__SHIFT 0x0 1591#define DPM_TABLE_47__VddcLevel_5_Smio_MASK 0xff00 1592#define DPM_TABLE_47__VddcLevel_5_Smio__SHIFT 0x8 1593#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd_MASK 0xffff0000 1594#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd__SHIFT 0x10 1595#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd_MASK 0xffff 1596#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd__SHIFT 0x0 1597#define DPM_TABLE_48__VddcLevel_6_Voltage_MASK 0xffff0000 1598#define DPM_TABLE_48__VddcLevel_6_Voltage__SHIFT 0x10 1599#define DPM_TABLE_49__VddcLevel_6_padding_MASK 0xff 1600#define DPM_TABLE_49__VddcLevel_6_padding__SHIFT 0x0 1601#define DPM_TABLE_49__VddcLevel_6_Smio_MASK 0xff00 1602#define DPM_TABLE_49__VddcLevel_6_Smio__SHIFT 0x8 1603#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd_MASK 0xffff0000 1604#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd__SHIFT 0x10 1605#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd_MASK 0xffff 1606#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd__SHIFT 0x0 1607#define DPM_TABLE_50__VddcLevel_7_Voltage_MASK 0xffff0000 1608#define DPM_TABLE_50__VddcLevel_7_Voltage__SHIFT 0x10 1609#define DPM_TABLE_51__VddcLevel_7_padding_MASK 0xff 1610#define DPM_TABLE_51__VddcLevel_7_padding__SHIFT 0x0 1611#define DPM_TABLE_51__VddcLevel_7_Smio_MASK 0xff00 1612#define DPM_TABLE_51__VddcLevel_7_Smio__SHIFT 0x8 1613#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd_MASK 0xffff0000 1614#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd__SHIFT 0x10 1615#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd_MASK 0xffff 1616#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd__SHIFT 0x0 1617#define DPM_TABLE_52__VddciLevel_0_Voltage_MASK 0xffff0000 1618#define DPM_TABLE_52__VddciLevel_0_Voltage__SHIFT 0x10 1619#define DPM_TABLE_53__VddciLevel_0_padding_MASK 0xff 1620#define DPM_TABLE_53__VddciLevel_0_padding__SHIFT 0x0 1621#define DPM_TABLE_53__VddciLevel_0_Smio_MASK 0xff00 1622#define DPM_TABLE_53__VddciLevel_0_Smio__SHIFT 0x8 1623#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd_MASK 0xffff0000 1624#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd__SHIFT 0x10 1625#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd_MASK 0xffff 1626#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd__SHIFT 0x0 1627#define DPM_TABLE_54__VddciLevel_1_Voltage_MASK 0xffff0000 1628#define DPM_TABLE_54__VddciLevel_1_Voltage__SHIFT 0x10 1629#define DPM_TABLE_55__VddciLevel_1_padding_MASK 0xff 1630#define DPM_TABLE_55__VddciLevel_1_padding__SHIFT 0x0 1631#define DPM_TABLE_55__VddciLevel_1_Smio_MASK 0xff00 1632#define DPM_TABLE_55__VddciLevel_1_Smio__SHIFT 0x8 1633#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd_MASK 0xffff0000 1634#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd__SHIFT 0x10 1635#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd_MASK 0xffff 1636#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd__SHIFT 0x0 1637#define DPM_TABLE_56__VddciLevel_2_Voltage_MASK 0xffff0000 1638#define DPM_TABLE_56__VddciLevel_2_Voltage__SHIFT 0x10 1639#define DPM_TABLE_57__VddciLevel_2_padding_MASK 0xff 1640#define DPM_TABLE_57__VddciLevel_2_padding__SHIFT 0x0 1641#define DPM_TABLE_57__VddciLevel_2_Smio_MASK 0xff00 1642#define DPM_TABLE_57__VddciLevel_2_Smio__SHIFT 0x8 1643#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd_MASK 0xffff0000 1644#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd__SHIFT 0x10 1645#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd_MASK 0xffff 1646#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd__SHIFT 0x0 1647#define DPM_TABLE_58__VddciLevel_3_Voltage_MASK 0xffff0000 1648#define DPM_TABLE_58__VddciLevel_3_Voltage__SHIFT 0x10 1649#define DPM_TABLE_59__VddciLevel_3_padding_MASK 0xff 1650#define DPM_TABLE_59__VddciLevel_3_padding__SHIFT 0x0 1651#define DPM_TABLE_59__VddciLevel_3_Smio_MASK 0xff00 1652#define DPM_TABLE_59__VddciLevel_3_Smio__SHIFT 0x8 1653#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd_MASK 0xffff0000 1654#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd__SHIFT 0x10 1655#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd_MASK 0xffff 1656#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd__SHIFT 0x0 1657#define DPM_TABLE_60__MvddLevel_0_Voltage_MASK 0xffff0000 1658#define DPM_TABLE_60__MvddLevel_0_Voltage__SHIFT 0x10 1659#define DPM_TABLE_61__MvddLevel_0_padding_MASK 0xff 1660#define DPM_TABLE_61__MvddLevel_0_padding__SHIFT 0x0 1661#define DPM_TABLE_61__MvddLevel_0_Smio_MASK 0xff00 1662#define DPM_TABLE_61__MvddLevel_0_Smio__SHIFT 0x8 1663#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd_MASK 0xffff0000 1664#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd__SHIFT 0x10 1665#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd_MASK 0xffff 1666#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd__SHIFT 0x0 1667#define DPM_TABLE_62__MvddLevel_1_Voltage_MASK 0xffff0000 1668#define DPM_TABLE_62__MvddLevel_1_Voltage__SHIFT 0x10 1669#define DPM_TABLE_63__MvddLevel_1_padding_MASK 0xff 1670#define DPM_TABLE_63__MvddLevel_1_padding__SHIFT 0x0 1671#define DPM_TABLE_63__MvddLevel_1_Smio_MASK 0xff00 1672#define DPM_TABLE_63__MvddLevel_1_Smio__SHIFT 0x8 1673#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd_MASK 0xffff0000 1674#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd__SHIFT 0x10 1675#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd_MASK 0xffff 1676#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd__SHIFT 0x0 1677#define DPM_TABLE_64__MvddLevel_2_Voltage_MASK 0xffff0000 1678#define DPM_TABLE_64__MvddLevel_2_Voltage__SHIFT 0x10 1679#define DPM_TABLE_65__MvddLevel_2_padding_MASK 0xff 1680#define DPM_TABLE_65__MvddLevel_2_padding__SHIFT 0x0 1681#define DPM_TABLE_65__MvddLevel_2_Smio_MASK 0xff00 1682#define DPM_TABLE_65__MvddLevel_2_Smio__SHIFT 0x8 1683#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd_MASK 0xffff0000 1684#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd__SHIFT 0x10 1685#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd_MASK 0xffff 1686#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd__SHIFT 0x0 1687#define DPM_TABLE_66__MvddLevel_3_Voltage_MASK 0xffff0000 1688#define DPM_TABLE_66__MvddLevel_3_Voltage__SHIFT 0x10 1689#define DPM_TABLE_67__MvddLevel_3_padding_MASK 0xff 1690#define DPM_TABLE_67__MvddLevel_3_padding__SHIFT 0x0 1691#define DPM_TABLE_67__MvddLevel_3_Smio_MASK 0xff00 1692#define DPM_TABLE_67__MvddLevel_3_Smio__SHIFT 0x8 1693#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd_MASK 0xffff0000 1694#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd__SHIFT 0x10 1695#define DPM_TABLE_68__MasterDeepSleepControl_MASK 0xff 1696#define DPM_TABLE_68__MasterDeepSleepControl__SHIFT 0x0 1697#define DPM_TABLE_68__LinkLevelCount_MASK 0xff00 1698#define DPM_TABLE_68__LinkLevelCount__SHIFT 0x8 1699#define DPM_TABLE_68__MemoryDpmLevelCount_MASK 0xff0000 1700#define DPM_TABLE_68__MemoryDpmLevelCount__SHIFT 0x10 1701#define DPM_TABLE_68__GraphicsDpmLevelCount_MASK 0xff000000 1702#define DPM_TABLE_68__GraphicsDpmLevelCount__SHIFT 0x18 1703#define DPM_TABLE_69__Reserved_0_MASK 0xffffffff 1704#define DPM_TABLE_69__Reserved_0__SHIFT 0x0 1705#define DPM_TABLE_70__Reserved_1_MASK 0xffffffff 1706#define DPM_TABLE_70__Reserved_1__SHIFT 0x0 1707#define DPM_TABLE_71__Reserved_2_MASK 0xffffffff 1708#define DPM_TABLE_71__Reserved_2__SHIFT 0x0 1709#define DPM_TABLE_72__Reserved_3_MASK 0xffffffff 1710#define DPM_TABLE_72__Reserved_3__SHIFT 0x0 1711#define DPM_TABLE_73__Reserved_4_MASK 0xffffffff 1712#define DPM_TABLE_73__Reserved_4__SHIFT 0x0 1713#define DPM_TABLE_74__GraphicsLevel_0_MinVddc_MASK 0xffffffff 1714#define DPM_TABLE_74__GraphicsLevel_0_MinVddc__SHIFT 0x0 1715#define DPM_TABLE_75__GraphicsLevel_0_MinVddcPhases_MASK 0xffffffff 1716#define DPM_TABLE_75__GraphicsLevel_0_MinVddcPhases__SHIFT 0x0 1717#define DPM_TABLE_76__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff 1718#define DPM_TABLE_76__GraphicsLevel_0_SclkFrequency__SHIFT 0x0 1719#define DPM_TABLE_77__GraphicsLevel_0_ActivityLevel_MASK 0xffff 1720#define DPM_TABLE_77__GraphicsLevel_0_ActivityLevel__SHIFT 0x0 1721#define DPM_TABLE_77__GraphicsLevel_0_DeepSleepDivId_MASK 0xff0000 1722#define DPM_TABLE_77__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x10 1723#define DPM_TABLE_77__GraphicsLevel_0_pcieDpmLevel_MASK 0xff000000 1724#define DPM_TABLE_77__GraphicsLevel_0_pcieDpmLevel__SHIFT 0x18 1725#define DPM_TABLE_78__GraphicsLevel_0_CgSpllFuncCntl3_MASK 0xffffffff 1726#define DPM_TABLE_78__GraphicsLevel_0_CgSpllFuncCntl3__SHIFT 0x0 1727#define DPM_TABLE_79__GraphicsLevel_0_CgSpllFuncCntl4_MASK 0xffffffff 1728#define DPM_TABLE_79__GraphicsLevel_0_CgSpllFuncCntl4__SHIFT 0x0 1729#define DPM_TABLE_80__GraphicsLevel_0_SpllSpreadSpectrum_MASK 0xffffffff 1730#define DPM_TABLE_80__GraphicsLevel_0_SpllSpreadSpectrum__SHIFT 0x0 1731#define DPM_TABLE_81__GraphicsLevel_0_SpllSpreadSpectrum2_MASK 0xffffffff 1732#define DPM_TABLE_81__GraphicsLevel_0_SpllSpreadSpectrum2__SHIFT 0x0 1733#define DPM_TABLE_82__GraphicsLevel_0_CcPwrDynRm_MASK 0xffffffff 1734#define DPM_TABLE_82__GraphicsLevel_0_CcPwrDynRm__SHIFT 0x0 1735#define DPM_TABLE_83__GraphicsLevel_0_CcPwrDynRm1_MASK 0xffffffff 1736#define DPM_TABLE_83__GraphicsLevel_0_CcPwrDynRm1__SHIFT 0x0 1737#define DPM_TABLE_84__GraphicsLevel_0_EnabledForThrottle_MASK 0xff 1738#define DPM_TABLE_84__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x0 1739#define DPM_TABLE_84__GraphicsLevel_0_EnabledForActivity_MASK 0xff00 1740#define DPM_TABLE_84__GraphicsLevel_0_EnabledForActivity__SHIFT 0x8 1741#define DPM_TABLE_84__GraphicsLevel_0_DisplayWatermark_MASK 0xff0000 1742#define DPM_TABLE_84__GraphicsLevel_0_DisplayWatermark__SHIFT 0x10 1743#define DPM_TABLE_84__GraphicsLevel_0_SclkDid_MASK 0xff000000 1744#define DPM_TABLE_84__GraphicsLevel_0_SclkDid__SHIFT 0x18 1745#define DPM_TABLE_85__GraphicsLevel_0_PowerThrottle_MASK 0xff 1746#define DPM_TABLE_85__GraphicsLevel_0_PowerThrottle__SHIFT 0x0 1747#define DPM_TABLE_85__GraphicsLevel_0_VoltageDownHyst_MASK 0xff00 1748#define DPM_TABLE_85__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x8 1749#define DPM_TABLE_85__GraphicsLevel_0_DownHyst_MASK 0xff0000 1750#define DPM_TABLE_85__GraphicsLevel_0_DownHyst__SHIFT 0x10 1751#define DPM_TABLE_85__GraphicsLevel_0_UpHyst_MASK 0xff000000 1752#define DPM_TABLE_85__GraphicsLevel_0_UpHyst__SHIFT 0x18 1753#define DPM_TABLE_86__GraphicsLevel_1_MinVddc_MASK 0xffffffff 1754#define DPM_TABLE_86__GraphicsLevel_1_MinVddc__SHIFT 0x0 1755#define DPM_TABLE_87__GraphicsLevel_1_MinVddcPhases_MASK 0xffffffff 1756#define DPM_TABLE_87__GraphicsLevel_1_MinVddcPhases__SHIFT 0x0 1757#define DPM_TABLE_88__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff 1758#define DPM_TABLE_88__GraphicsLevel_1_SclkFrequency__SHIFT 0x0 1759#define DPM_TABLE_89__GraphicsLevel_1_ActivityLevel_MASK 0xffff 1760#define DPM_TABLE_89__GraphicsLevel_1_ActivityLevel__SHIFT 0x0 1761#define DPM_TABLE_89__GraphicsLevel_1_DeepSleepDivId_MASK 0xff0000 1762#define DPM_TABLE_89__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x10 1763#define DPM_TABLE_89__GraphicsLevel_1_pcieDpmLevel_MASK 0xff000000 1764#define DPM_TABLE_89__GraphicsLevel_1_pcieDpmLevel__SHIFT 0x18 1765#define DPM_TABLE_90__GraphicsLevel_1_CgSpllFuncCntl3_MASK 0xffffffff 1766#define DPM_TABLE_90__GraphicsLevel_1_CgSpllFuncCntl3__SHIFT 0x0 1767#define DPM_TABLE_91__GraphicsLevel_1_CgSpllFuncCntl4_MASK 0xffffffff 1768#define DPM_TABLE_91__GraphicsLevel_1_CgSpllFuncCntl4__SHIFT 0x0 1769#define DPM_TABLE_92__GraphicsLevel_1_SpllSpreadSpectrum_MASK 0xffffffff 1770#define DPM_TABLE_92__GraphicsLevel_1_SpllSpreadSpectrum__SHIFT 0x0 1771#define DPM_TABLE_93__GraphicsLevel_1_SpllSpreadSpectrum2_MASK 0xffffffff 1772#define DPM_TABLE_93__GraphicsLevel_1_SpllSpreadSpectrum2__SHIFT 0x0 1773#define DPM_TABLE_94__GraphicsLevel_1_CcPwrDynRm_MASK 0xffffffff 1774#define DPM_TABLE_94__GraphicsLevel_1_CcPwrDynRm__SHIFT 0x0 1775#define DPM_TABLE_95__GraphicsLevel_1_CcPwrDynRm1_MASK 0xffffffff 1776#define DPM_TABLE_95__GraphicsLevel_1_CcPwrDynRm1__SHIFT 0x0 1777#define DPM_TABLE_96__GraphicsLevel_1_EnabledForThrottle_MASK 0xff 1778#define DPM_TABLE_96__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x0 1779#define DPM_TABLE_96__GraphicsLevel_1_EnabledForActivity_MASK 0xff00 1780#define DPM_TABLE_96__GraphicsLevel_1_EnabledForActivity__SHIFT 0x8 1781#define DPM_TABLE_96__GraphicsLevel_1_DisplayWatermark_MASK 0xff0000 1782#define DPM_TABLE_96__GraphicsLevel_1_DisplayWatermark__SHIFT 0x10 1783#define DPM_TABLE_96__GraphicsLevel_1_SclkDid_MASK 0xff000000 1784#define DPM_TABLE_96__GraphicsLevel_1_SclkDid__SHIFT 0x18 1785#define DPM_TABLE_97__GraphicsLevel_1_PowerThrottle_MASK 0xff 1786#define DPM_TABLE_97__GraphicsLevel_1_PowerThrottle__SHIFT 0x0 1787#define DPM_TABLE_97__GraphicsLevel_1_VoltageDownHyst_MASK 0xff00 1788#define DPM_TABLE_97__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x8 1789#define DPM_TABLE_97__GraphicsLevel_1_DownHyst_MASK 0xff0000 1790#define DPM_TABLE_97__GraphicsLevel_1_DownHyst__SHIFT 0x10 1791#define DPM_TABLE_97__GraphicsLevel_1_UpHyst_MASK 0xff000000 1792#define DPM_TABLE_97__GraphicsLevel_1_UpHyst__SHIFT 0x18 1793#define DPM_TABLE_98__GraphicsLevel_2_MinVddc_MASK 0xffffffff 1794#define DPM_TABLE_98__GraphicsLevel_2_MinVddc__SHIFT 0x0 1795#define DPM_TABLE_99__GraphicsLevel_2_MinVddcPhases_MASK 0xffffffff 1796#define DPM_TABLE_99__GraphicsLevel_2_MinVddcPhases__SHIFT 0x0 1797#define DPM_TABLE_100__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff 1798#define DPM_TABLE_100__GraphicsLevel_2_SclkFrequency__SHIFT 0x0 1799#define DPM_TABLE_101__GraphicsLevel_2_ActivityLevel_MASK 0xffff 1800#define DPM_TABLE_101__GraphicsLevel_2_ActivityLevel__SHIFT 0x0 1801#define DPM_TABLE_101__GraphicsLevel_2_DeepSleepDivId_MASK 0xff0000 1802#define DPM_TABLE_101__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x10 1803#define DPM_TABLE_101__GraphicsLevel_2_pcieDpmLevel_MASK 0xff000000 1804#define DPM_TABLE_101__GraphicsLevel_2_pcieDpmLevel__SHIFT 0x18 1805#define DPM_TABLE_102__GraphicsLevel_2_CgSpllFuncCntl3_MASK 0xffffffff 1806#define DPM_TABLE_102__GraphicsLevel_2_CgSpllFuncCntl3__SHIFT 0x0 1807#define DPM_TABLE_103__GraphicsLevel_2_CgSpllFuncCntl4_MASK 0xffffffff 1808#define DPM_TABLE_103__GraphicsLevel_2_CgSpllFuncCntl4__SHIFT 0x0 1809#define DPM_TABLE_104__GraphicsLevel_2_SpllSpreadSpectrum_MASK 0xffffffff 1810#define DPM_TABLE_104__GraphicsLevel_2_SpllSpreadSpectrum__SHIFT 0x0 1811#define DPM_TABLE_105__GraphicsLevel_2_SpllSpreadSpectrum2_MASK 0xffffffff 1812#define DPM_TABLE_105__GraphicsLevel_2_SpllSpreadSpectrum2__SHIFT 0x0 1813#define DPM_TABLE_106__GraphicsLevel_2_CcPwrDynRm_MASK 0xffffffff 1814#define DPM_TABLE_106__GraphicsLevel_2_CcPwrDynRm__SHIFT 0x0 1815#define DPM_TABLE_107__GraphicsLevel_2_CcPwrDynRm1_MASK 0xffffffff 1816#define DPM_TABLE_107__GraphicsLevel_2_CcPwrDynRm1__SHIFT 0x0 1817#define DPM_TABLE_108__GraphicsLevel_2_EnabledForThrottle_MASK 0xff 1818#define DPM_TABLE_108__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x0 1819#define DPM_TABLE_108__GraphicsLevel_2_EnabledForActivity_MASK 0xff00 1820#define DPM_TABLE_108__GraphicsLevel_2_EnabledForActivity__SHIFT 0x8 1821#define DPM_TABLE_108__GraphicsLevel_2_DisplayWatermark_MASK 0xff0000 1822#define DPM_TABLE_108__GraphicsLevel_2_DisplayWatermark__SHIFT 0x10 1823#define DPM_TABLE_108__GraphicsLevel_2_SclkDid_MASK 0xff000000 1824#define DPM_TABLE_108__GraphicsLevel_2_SclkDid__SHIFT 0x18 1825#define DPM_TABLE_109__GraphicsLevel_2_PowerThrottle_MASK 0xff 1826#define DPM_TABLE_109__GraphicsLevel_2_PowerThrottle__SHIFT 0x0 1827#define DPM_TABLE_109__GraphicsLevel_2_VoltageDownHyst_MASK 0xff00 1828#define DPM_TABLE_109__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x8 1829#define DPM_TABLE_109__GraphicsLevel_2_DownHyst_MASK 0xff0000 1830#define DPM_TABLE_109__GraphicsLevel_2_DownHyst__SHIFT 0x10 1831#define DPM_TABLE_109__GraphicsLevel_2_UpHyst_MASK 0xff000000 1832#define DPM_TABLE_109__GraphicsLevel_2_UpHyst__SHIFT 0x18 1833#define DPM_TABLE_110__GraphicsLevel_3_MinVddc_MASK 0xffffffff 1834#define DPM_TABLE_110__GraphicsLevel_3_MinVddc__SHIFT 0x0 1835#define DPM_TABLE_111__GraphicsLevel_3_MinVddcPhases_MASK 0xffffffff 1836#define DPM_TABLE_111__GraphicsLevel_3_MinVddcPhases__SHIFT 0x0 1837#define DPM_TABLE_112__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff 1838#define DPM_TABLE_112__GraphicsLevel_3_SclkFrequency__SHIFT 0x0 1839#define DPM_TABLE_113__GraphicsLevel_3_ActivityLevel_MASK 0xffff 1840#define DPM_TABLE_113__GraphicsLevel_3_ActivityLevel__SHIFT 0x0 1841#define DPM_TABLE_113__GraphicsLevel_3_DeepSleepDivId_MASK 0xff0000 1842#define DPM_TABLE_113__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x10 1843#define DPM_TABLE_113__GraphicsLevel_3_pcieDpmLevel_MASK 0xff000000 1844#define DPM_TABLE_113__GraphicsLevel_3_pcieDpmLevel__SHIFT 0x18 1845#define DPM_TABLE_114__GraphicsLevel_3_CgSpllFuncCntl3_MASK 0xffffffff 1846#define DPM_TABLE_114__GraphicsLevel_3_CgSpllFuncCntl3__SHIFT 0x0 1847#define DPM_TABLE_115__GraphicsLevel_3_CgSpllFuncCntl4_MASK 0xffffffff 1848#define DPM_TABLE_115__GraphicsLevel_3_CgSpllFuncCntl4__SHIFT 0x0 1849#define DPM_TABLE_116__GraphicsLevel_3_SpllSpreadSpectrum_MASK 0xffffffff 1850#define DPM_TABLE_116__GraphicsLevel_3_SpllSpreadSpectrum__SHIFT 0x0 1851#define DPM_TABLE_117__GraphicsLevel_3_SpllSpreadSpectrum2_MASK 0xffffffff 1852#define DPM_TABLE_117__GraphicsLevel_3_SpllSpreadSpectrum2__SHIFT 0x0 1853#define DPM_TABLE_118__GraphicsLevel_3_CcPwrDynRm_MASK 0xffffffff 1854#define DPM_TABLE_118__GraphicsLevel_3_CcPwrDynRm__SHIFT 0x0 1855#define DPM_TABLE_119__GraphicsLevel_3_CcPwrDynRm1_MASK 0xffffffff 1856#define DPM_TABLE_119__GraphicsLevel_3_CcPwrDynRm1__SHIFT 0x0 1857#define DPM_TABLE_120__GraphicsLevel_3_EnabledForThrottle_MASK 0xff 1858#define DPM_TABLE_120__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x0 1859#define DPM_TABLE_120__GraphicsLevel_3_EnabledForActivity_MASK 0xff00 1860#define DPM_TABLE_120__GraphicsLevel_3_EnabledForActivity__SHIFT 0x8 1861#define DPM_TABLE_120__GraphicsLevel_3_DisplayWatermark_MASK 0xff0000 1862#define DPM_TABLE_120__GraphicsLevel_3_DisplayWatermark__SHIFT 0x10 1863#define DPM_TABLE_120__GraphicsLevel_3_SclkDid_MASK 0xff000000 1864#define DPM_TABLE_120__GraphicsLevel_3_SclkDid__SHIFT 0x18 1865#define DPM_TABLE_121__GraphicsLevel_3_PowerThrottle_MASK 0xff 1866#define DPM_TABLE_121__GraphicsLevel_3_PowerThrottle__SHIFT 0x0 1867#define DPM_TABLE_121__GraphicsLevel_3_VoltageDownHyst_MASK 0xff00 1868#define DPM_TABLE_121__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x8 1869#define DPM_TABLE_121__GraphicsLevel_3_DownHyst_MASK 0xff0000 1870#define DPM_TABLE_121__GraphicsLevel_3_DownHyst__SHIFT 0x10 1871#define DPM_TABLE_121__GraphicsLevel_3_UpHyst_MASK 0xff000000 1872#define DPM_TABLE_121__GraphicsLevel_3_UpHyst__SHIFT 0x18 1873#define DPM_TABLE_122__GraphicsLevel_4_MinVddc_MASK 0xffffffff 1874#define DPM_TABLE_122__GraphicsLevel_4_MinVddc__SHIFT 0x0 1875#define DPM_TABLE_123__GraphicsLevel_4_MinVddcPhases_MASK 0xffffffff 1876#define DPM_TABLE_123__GraphicsLevel_4_MinVddcPhases__SHIFT 0x0 1877#define DPM_TABLE_124__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff 1878#define DPM_TABLE_124__GraphicsLevel_4_SclkFrequency__SHIFT 0x0 1879#define DPM_TABLE_125__GraphicsLevel_4_ActivityLevel_MASK 0xffff 1880#define DPM_TABLE_125__GraphicsLevel_4_ActivityLevel__SHIFT 0x0 1881#define DPM_TABLE_125__GraphicsLevel_4_DeepSleepDivId_MASK 0xff0000 1882#define DPM_TABLE_125__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x10 1883#define DPM_TABLE_125__GraphicsLevel_4_pcieDpmLevel_MASK 0xff000000 1884#define DPM_TABLE_125__GraphicsLevel_4_pcieDpmLevel__SHIFT 0x18 1885#define DPM_TABLE_126__GraphicsLevel_4_CgSpllFuncCntl3_MASK 0xffffffff 1886#define DPM_TABLE_126__GraphicsLevel_4_CgSpllFuncCntl3__SHIFT 0x0 1887#define DPM_TABLE_127__GraphicsLevel_4_CgSpllFuncCntl4_MASK 0xffffffff 1888#define DPM_TABLE_127__GraphicsLevel_4_CgSpllFuncCntl4__SHIFT 0x0 1889#define DPM_TABLE_128__GraphicsLevel_4_SpllSpreadSpectrum_MASK 0xffffffff 1890#define DPM_TABLE_128__GraphicsLevel_4_SpllSpreadSpectrum__SHIFT 0x0 1891#define DPM_TABLE_129__GraphicsLevel_4_SpllSpreadSpectrum2_MASK 0xffffffff 1892#define DPM_TABLE_129__GraphicsLevel_4_SpllSpreadSpectrum2__SHIFT 0x0 1893#define DPM_TABLE_130__GraphicsLevel_4_CcPwrDynRm_MASK 0xffffffff 1894#define DPM_TABLE_130__GraphicsLevel_4_CcPwrDynRm__SHIFT 0x0 1895#define DPM_TABLE_131__GraphicsLevel_4_CcPwrDynRm1_MASK 0xffffffff 1896#define DPM_TABLE_131__GraphicsLevel_4_CcPwrDynRm1__SHIFT 0x0 1897#define DPM_TABLE_132__GraphicsLevel_4_EnabledForThrottle_MASK 0xff 1898#define DPM_TABLE_132__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x0 1899#define DPM_TABLE_132__GraphicsLevel_4_EnabledForActivity_MASK 0xff00 1900#define DPM_TABLE_132__GraphicsLevel_4_EnabledForActivity__SHIFT 0x8 1901#define DPM_TABLE_132__GraphicsLevel_4_DisplayWatermark_MASK 0xff0000 1902#define DPM_TABLE_132__GraphicsLevel_4_DisplayWatermark__SHIFT 0x10 1903#define DPM_TABLE_132__GraphicsLevel_4_SclkDid_MASK 0xff000000 1904#define DPM_TABLE_132__GraphicsLevel_4_SclkDid__SHIFT 0x18 1905#define DPM_TABLE_133__GraphicsLevel_4_PowerThrottle_MASK 0xff 1906#define DPM_TABLE_133__GraphicsLevel_4_PowerThrottle__SHIFT 0x0 1907#define DPM_TABLE_133__GraphicsLevel_4_VoltageDownHyst_MASK 0xff00 1908#define DPM_TABLE_133__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x8 1909#define DPM_TABLE_133__GraphicsLevel_4_DownHyst_MASK 0xff0000 1910#define DPM_TABLE_133__GraphicsLevel_4_DownHyst__SHIFT 0x10 1911#define DPM_TABLE_133__GraphicsLevel_4_UpHyst_MASK 0xff000000 1912#define DPM_TABLE_133__GraphicsLevel_4_UpHyst__SHIFT 0x18 1913#define DPM_TABLE_134__GraphicsLevel_5_MinVddc_MASK 0xffffffff 1914#define DPM_TABLE_134__GraphicsLevel_5_MinVddc__SHIFT 0x0 1915#define DPM_TABLE_135__GraphicsLevel_5_MinVddcPhases_MASK 0xffffffff 1916#define DPM_TABLE_135__GraphicsLevel_5_MinVddcPhases__SHIFT 0x0 1917#define DPM_TABLE_136__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff 1918#define DPM_TABLE_136__GraphicsLevel_5_SclkFrequency__SHIFT 0x0 1919#define DPM_TABLE_137__GraphicsLevel_5_ActivityLevel_MASK 0xffff 1920#define DPM_TABLE_137__GraphicsLevel_5_ActivityLevel__SHIFT 0x0 1921#define DPM_TABLE_137__GraphicsLevel_5_DeepSleepDivId_MASK 0xff0000 1922#define DPM_TABLE_137__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x10 1923#define DPM_TABLE_137__GraphicsLevel_5_pcieDpmLevel_MASK 0xff000000 1924#define DPM_TABLE_137__GraphicsLevel_5_pcieDpmLevel__SHIFT 0x18 1925#define DPM_TABLE_138__GraphicsLevel_5_CgSpllFuncCntl3_MASK 0xffffffff 1926#define DPM_TABLE_138__GraphicsLevel_5_CgSpllFuncCntl3__SHIFT 0x0 1927#define DPM_TABLE_139__GraphicsLevel_5_CgSpllFuncCntl4_MASK 0xffffffff 1928#define DPM_TABLE_139__GraphicsLevel_5_CgSpllFuncCntl4__SHIFT 0x0 1929#define DPM_TABLE_140__GraphicsLevel_5_SpllSpreadSpectrum_MASK 0xffffffff 1930#define DPM_TABLE_140__GraphicsLevel_5_SpllSpreadSpectrum__SHIFT 0x0 1931#define DPM_TABLE_141__GraphicsLevel_5_SpllSpreadSpectrum2_MASK 0xffffffff 1932#define DPM_TABLE_141__GraphicsLevel_5_SpllSpreadSpectrum2__SHIFT 0x0 1933#define DPM_TABLE_142__GraphicsLevel_5_CcPwrDynRm_MASK 0xffffffff 1934#define DPM_TABLE_142__GraphicsLevel_5_CcPwrDynRm__SHIFT 0x0 1935#define DPM_TABLE_143__GraphicsLevel_5_CcPwrDynRm1_MASK 0xffffffff 1936#define DPM_TABLE_143__GraphicsLevel_5_CcPwrDynRm1__SHIFT 0x0 1937#define DPM_TABLE_144__GraphicsLevel_5_EnabledForThrottle_MASK 0xff 1938#define DPM_TABLE_144__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x0 1939#define DPM_TABLE_144__GraphicsLevel_5_EnabledForActivity_MASK 0xff00 1940#define DPM_TABLE_144__GraphicsLevel_5_EnabledForActivity__SHIFT 0x8 1941#define DPM_TABLE_144__GraphicsLevel_5_DisplayWatermark_MASK 0xff0000 1942#define DPM_TABLE_144__GraphicsLevel_5_DisplayWatermark__SHIFT 0x10 1943#define DPM_TABLE_144__GraphicsLevel_5_SclkDid_MASK 0xff000000 1944#define DPM_TABLE_144__GraphicsLevel_5_SclkDid__SHIFT 0x18 1945#define DPM_TABLE_145__GraphicsLevel_5_PowerThrottle_MASK 0xff 1946#define DPM_TABLE_145__GraphicsLevel_5_PowerThrottle__SHIFT 0x0 1947#define DPM_TABLE_145__GraphicsLevel_5_VoltageDownHyst_MASK 0xff00 1948#define DPM_TABLE_145__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x8 1949#define DPM_TABLE_145__GraphicsLevel_5_DownHyst_MASK 0xff0000 1950#define DPM_TABLE_145__GraphicsLevel_5_DownHyst__SHIFT 0x10 1951#define DPM_TABLE_145__GraphicsLevel_5_UpHyst_MASK 0xff000000 1952#define DPM_TABLE_145__GraphicsLevel_5_UpHyst__SHIFT 0x18 1953#define DPM_TABLE_146__GraphicsLevel_6_MinVddc_MASK 0xffffffff 1954#define DPM_TABLE_146__GraphicsLevel_6_MinVddc__SHIFT 0x0 1955#define DPM_TABLE_147__GraphicsLevel_6_MinVddcPhases_MASK 0xffffffff 1956#define DPM_TABLE_147__GraphicsLevel_6_MinVddcPhases__SHIFT 0x0 1957#define DPM_TABLE_148__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff 1958#define DPM_TABLE_148__GraphicsLevel_6_SclkFrequency__SHIFT 0x0 1959#define DPM_TABLE_149__GraphicsLevel_6_ActivityLevel_MASK 0xffff 1960#define DPM_TABLE_149__GraphicsLevel_6_ActivityLevel__SHIFT 0x0 1961#define DPM_TABLE_149__GraphicsLevel_6_DeepSleepDivId_MASK 0xff0000 1962#define DPM_TABLE_149__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x10 1963#define DPM_TABLE_149__GraphicsLevel_6_pcieDpmLevel_MASK 0xff000000 1964#define DPM_TABLE_149__GraphicsLevel_6_pcieDpmLevel__SHIFT 0x18 1965#define DPM_TABLE_150__GraphicsLevel_6_CgSpllFuncCntl3_MASK 0xffffffff 1966#define DPM_TABLE_150__GraphicsLevel_6_CgSpllFuncCntl3__SHIFT 0x0 1967#define DPM_TABLE_151__GraphicsLevel_6_CgSpllFuncCntl4_MASK 0xffffffff 1968#define DPM_TABLE_151__GraphicsLevel_6_CgSpllFuncCntl4__SHIFT 0x0 1969#define DPM_TABLE_152__GraphicsLevel_6_SpllSpreadSpectrum_MASK 0xffffffff 1970#define DPM_TABLE_152__GraphicsLevel_6_SpllSpreadSpectrum__SHIFT 0x0 1971#define DPM_TABLE_153__GraphicsLevel_6_SpllSpreadSpectrum2_MASK 0xffffffff 1972#define DPM_TABLE_153__GraphicsLevel_6_SpllSpreadSpectrum2__SHIFT 0x0 1973#define DPM_TABLE_154__GraphicsLevel_6_CcPwrDynRm_MASK 0xffffffff 1974#define DPM_TABLE_154__GraphicsLevel_6_CcPwrDynRm__SHIFT 0x0 1975#define DPM_TABLE_155__GraphicsLevel_6_CcPwrDynRm1_MASK 0xffffffff 1976#define DPM_TABLE_155__GraphicsLevel_6_CcPwrDynRm1__SHIFT 0x0 1977#define DPM_TABLE_156__GraphicsLevel_6_EnabledForThrottle_MASK 0xff 1978#define DPM_TABLE_156__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x0 1979#define DPM_TABLE_156__GraphicsLevel_6_EnabledForActivity_MASK 0xff00 1980#define DPM_TABLE_156__GraphicsLevel_6_EnabledForActivity__SHIFT 0x8 1981#define DPM_TABLE_156__GraphicsLevel_6_DisplayWatermark_MASK 0xff0000 1982#define DPM_TABLE_156__GraphicsLevel_6_DisplayWatermark__SHIFT 0x10 1983#define DPM_TABLE_156__GraphicsLevel_6_SclkDid_MASK 0xff000000 1984#define DPM_TABLE_156__GraphicsLevel_6_SclkDid__SHIFT 0x18 1985#define DPM_TABLE_157__GraphicsLevel_6_PowerThrottle_MASK 0xff 1986#define DPM_TABLE_157__GraphicsLevel_6_PowerThrottle__SHIFT 0x0 1987#define DPM_TABLE_157__GraphicsLevel_6_VoltageDownHyst_MASK 0xff00 1988#define DPM_TABLE_157__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x8 1989#define DPM_TABLE_157__GraphicsLevel_6_DownHyst_MASK 0xff0000 1990#define DPM_TABLE_157__GraphicsLevel_6_DownHyst__SHIFT 0x10 1991#define DPM_TABLE_157__GraphicsLevel_6_UpHyst_MASK 0xff000000 1992#define DPM_TABLE_157__GraphicsLevel_6_UpHyst__SHIFT 0x18 1993#define DPM_TABLE_158__GraphicsLevel_7_MinVddc_MASK 0xffffffff 1994#define DPM_TABLE_158__GraphicsLevel_7_MinVddc__SHIFT 0x0 1995#define DPM_TABLE_159__GraphicsLevel_7_MinVddcPhases_MASK 0xffffffff 1996#define DPM_TABLE_159__GraphicsLevel_7_MinVddcPhases__SHIFT 0x0 1997#define DPM_TABLE_160__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff 1998#define DPM_TABLE_160__GraphicsLevel_7_SclkFrequency__SHIFT 0x0 1999#define DPM_TABLE_161__GraphicsLevel_7_ActivityLevel_MASK 0xffff 2000#define DPM_TABLE_161__GraphicsLevel_7_ActivityLevel__SHIFT 0x0 2001#define DPM_TABLE_161__GraphicsLevel_7_DeepSleepDivId_MASK 0xff0000 2002#define DPM_TABLE_161__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x10 2003#define DPM_TABLE_161__GraphicsLevel_7_pcieDpmLevel_MASK 0xff000000 2004#define DPM_TABLE_161__GraphicsLevel_7_pcieDpmLevel__SHIFT 0x18 2005#define DPM_TABLE_162__GraphicsLevel_7_CgSpllFuncCntl3_MASK 0xffffffff 2006#define DPM_TABLE_162__GraphicsLevel_7_CgSpllFuncCntl3__SHIFT 0x0 2007#define DPM_TABLE_163__GraphicsLevel_7_CgSpllFuncCntl4_MASK 0xffffffff 2008#define DPM_TABLE_163__GraphicsLevel_7_CgSpllFuncCntl4__SHIFT 0x0 2009#define DPM_TABLE_164__GraphicsLevel_7_SpllSpreadSpectrum_MASK 0xffffffff 2010#define DPM_TABLE_164__GraphicsLevel_7_SpllSpreadSpectrum__SHIFT 0x0 2011#define DPM_TABLE_165__GraphicsLevel_7_SpllSpreadSpectrum2_MASK 0xffffffff 2012#define DPM_TABLE_165__GraphicsLevel_7_SpllSpreadSpectrum2__SHIFT 0x0 2013#define DPM_TABLE_166__GraphicsLevel_7_CcPwrDynRm_MASK 0xffffffff 2014#define DPM_TABLE_166__GraphicsLevel_7_CcPwrDynRm__SHIFT 0x0 2015#define DPM_TABLE_167__GraphicsLevel_7_CcPwrDynRm1_MASK 0xffffffff 2016#define DPM_TABLE_167__GraphicsLevel_7_CcPwrDynRm1__SHIFT 0x0 2017#define DPM_TABLE_168__GraphicsLevel_7_EnabledForThrottle_MASK 0xff 2018#define DPM_TABLE_168__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x0 2019#define DPM_TABLE_168__GraphicsLevel_7_EnabledForActivity_MASK 0xff00 2020#define DPM_TABLE_168__GraphicsLevel_7_EnabledForActivity__SHIFT 0x8 2021#define DPM_TABLE_168__GraphicsLevel_7_DisplayWatermark_MASK 0xff0000 2022#define DPM_TABLE_168__GraphicsLevel_7_DisplayWatermark__SHIFT 0x10 2023#define DPM_TABLE_168__GraphicsLevel_7_SclkDid_MASK 0xff000000 2024#define DPM_TABLE_168__GraphicsLevel_7_SclkDid__SHIFT 0x18 2025#define DPM_TABLE_169__GraphicsLevel_7_PowerThrottle_MASK 0xff 2026#define DPM_TABLE_169__GraphicsLevel_7_PowerThrottle__SHIFT 0x0 2027#define DPM_TABLE_169__GraphicsLevel_7_VoltageDownHyst_MASK 0xff00 2028#define DPM_TABLE_169__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x8 2029#define DPM_TABLE_169__GraphicsLevel_7_DownHyst_MASK 0xff0000 2030#define DPM_TABLE_169__GraphicsLevel_7_DownHyst__SHIFT 0x10 2031#define DPM_TABLE_169__GraphicsLevel_7_UpHyst_MASK 0xff000000 2032#define DPM_TABLE_169__GraphicsLevel_7_UpHyst__SHIFT 0x18 2033#define DPM_TABLE_170__MemoryACPILevel_MinVddc_MASK 0xffffffff 2034#define DPM_TABLE_170__MemoryACPILevel_MinVddc__SHIFT 0x0 2035#define DPM_TABLE_171__MemoryACPILevel_MinVddcPhases_MASK 0xffffffff 2036#define DPM_TABLE_171__MemoryACPILevel_MinVddcPhases__SHIFT 0x0 2037#define DPM_TABLE_172__MemoryACPILevel_MinVddci_MASK 0xffffffff 2038#define DPM_TABLE_172__MemoryACPILevel_MinVddci__SHIFT 0x0 2039#define DPM_TABLE_173__MemoryACPILevel_MinMvdd_MASK 0xffffffff 2040#define DPM_TABLE_173__MemoryACPILevel_MinMvdd__SHIFT 0x0 2041#define DPM_TABLE_174__MemoryACPILevel_MclkFrequency_MASK 0xffffffff 2042#define DPM_TABLE_174__MemoryACPILevel_MclkFrequency__SHIFT 0x0 2043#define DPM_TABLE_175__MemoryACPILevel_StutterEnable_MASK 0xff 2044#define DPM_TABLE_175__MemoryACPILevel_StutterEnable__SHIFT 0x0 2045#define DPM_TABLE_175__MemoryACPILevel_RttEnable_MASK 0xff00 2046#define DPM_TABLE_175__MemoryACPILevel_RttEnable__SHIFT 0x8 2047#define DPM_TABLE_175__MemoryACPILevel_EdcWriteEnable_MASK 0xff0000 2048#define DPM_TABLE_175__MemoryACPILevel_EdcWriteEnable__SHIFT 0x10 2049#define DPM_TABLE_175__MemoryACPILevel_EdcReadEnable_MASK 0xff000000 2050#define DPM_TABLE_175__MemoryACPILevel_EdcReadEnable__SHIFT 0x18 2051#define DPM_TABLE_176__MemoryACPILevel_EnabledForActivity_MASK 0xff 2052#define DPM_TABLE_176__MemoryACPILevel_EnabledForActivity__SHIFT 0x0 2053#define DPM_TABLE_176__MemoryACPILevel_EnabledForThrottle_MASK 0xff00 2054#define DPM_TABLE_176__MemoryACPILevel_EnabledForThrottle__SHIFT 0x8 2055#define DPM_TABLE_176__MemoryACPILevel_StrobeRatio_MASK 0xff0000 2056#define DPM_TABLE_176__MemoryACPILevel_StrobeRatio__SHIFT 0x10 2057#define DPM_TABLE_176__MemoryACPILevel_StrobeEnable_MASK 0xff000000 2058#define DPM_TABLE_176__MemoryACPILevel_StrobeEnable__SHIFT 0x18 2059#define DPM_TABLE_177__MemoryACPILevel_padding_MASK 0xff 2060#define DPM_TABLE_177__MemoryACPILevel_padding__SHIFT 0x0 2061#define DPM_TABLE_177__MemoryACPILevel_VoltageDownHyst_MASK 0xff00 2062#define DPM_TABLE_177__MemoryACPILevel_VoltageDownHyst__SHIFT 0x8 2063#define DPM_TABLE_177__MemoryACPILevel_DownHyst_MASK 0xff0000 2064#define DPM_TABLE_177__MemoryACPILevel_DownHyst__SHIFT 0x10 2065#define DPM_TABLE_177__MemoryACPILevel_UpHyst_MASK 0xff000000 2066#define DPM_TABLE_177__MemoryACPILevel_UpHyst__SHIFT 0x18 2067#define DPM_TABLE_178__MemoryACPILevel_padding1_MASK 0xff 2068#define DPM_TABLE_178__MemoryACPILevel_padding1__SHIFT 0x0 2069#define DPM_TABLE_178__MemoryACPILevel_DisplayWatermark_MASK 0xff00 2070#define DPM_TABLE_178__MemoryACPILevel_DisplayWatermark__SHIFT 0x8 2071#define DPM_TABLE_178__MemoryACPILevel_ActivityLevel_MASK 0xffff0000 2072#define DPM_TABLE_178__MemoryACPILevel_ActivityLevel__SHIFT 0x10 2073#define DPM_TABLE_179__MemoryACPILevel_MpllFuncCntl_MASK 0xffffffff 2074#define DPM_TABLE_179__MemoryACPILevel_MpllFuncCntl__SHIFT 0x0 2075#define DPM_TABLE_180__MemoryACPILevel_MpllFuncCntl_1_MASK 0xffffffff 2076#define DPM_TABLE_180__MemoryACPILevel_MpllFuncCntl_1__SHIFT 0x0 2077#define DPM_TABLE_181__MemoryACPILevel_MpllFuncCntl_2_MASK 0xffffffff 2078#define DPM_TABLE_181__MemoryACPILevel_MpllFuncCntl_2__SHIFT 0x0 2079#define DPM_TABLE_182__MemoryACPILevel_MpllAdFuncCntl_MASK 0xffffffff 2080#define DPM_TABLE_182__MemoryACPILevel_MpllAdFuncCntl__SHIFT 0x0 2081#define DPM_TABLE_183__MemoryACPILevel_MpllDqFuncCntl_MASK 0xffffffff 2082#define DPM_TABLE_183__MemoryACPILevel_MpllDqFuncCntl__SHIFT 0x0 2083#define DPM_TABLE_184__MemoryACPILevel_MclkPwrmgtCntl_MASK 0xffffffff 2084#define DPM_TABLE_184__MemoryACPILevel_MclkPwrmgtCntl__SHIFT 0x0 2085#define DPM_TABLE_185__MemoryACPILevel_DllCntl_MASK 0xffffffff 2086#define DPM_TABLE_185__MemoryACPILevel_DllCntl__SHIFT 0x0 2087#define DPM_TABLE_186__MemoryACPILevel_MpllSs1_MASK 0xffffffff 2088#define DPM_TABLE_186__MemoryACPILevel_MpllSs1__SHIFT 0x0 2089#define DPM_TABLE_187__MemoryACPILevel_MpllSs2_MASK 0xffffffff 2090#define DPM_TABLE_187__MemoryACPILevel_MpllSs2__SHIFT 0x0 2091#define DPM_TABLE_188__MemoryLevel_0_MinVddc_MASK 0xffffffff 2092#define DPM_TABLE_188__MemoryLevel_0_MinVddc__SHIFT 0x0 2093#define DPM_TABLE_189__MemoryLevel_0_MinVddcPhases_MASK 0xffffffff 2094#define DPM_TABLE_189__MemoryLevel_0_MinVddcPhases__SHIFT 0x0 2095#define DPM_TABLE_190__MemoryLevel_0_MinVddci_MASK 0xffffffff 2096#define DPM_TABLE_190__MemoryLevel_0_MinVddci__SHIFT 0x0 2097#define DPM_TABLE_191__MemoryLevel_0_MinMvdd_MASK 0xffffffff 2098#define DPM_TABLE_191__MemoryLevel_0_MinMvdd__SHIFT 0x0 2099#define DPM_TABLE_192__MemoryLevel_0_MclkFrequency_MASK 0xffffffff 2100#define DPM_TABLE_192__MemoryLevel_0_MclkFrequency__SHIFT 0x0 2101#define DPM_TABLE_193__MemoryLevel_0_StutterEnable_MASK 0xff 2102#define DPM_TABLE_193__MemoryLevel_0_StutterEnable__SHIFT 0x0 2103#define DPM_TABLE_193__MemoryLevel_0_RttEnable_MASK 0xff00 2104#define DPM_TABLE_193__MemoryLevel_0_RttEnable__SHIFT 0x8 2105#define DPM_TABLE_193__MemoryLevel_0_EdcWriteEnable_MASK 0xff0000 2106#define DPM_TABLE_193__MemoryLevel_0_EdcWriteEnable__SHIFT 0x10 2107#define DPM_TABLE_193__MemoryLevel_0_EdcReadEnable_MASK 0xff000000 2108#define DPM_TABLE_193__MemoryLevel_0_EdcReadEnable__SHIFT 0x18 2109#define DPM_TABLE_194__MemoryLevel_0_EnabledForActivity_MASK 0xff 2110#define DPM_TABLE_194__MemoryLevel_0_EnabledForActivity__SHIFT 0x0 2111#define DPM_TABLE_194__MemoryLevel_0_EnabledForThrottle_MASK 0xff00 2112#define DPM_TABLE_194__MemoryLevel_0_EnabledForThrottle__SHIFT 0x8 2113#define DPM_TABLE_194__MemoryLevel_0_StrobeRatio_MASK 0xff0000 2114#define DPM_TABLE_194__MemoryLevel_0_StrobeRatio__SHIFT 0x10 2115#define DPM_TABLE_194__MemoryLevel_0_StrobeEnable_MASK 0xff000000 2116#define DPM_TABLE_194__MemoryLevel_0_StrobeEnable__SHIFT 0x18 2117#define DPM_TABLE_195__MemoryLevel_0_padding_MASK 0xff 2118#define DPM_TABLE_195__MemoryLevel_0_padding__SHIFT 0x0 2119#define DPM_TABLE_195__MemoryLevel_0_VoltageDownHyst_MASK 0xff00 2120#define DPM_TABLE_195__MemoryLevel_0_VoltageDownHyst__SHIFT 0x8 2121#define DPM_TABLE_195__MemoryLevel_0_DownHyst_MASK 0xff0000 2122#define DPM_TABLE_195__MemoryLevel_0_DownHyst__SHIFT 0x10 2123#define DPM_TABLE_195__MemoryLevel_0_UpHyst_MASK 0xff000000 2124#define DPM_TABLE_195__MemoryLevel_0_UpHyst__SHIFT 0x18 2125#define DPM_TABLE_196__MemoryLevel_0_padding1_MASK 0xff 2126#define DPM_TABLE_196__MemoryLevel_0_padding1__SHIFT 0x0 2127#define DPM_TABLE_196__MemoryLevel_0_DisplayWatermark_MASK 0xff00 2128#define DPM_TABLE_196__MemoryLevel_0_DisplayWatermark__SHIFT 0x8 2129#define DPM_TABLE_196__MemoryLevel_0_ActivityLevel_MASK 0xffff0000 2130#define DPM_TABLE_196__MemoryLevel_0_ActivityLevel__SHIFT 0x10 2131#define DPM_TABLE_197__MemoryLevel_0_MpllFuncCntl_MASK 0xffffffff 2132#define DPM_TABLE_197__MemoryLevel_0_MpllFuncCntl__SHIFT 0x0 2133#define DPM_TABLE_198__MemoryLevel_0_MpllFuncCntl_1_MASK 0xffffffff 2134#define DPM_TABLE_198__MemoryLevel_0_MpllFuncCntl_1__SHIFT 0x0 2135#define DPM_TABLE_199__MemoryLevel_0_MpllFuncCntl_2_MASK 0xffffffff 2136#define DPM_TABLE_199__MemoryLevel_0_MpllFuncCntl_2__SHIFT 0x0 2137#define DPM_TABLE_200__MemoryLevel_0_MpllAdFuncCntl_MASK 0xffffffff 2138#define DPM_TABLE_200__MemoryLevel_0_MpllAdFuncCntl__SHIFT 0x0 2139#define DPM_TABLE_201__MemoryLevel_0_MpllDqFuncCntl_MASK 0xffffffff 2140#define DPM_TABLE_201__MemoryLevel_0_MpllDqFuncCntl__SHIFT 0x0 2141#define DPM_TABLE_202__MemoryLevel_0_MclkPwrmgtCntl_MASK 0xffffffff 2142#define DPM_TABLE_202__MemoryLevel_0_MclkPwrmgtCntl__SHIFT 0x0 2143#define DPM_TABLE_203__MemoryLevel_0_DllCntl_MASK 0xffffffff 2144#define DPM_TABLE_203__MemoryLevel_0_DllCntl__SHIFT 0x0 2145#define DPM_TABLE_204__MemoryLevel_0_MpllSs1_MASK 0xffffffff 2146#define DPM_TABLE_204__MemoryLevel_0_MpllSs1__SHIFT 0x0 2147#define DPM_TABLE_205__MemoryLevel_0_MpllSs2_MASK 0xffffffff 2148#define DPM_TABLE_205__MemoryLevel_0_MpllSs2__SHIFT 0x0 2149#define DPM_TABLE_206__MemoryLevel_1_MinVddc_MASK 0xffffffff 2150#define DPM_TABLE_206__MemoryLevel_1_MinVddc__SHIFT 0x0 2151#define DPM_TABLE_207__MemoryLevel_1_MinVddcPhases_MASK 0xffffffff 2152#define DPM_TABLE_207__MemoryLevel_1_MinVddcPhases__SHIFT 0x0 2153#define DPM_TABLE_208__MemoryLevel_1_MinVddci_MASK 0xffffffff 2154#define DPM_TABLE_208__MemoryLevel_1_MinVddci__SHIFT 0x0 2155#define DPM_TABLE_209__MemoryLevel_1_MinMvdd_MASK 0xffffffff 2156#define DPM_TABLE_209__MemoryLevel_1_MinMvdd__SHIFT 0x0 2157#define DPM_TABLE_210__MemoryLevel_1_MclkFrequency_MASK 0xffffffff 2158#define DPM_TABLE_210__MemoryLevel_1_MclkFrequency__SHIFT 0x0 2159#define DPM_TABLE_211__MemoryLevel_1_StutterEnable_MASK 0xff 2160#define DPM_TABLE_211__MemoryLevel_1_StutterEnable__SHIFT 0x0 2161#define DPM_TABLE_211__MemoryLevel_1_RttEnable_MASK 0xff00 2162#define DPM_TABLE_211__MemoryLevel_1_RttEnable__SHIFT 0x8 2163#define DPM_TABLE_211__MemoryLevel_1_EdcWriteEnable_MASK 0xff0000 2164#define DPM_TABLE_211__MemoryLevel_1_EdcWriteEnable__SHIFT 0x10 2165#define DPM_TABLE_211__MemoryLevel_1_EdcReadEnable_MASK 0xff000000 2166#define DPM_TABLE_211__MemoryLevel_1_EdcReadEnable__SHIFT 0x18 2167#define DPM_TABLE_212__MemoryLevel_1_EnabledForActivity_MASK 0xff 2168#define DPM_TABLE_212__MemoryLevel_1_EnabledForActivity__SHIFT 0x0 2169#define DPM_TABLE_212__MemoryLevel_1_EnabledForThrottle_MASK 0xff00 2170#define DPM_TABLE_212__MemoryLevel_1_EnabledForThrottle__SHIFT 0x8 2171#define DPM_TABLE_212__MemoryLevel_1_StrobeRatio_MASK 0xff0000 2172#define DPM_TABLE_212__MemoryLevel_1_StrobeRatio__SHIFT 0x10 2173#define DPM_TABLE_212__MemoryLevel_1_StrobeEnable_MASK 0xff000000 2174#define DPM_TABLE_212__MemoryLevel_1_StrobeEnable__SHIFT 0x18 2175#define DPM_TABLE_213__MemoryLevel_1_padding_MASK 0xff 2176#define DPM_TABLE_213__MemoryLevel_1_padding__SHIFT 0x0 2177#define DPM_TABLE_213__MemoryLevel_1_VoltageDownHyst_MASK 0xff00 2178#define DPM_TABLE_213__MemoryLevel_1_VoltageDownHyst__SHIFT 0x8 2179#define DPM_TABLE_213__MemoryLevel_1_DownHyst_MASK 0xff0000 2180#define DPM_TABLE_213__MemoryLevel_1_DownHyst__SHIFT 0x10 2181#define DPM_TABLE_213__MemoryLevel_1_UpHyst_MASK 0xff000000 2182#define DPM_TABLE_213__MemoryLevel_1_UpHyst__SHIFT 0x18 2183#define DPM_TABLE_214__MemoryLevel_1_padding1_MASK 0xff 2184#define DPM_TABLE_214__MemoryLevel_1_padding1__SHIFT 0x0 2185#define DPM_TABLE_214__MemoryLevel_1_DisplayWatermark_MASK 0xff00 2186#define DPM_TABLE_214__MemoryLevel_1_DisplayWatermark__SHIFT 0x8 2187#define DPM_TABLE_214__MemoryLevel_1_ActivityLevel_MASK 0xffff0000 2188#define DPM_TABLE_214__MemoryLevel_1_ActivityLevel__SHIFT 0x10 2189#define DPM_TABLE_215__MemoryLevel_1_MpllFuncCntl_MASK 0xffffffff 2190#define DPM_TABLE_215__MemoryLevel_1_MpllFuncCntl__SHIFT 0x0 2191#define DPM_TABLE_216__MemoryLevel_1_MpllFuncCntl_1_MASK 0xffffffff 2192#define DPM_TABLE_216__MemoryLevel_1_MpllFuncCntl_1__SHIFT 0x0 2193#define DPM_TABLE_217__MemoryLevel_1_MpllFuncCntl_2_MASK 0xffffffff 2194#define DPM_TABLE_217__MemoryLevel_1_MpllFuncCntl_2__SHIFT 0x0 2195#define DPM_TABLE_218__MemoryLevel_1_MpllAdFuncCntl_MASK 0xffffffff 2196#define DPM_TABLE_218__MemoryLevel_1_MpllAdFuncCntl__SHIFT 0x0 2197#define DPM_TABLE_219__MemoryLevel_1_MpllDqFuncCntl_MASK 0xffffffff 2198#define DPM_TABLE_219__MemoryLevel_1_MpllDqFuncCntl__SHIFT 0x0 2199#define DPM_TABLE_220__MemoryLevel_1_MclkPwrmgtCntl_MASK 0xffffffff 2200#define DPM_TABLE_220__MemoryLevel_1_MclkPwrmgtCntl__SHIFT 0x0 2201#define DPM_TABLE_221__MemoryLevel_1_DllCntl_MASK 0xffffffff 2202#define DPM_TABLE_221__MemoryLevel_1_DllCntl__SHIFT 0x0 2203#define DPM_TABLE_222__MemoryLevel_1_MpllSs1_MASK 0xffffffff 2204#define DPM_TABLE_222__MemoryLevel_1_MpllSs1__SHIFT 0x0 2205#define DPM_TABLE_223__MemoryLevel_1_MpllSs2_MASK 0xffffffff 2206#define DPM_TABLE_223__MemoryLevel_1_MpllSs2__SHIFT 0x0 2207#define DPM_TABLE_224__MemoryLevel_2_MinVddc_MASK 0xffffffff 2208#define DPM_TABLE_224__MemoryLevel_2_MinVddc__SHIFT 0x0 2209#define DPM_TABLE_225__MemoryLevel_2_MinVddcPhases_MASK 0xffffffff 2210#define DPM_TABLE_225__MemoryLevel_2_MinVddcPhases__SHIFT 0x0 2211#define DPM_TABLE_226__MemoryLevel_2_MinVddci_MASK 0xffffffff 2212#define DPM_TABLE_226__MemoryLevel_2_MinVddci__SHIFT 0x0 2213#define DPM_TABLE_227__MemoryLevel_2_MinMvdd_MASK 0xffffffff 2214#define DPM_TABLE_227__MemoryLevel_2_MinMvdd__SHIFT 0x0 2215#define DPM_TABLE_228__MemoryLevel_2_MclkFrequency_MASK 0xffffffff 2216#define DPM_TABLE_228__MemoryLevel_2_MclkFrequency__SHIFT 0x0 2217#define DPM_TABLE_229__MemoryLevel_2_StutterEnable_MASK 0xff 2218#define DPM_TABLE_229__MemoryLevel_2_StutterEnable__SHIFT 0x0 2219#define DPM_TABLE_229__MemoryLevel_2_RttEnable_MASK 0xff00 2220#define DPM_TABLE_229__MemoryLevel_2_RttEnable__SHIFT 0x8 2221#define DPM_TABLE_229__MemoryLevel_2_EdcWriteEnable_MASK 0xff0000 2222#define DPM_TABLE_229__MemoryLevel_2_EdcWriteEnable__SHIFT 0x10 2223#define DPM_TABLE_229__MemoryLevel_2_EdcReadEnable_MASK 0xff000000 2224#define DPM_TABLE_229__MemoryLevel_2_EdcReadEnable__SHIFT 0x18 2225#define DPM_TABLE_230__MemoryLevel_2_EnabledForActivity_MASK 0xff 2226#define DPM_TABLE_230__MemoryLevel_2_EnabledForActivity__SHIFT 0x0 2227#define DPM_TABLE_230__MemoryLevel_2_EnabledForThrottle_MASK 0xff00 2228#define DPM_TABLE_230__MemoryLevel_2_EnabledForThrottle__SHIFT 0x8 2229#define DPM_TABLE_230__MemoryLevel_2_StrobeRatio_MASK 0xff0000 2230#define DPM_TABLE_230__MemoryLevel_2_StrobeRatio__SHIFT 0x10 2231#define DPM_TABLE_230__MemoryLevel_2_StrobeEnable_MASK 0xff000000 2232#define DPM_TABLE_230__MemoryLevel_2_StrobeEnable__SHIFT 0x18 2233#define DPM_TABLE_231__MemoryLevel_2_padding_MASK 0xff 2234#define DPM_TABLE_231__MemoryLevel_2_padding__SHIFT 0x0 2235#define DPM_TABLE_231__MemoryLevel_2_VoltageDownHyst_MASK 0xff00 2236#define DPM_TABLE_231__MemoryLevel_2_VoltageDownHyst__SHIFT 0x8 2237#define DPM_TABLE_231__MemoryLevel_2_DownHyst_MASK 0xff0000 2238#define DPM_TABLE_231__MemoryLevel_2_DownHyst__SHIFT 0x10 2239#define DPM_TABLE_231__MemoryLevel_2_UpHyst_MASK 0xff000000 2240#define DPM_TABLE_231__MemoryLevel_2_UpHyst__SHIFT 0x18 2241#define DPM_TABLE_232__MemoryLevel_2_padding1_MASK 0xff 2242#define DPM_TABLE_232__MemoryLevel_2_padding1__SHIFT 0x0 2243#define DPM_TABLE_232__MemoryLevel_2_DisplayWatermark_MASK 0xff00 2244#define DPM_TABLE_232__MemoryLevel_2_DisplayWatermark__SHIFT 0x8 2245#define DPM_TABLE_232__MemoryLevel_2_ActivityLevel_MASK 0xffff0000 2246#define DPM_TABLE_232__MemoryLevel_2_ActivityLevel__SHIFT 0x10 2247#define DPM_TABLE_233__MemoryLevel_2_MpllFuncCntl_MASK 0xffffffff 2248#define DPM_TABLE_233__MemoryLevel_2_MpllFuncCntl__SHIFT 0x0 2249#define DPM_TABLE_234__MemoryLevel_2_MpllFuncCntl_1_MASK 0xffffffff 2250#define DPM_TABLE_234__MemoryLevel_2_MpllFuncCntl_1__SHIFT 0x0 2251#define DPM_TABLE_235__MemoryLevel_2_MpllFuncCntl_2_MASK 0xffffffff 2252#define DPM_TABLE_235__MemoryLevel_2_MpllFuncCntl_2__SHIFT 0x0 2253#define DPM_TABLE_236__MemoryLevel_2_MpllAdFuncCntl_MASK 0xffffffff 2254#define DPM_TABLE_236__MemoryLevel_2_MpllAdFuncCntl__SHIFT 0x0 2255#define DPM_TABLE_237__MemoryLevel_2_MpllDqFuncCntl_MASK 0xffffffff 2256#define DPM_TABLE_237__MemoryLevel_2_MpllDqFuncCntl__SHIFT 0x0 2257#define DPM_TABLE_238__MemoryLevel_2_MclkPwrmgtCntl_MASK 0xffffffff 2258#define DPM_TABLE_238__MemoryLevel_2_MclkPwrmgtCntl__SHIFT 0x0 2259#define DPM_TABLE_239__MemoryLevel_2_DllCntl_MASK 0xffffffff 2260#define DPM_TABLE_239__MemoryLevel_2_DllCntl__SHIFT 0x0 2261#define DPM_TABLE_240__MemoryLevel_2_MpllSs1_MASK 0xffffffff 2262#define DPM_TABLE_240__MemoryLevel_2_MpllSs1__SHIFT 0x0 2263#define DPM_TABLE_241__MemoryLevel_2_MpllSs2_MASK 0xffffffff 2264#define DPM_TABLE_241__MemoryLevel_2_MpllSs2__SHIFT 0x0 2265#define DPM_TABLE_242__MemoryLevel_3_MinVddc_MASK 0xffffffff 2266#define DPM_TABLE_242__MemoryLevel_3_MinVddc__SHIFT 0x0 2267#define DPM_TABLE_243__MemoryLevel_3_MinVddcPhases_MASK 0xffffffff 2268#define DPM_TABLE_243__MemoryLevel_3_MinVddcPhases__SHIFT 0x0 2269#define DPM_TABLE_244__MemoryLevel_3_MinVddci_MASK 0xffffffff 2270#define DPM_TABLE_244__MemoryLevel_3_MinVddci__SHIFT 0x0 2271#define DPM_TABLE_245__MemoryLevel_3_MinMvdd_MASK 0xffffffff 2272#define DPM_TABLE_245__MemoryLevel_3_MinMvdd__SHIFT 0x0 2273#define DPM_TABLE_246__MemoryLevel_3_MclkFrequency_MASK 0xffffffff 2274#define DPM_TABLE_246__MemoryLevel_3_MclkFrequency__SHIFT 0x0 2275#define DPM_TABLE_247__MemoryLevel_3_StutterEnable_MASK 0xff 2276#define DPM_TABLE_247__MemoryLevel_3_StutterEnable__SHIFT 0x0 2277#define DPM_TABLE_247__MemoryLevel_3_RttEnable_MASK 0xff00 2278#define DPM_TABLE_247__MemoryLevel_3_RttEnable__SHIFT 0x8 2279#define DPM_TABLE_247__MemoryLevel_3_EdcWriteEnable_MASK 0xff0000 2280#define DPM_TABLE_247__MemoryLevel_3_EdcWriteEnable__SHIFT 0x10 2281#define DPM_TABLE_247__MemoryLevel_3_EdcReadEnable_MASK 0xff000000 2282#define DPM_TABLE_247__MemoryLevel_3_EdcReadEnable__SHIFT 0x18 2283#define DPM_TABLE_248__MemoryLevel_3_EnabledForActivity_MASK 0xff 2284#define DPM_TABLE_248__MemoryLevel_3_EnabledForActivity__SHIFT 0x0 2285#define DPM_TABLE_248__MemoryLevel_3_EnabledForThrottle_MASK 0xff00 2286#define DPM_TABLE_248__MemoryLevel_3_EnabledForThrottle__SHIFT 0x8 2287#define DPM_TABLE_248__MemoryLevel_3_StrobeRatio_MASK 0xff0000 2288#define DPM_TABLE_248__MemoryLevel_3_StrobeRatio__SHIFT 0x10 2289#define DPM_TABLE_248__MemoryLevel_3_StrobeEnable_MASK 0xff000000 2290#define DPM_TABLE_248__MemoryLevel_3_StrobeEnable__SHIFT 0x18 2291#define DPM_TABLE_249__MemoryLevel_3_padding_MASK 0xff 2292#define DPM_TABLE_249__MemoryLevel_3_padding__SHIFT 0x0 2293#define DPM_TABLE_249__MemoryLevel_3_VoltageDownHyst_MASK 0xff00 2294#define DPM_TABLE_249__MemoryLevel_3_VoltageDownHyst__SHIFT 0x8 2295#define DPM_TABLE_249__MemoryLevel_3_DownHyst_MASK 0xff0000 2296#define DPM_TABLE_249__MemoryLevel_3_DownHyst__SHIFT 0x10 2297#define DPM_TABLE_249__MemoryLevel_3_UpHyst_MASK 0xff000000 2298#define DPM_TABLE_249__MemoryLevel_3_UpHyst__SHIFT 0x18 2299#define DPM_TABLE_250__MemoryLevel_3_padding1_MASK 0xff 2300#define DPM_TABLE_250__MemoryLevel_3_padding1__SHIFT 0x0 2301#define DPM_TABLE_250__MemoryLevel_3_DisplayWatermark_MASK 0xff00 2302#define DPM_TABLE_250__MemoryLevel_3_DisplayWatermark__SHIFT 0x8 2303#define DPM_TABLE_250__MemoryLevel_3_ActivityLevel_MASK 0xffff0000 2304#define DPM_TABLE_250__MemoryLevel_3_ActivityLevel__SHIFT 0x10 2305#define DPM_TABLE_251__MemoryLevel_3_MpllFuncCntl_MASK 0xffffffff 2306#define DPM_TABLE_251__MemoryLevel_3_MpllFuncCntl__SHIFT 0x0 2307#define DPM_TABLE_252__MemoryLevel_3_MpllFuncCntl_1_MASK 0xffffffff 2308#define DPM_TABLE_252__MemoryLevel_3_MpllFuncCntl_1__SHIFT 0x0 2309#define DPM_TABLE_253__MemoryLevel_3_MpllFuncCntl_2_MASK 0xffffffff 2310#define DPM_TABLE_253__MemoryLevel_3_MpllFuncCntl_2__SHIFT 0x0 2311#define DPM_TABLE_254__MemoryLevel_3_MpllAdFuncCntl_MASK 0xffffffff 2312#define DPM_TABLE_254__MemoryLevel_3_MpllAdFuncCntl__SHIFT 0x0 2313#define DPM_TABLE_255__MemoryLevel_3_MpllDqFuncCntl_MASK 0xffffffff 2314#define DPM_TABLE_255__MemoryLevel_3_MpllDqFuncCntl__SHIFT 0x0 2315#define DPM_TABLE_256__MemoryLevel_3_MclkPwrmgtCntl_MASK 0xffffffff 2316#define DPM_TABLE_256__MemoryLevel_3_MclkPwrmgtCntl__SHIFT 0x0 2317#define DPM_TABLE_257__MemoryLevel_3_DllCntl_MASK 0xffffffff 2318#define DPM_TABLE_257__MemoryLevel_3_DllCntl__SHIFT 0x0 2319#define DPM_TABLE_258__MemoryLevel_3_MpllSs1_MASK 0xffffffff 2320#define DPM_TABLE_258__MemoryLevel_3_MpllSs1__SHIFT 0x0 2321#define DPM_TABLE_259__MemoryLevel_3_MpllSs2_MASK 0xffffffff 2322#define DPM_TABLE_259__MemoryLevel_3_MpllSs2__SHIFT 0x0 2323#define DPM_TABLE_260__LinkLevel_0_SPC_MASK 0xff 2324#define DPM_TABLE_260__LinkLevel_0_SPC__SHIFT 0x0 2325#define DPM_TABLE_260__LinkLevel_0_EnabledForActivity_MASK 0xff00 2326#define DPM_TABLE_260__LinkLevel_0_EnabledForActivity__SHIFT 0x8 2327#define DPM_TABLE_260__LinkLevel_0_PcieLaneCount_MASK 0xff0000 2328#define DPM_TABLE_260__LinkLevel_0_PcieLaneCount__SHIFT 0x10 2329#define DPM_TABLE_260__LinkLevel_0_PcieGenSpeed_MASK 0xff000000 2330#define DPM_TABLE_260__LinkLevel_0_PcieGenSpeed__SHIFT 0x18 2331#define DPM_TABLE_261__LinkLevel_0_DownThreshold_MASK 0xffffffff 2332#define DPM_TABLE_261__LinkLevel_0_DownThreshold__SHIFT 0x0 2333#define DPM_TABLE_262__LinkLevel_0_UpThreshold_MASK 0xffffffff 2334#define DPM_TABLE_262__LinkLevel_0_UpThreshold__SHIFT 0x0 2335#define DPM_TABLE_263__LinkLevel_0_Reserved_MASK 0xffffffff 2336#define DPM_TABLE_263__LinkLevel_0_Reserved__SHIFT 0x0 2337#define DPM_TABLE_264__LinkLevel_1_SPC_MASK 0xff 2338#define DPM_TABLE_264__LinkLevel_1_SPC__SHIFT 0x0 2339#define DPM_TABLE_264__LinkLevel_1_EnabledForActivity_MASK 0xff00 2340#define DPM_TABLE_264__LinkLevel_1_EnabledForActivity__SHIFT 0x8 2341#define DPM_TABLE_264__LinkLevel_1_PcieLaneCount_MASK 0xff0000 2342#define DPM_TABLE_264__LinkLevel_1_PcieLaneCount__SHIFT 0x10 2343#define DPM_TABLE_264__LinkLevel_1_PcieGenSpeed_MASK 0xff000000 2344#define DPM_TABLE_264__LinkLevel_1_PcieGenSpeed__SHIFT 0x18 2345#define DPM_TABLE_265__LinkLevel_1_DownThreshold_MASK 0xffffffff 2346#define DPM_TABLE_265__LinkLevel_1_DownThreshold__SHIFT 0x0 2347#define DPM_TABLE_266__LinkLevel_1_UpThreshold_MASK 0xffffffff 2348#define DPM_TABLE_266__LinkLevel_1_UpThreshold__SHIFT 0x0 2349#define DPM_TABLE_267__LinkLevel_1_Reserved_MASK 0xffffffff 2350#define DPM_TABLE_267__LinkLevel_1_Reserved__SHIFT 0x0 2351#define DPM_TABLE_268__LinkLevel_2_SPC_MASK 0xff 2352#define DPM_TABLE_268__LinkLevel_2_SPC__SHIFT 0x0 2353#define DPM_TABLE_268__LinkLevel_2_EnabledForActivity_MASK 0xff00 2354#define DPM_TABLE_268__LinkLevel_2_EnabledForActivity__SHIFT 0x8 2355#define DPM_TABLE_268__LinkLevel_2_PcieLaneCount_MASK 0xff0000 2356#define DPM_TABLE_268__LinkLevel_2_PcieLaneCount__SHIFT 0x10 2357#define DPM_TABLE_268__LinkLevel_2_PcieGenSpeed_MASK 0xff000000 2358#define DPM_TABLE_268__LinkLevel_2_PcieGenSpeed__SHIFT 0x18 2359#define DPM_TABLE_269__LinkLevel_2_DownThreshold_MASK 0xffffffff 2360#define DPM_TABLE_269__LinkLevel_2_DownThreshold__SHIFT 0x0 2361#define DPM_TABLE_270__LinkLevel_2_UpThreshold_MASK 0xffffffff 2362#define DPM_TABLE_270__LinkLevel_2_UpThreshold__SHIFT 0x0 2363#define DPM_TABLE_271__LinkLevel_2_Reserved_MASK 0xffffffff 2364#define DPM_TABLE_271__LinkLevel_2_Reserved__SHIFT 0x0 2365#define DPM_TABLE_272__LinkLevel_3_SPC_MASK 0xff 2366#define DPM_TABLE_272__LinkLevel_3_SPC__SHIFT 0x0 2367#define DPM_TABLE_272__LinkLevel_3_EnabledForActivity_MASK 0xff00 2368#define DPM_TABLE_272__LinkLevel_3_EnabledForActivity__SHIFT 0x8 2369#define DPM_TABLE_272__LinkLevel_3_PcieLaneCount_MASK 0xff0000 2370#define DPM_TABLE_272__LinkLevel_3_PcieLaneCount__SHIFT 0x10 2371#define DPM_TABLE_272__LinkLevel_3_PcieGenSpeed_MASK 0xff000000 2372#define DPM_TABLE_272__LinkLevel_3_PcieGenSpeed__SHIFT 0x18 2373#define DPM_TABLE_273__LinkLevel_3_DownThreshold_MASK 0xffffffff 2374#define DPM_TABLE_273__LinkLevel_3_DownThreshold__SHIFT 0x0 2375#define DPM_TABLE_274__LinkLevel_3_UpThreshold_MASK 0xffffffff 2376#define DPM_TABLE_274__LinkLevel_3_UpThreshold__SHIFT 0x0 2377#define DPM_TABLE_275__LinkLevel_3_Reserved_MASK 0xffffffff 2378#define DPM_TABLE_275__LinkLevel_3_Reserved__SHIFT 0x0 2379#define DPM_TABLE_276__LinkLevel_4_SPC_MASK 0xff 2380#define DPM_TABLE_276__LinkLevel_4_SPC__SHIFT 0x0 2381#define DPM_TABLE_276__LinkLevel_4_EnabledForActivity_MASK 0xff00 2382#define DPM_TABLE_276__LinkLevel_4_EnabledForActivity__SHIFT 0x8 2383#define DPM_TABLE_276__LinkLevel_4_PcieLaneCount_MASK 0xff0000 2384#define DPM_TABLE_276__LinkLevel_4_PcieLaneCount__SHIFT 0x10 2385#define DPM_TABLE_276__LinkLevel_4_PcieGenSpeed_MASK 0xff000000 2386#define DPM_TABLE_276__LinkLevel_4_PcieGenSpeed__SHIFT 0x18 2387#define DPM_TABLE_277__LinkLevel_4_DownThreshold_MASK 0xffffffff 2388#define DPM_TABLE_277__LinkLevel_4_DownThreshold__SHIFT 0x0 2389#define DPM_TABLE_278__LinkLevel_4_UpThreshold_MASK 0xffffffff 2390#define DPM_TABLE_278__LinkLevel_4_UpThreshold__SHIFT 0x0 2391#define DPM_TABLE_279__LinkLevel_4_Reserved_MASK 0xffffffff 2392#define DPM_TABLE_279__LinkLevel_4_Reserved__SHIFT 0x0 2393#define DPM_TABLE_280__LinkLevel_5_SPC_MASK 0xff 2394#define DPM_TABLE_280__LinkLevel_5_SPC__SHIFT 0x0 2395#define DPM_TABLE_280__LinkLevel_5_EnabledForActivity_MASK 0xff00 2396#define DPM_TABLE_280__LinkLevel_5_EnabledForActivity__SHIFT 0x8 2397#define DPM_TABLE_280__LinkLevel_5_PcieLaneCount_MASK 0xff0000 2398#define DPM_TABLE_280__LinkLevel_5_PcieLaneCount__SHIFT 0x10 2399#define DPM_TABLE_280__LinkLevel_5_PcieGenSpeed_MASK 0xff000000 2400#define DPM_TABLE_280__LinkLevel_5_PcieGenSpeed__SHIFT 0x18 2401#define DPM_TABLE_281__LinkLevel_5_DownThreshold_MASK 0xffffffff 2402#define DPM_TABLE_281__LinkLevel_5_DownThreshold__SHIFT 0x0 2403#define DPM_TABLE_282__LinkLevel_5_UpThreshold_MASK 0xffffffff 2404#define DPM_TABLE_282__LinkLevel_5_UpThreshold__SHIFT 0x0 2405#define DPM_TABLE_283__LinkLevel_5_Reserved_MASK 0xffffffff 2406#define DPM_TABLE_283__LinkLevel_5_Reserved__SHIFT 0x0 2407#define DPM_TABLE_284__LinkLevel_6_SPC_MASK 0xff 2408#define DPM_TABLE_284__LinkLevel_6_SPC__SHIFT 0x0 2409#define DPM_TABLE_284__LinkLevel_6_EnabledForActivity_MASK 0xff00 2410#define DPM_TABLE_284__LinkLevel_6_EnabledForActivity__SHIFT 0x8 2411#define DPM_TABLE_284__LinkLevel_6_PcieLaneCount_MASK 0xff0000 2412#define DPM_TABLE_284__LinkLevel_6_PcieLaneCount__SHIFT 0x10 2413#define DPM_TABLE_284__LinkLevel_6_PcieGenSpeed_MASK 0xff000000 2414#define DPM_TABLE_284__LinkLevel_6_PcieGenSpeed__SHIFT 0x18 2415#define DPM_TABLE_285__LinkLevel_6_DownThreshold_MASK 0xffffffff 2416#define DPM_TABLE_285__LinkLevel_6_DownThreshold__SHIFT 0x0 2417#define DPM_TABLE_286__LinkLevel_6_UpThreshold_MASK 0xffffffff 2418#define DPM_TABLE_286__LinkLevel_6_UpThreshold__SHIFT 0x0 2419#define DPM_TABLE_287__LinkLevel_6_Reserved_MASK 0xffffffff 2420#define DPM_TABLE_287__LinkLevel_6_Reserved__SHIFT 0x0 2421#define DPM_TABLE_288__LinkLevel_7_SPC_MASK 0xff 2422#define DPM_TABLE_288__LinkLevel_7_SPC__SHIFT 0x0 2423#define DPM_TABLE_288__LinkLevel_7_EnabledForActivity_MASK 0xff00 2424#define DPM_TABLE_288__LinkLevel_7_EnabledForActivity__SHIFT 0x8 2425#define DPM_TABLE_288__LinkLevel_7_PcieLaneCount_MASK 0xff0000 2426#define DPM_TABLE_288__LinkLevel_7_PcieLaneCount__SHIFT 0x10 2427#define DPM_TABLE_288__LinkLevel_7_PcieGenSpeed_MASK 0xff000000 2428#define DPM_TABLE_288__LinkLevel_7_PcieGenSpeed__SHIFT 0x18 2429#define DPM_TABLE_289__LinkLevel_7_DownThreshold_MASK 0xffffffff 2430#define DPM_TABLE_289__LinkLevel_7_DownThreshold__SHIFT 0x0 2431#define DPM_TABLE_290__LinkLevel_7_UpThreshold_MASK 0xffffffff 2432#define DPM_TABLE_290__LinkLevel_7_UpThreshold__SHIFT 0x0 2433#define DPM_TABLE_291__LinkLevel_7_Reserved_MASK 0xffffffff 2434#define DPM_TABLE_291__LinkLevel_7_Reserved__SHIFT 0x0 2435#define DPM_TABLE_292__ACPILevel_Flags_MASK 0xffffffff 2436#define DPM_TABLE_292__ACPILevel_Flags__SHIFT 0x0 2437#define DPM_TABLE_293__ACPILevel_MinVddc_MASK 0xffffffff 2438#define DPM_TABLE_293__ACPILevel_MinVddc__SHIFT 0x0 2439#define DPM_TABLE_294__ACPILevel_MinVddcPhases_MASK 0xffffffff 2440#define DPM_TABLE_294__ACPILevel_MinVddcPhases__SHIFT 0x0 2441#define DPM_TABLE_295__ACPILevel_SclkFrequency_MASK 0xffffffff 2442#define DPM_TABLE_295__ACPILevel_SclkFrequency__SHIFT 0x0 2443#define DPM_TABLE_296__ACPILevel_padding_MASK 0xff 2444#define DPM_TABLE_296__ACPILevel_padding__SHIFT 0x0 2445#define DPM_TABLE_296__ACPILevel_DeepSleepDivId_MASK 0xff00 2446#define DPM_TABLE_296__ACPILevel_DeepSleepDivId__SHIFT 0x8 2447#define DPM_TABLE_296__ACPILevel_DisplayWatermark_MASK 0xff0000 2448#define DPM_TABLE_296__ACPILevel_DisplayWatermark__SHIFT 0x10 2449#define DPM_TABLE_296__ACPILevel_SclkDid_MASK 0xff000000 2450#define DPM_TABLE_296__ACPILevel_SclkDid__SHIFT 0x18 2451#define DPM_TABLE_297__ACPILevel_CgSpllFuncCntl_MASK 0xffffffff 2452#define DPM_TABLE_297__ACPILevel_CgSpllFuncCntl__SHIFT 0x0 2453#define DPM_TABLE_298__ACPILevel_CgSpllFuncCntl2_MASK 0xffffffff 2454#define DPM_TABLE_298__ACPILevel_CgSpllFuncCntl2__SHIFT 0x0 2455#define DPM_TABLE_299__ACPILevel_CgSpllFuncCntl3_MASK 0xffffffff 2456#define DPM_TABLE_299__ACPILevel_CgSpllFuncCntl3__SHIFT 0x0 2457#define DPM_TABLE_300__ACPILevel_CgSpllFuncCntl4_MASK 0xffffffff 2458#define DPM_TABLE_300__ACPILevel_CgSpllFuncCntl4__SHIFT 0x0 2459#define DPM_TABLE_301__ACPILevel_SpllSpreadSpectrum_MASK 0xffffffff 2460#define DPM_TABLE_301__ACPILevel_SpllSpreadSpectrum__SHIFT 0x0 2461#define DPM_TABLE_302__ACPILevel_SpllSpreadSpectrum2_MASK 0xffffffff 2462#define DPM_TABLE_302__ACPILevel_SpllSpreadSpectrum2__SHIFT 0x0 2463#define DPM_TABLE_303__ACPILevel_CcPwrDynRm_MASK 0xffffffff 2464#define DPM_TABLE_303__ACPILevel_CcPwrDynRm__SHIFT 0x0 2465#define DPM_TABLE_304__ACPILevel_CcPwrDynRm1_MASK 0xffffffff 2466#define DPM_TABLE_304__ACPILevel_CcPwrDynRm1__SHIFT 0x0 2467#define DPM_TABLE_305__SclkStepSize_MASK 0xffffffff 2468#define DPM_TABLE_305__SclkStepSize__SHIFT 0x0 2469#define DPM_TABLE_306__Smio_0_MASK 0xffffffff 2470#define DPM_TABLE_306__Smio_0__SHIFT 0x0 2471#define DPM_TABLE_307__Smio_1_MASK 0xffffffff 2472#define DPM_TABLE_307__Smio_1__SHIFT 0x0 2473#define DPM_TABLE_308__Smio_2_MASK 0xffffffff 2474#define DPM_TABLE_308__Smio_2__SHIFT 0x0 2475#define DPM_TABLE_309__Smio_3_MASK 0xffffffff 2476#define DPM_TABLE_309__Smio_3__SHIFT 0x0 2477#define DPM_TABLE_310__Smio_4_MASK 0xffffffff 2478#define DPM_TABLE_310__Smio_4__SHIFT 0x0 2479#define DPM_TABLE_311__Smio_5_MASK 0xffffffff 2480#define DPM_TABLE_311__Smio_5__SHIFT 0x0 2481#define DPM_TABLE_312__Smio_6_MASK 0xffffffff 2482#define DPM_TABLE_312__Smio_6__SHIFT 0x0 2483#define DPM_TABLE_313__Smio_7_MASK 0xffffffff 2484#define DPM_TABLE_313__Smio_7__SHIFT 0x0 2485#define DPM_TABLE_314__Smio_8_MASK 0xffffffff 2486#define DPM_TABLE_314__Smio_8__SHIFT 0x0 2487#define DPM_TABLE_315__Smio_9_MASK 0xffffffff 2488#define DPM_TABLE_315__Smio_9__SHIFT 0x0 2489#define DPM_TABLE_316__Smio_10_MASK 0xffffffff 2490#define DPM_TABLE_316__Smio_10__SHIFT 0x0 2491#define DPM_TABLE_317__Smio_11_MASK 0xffffffff 2492#define DPM_TABLE_317__Smio_11__SHIFT 0x0 2493#define DPM_TABLE_318__Smio_12_MASK 0xffffffff 2494#define DPM_TABLE_318__Smio_12__SHIFT 0x0 2495#define DPM_TABLE_319__Smio_13_MASK 0xffffffff 2496#define DPM_TABLE_319__Smio_13__SHIFT 0x0 2497#define DPM_TABLE_320__Smio_14_MASK 0xffffffff 2498#define DPM_TABLE_320__Smio_14__SHIFT 0x0 2499#define DPM_TABLE_321__Smio_15_MASK 0xffffffff 2500#define DPM_TABLE_321__Smio_15__SHIFT 0x0 2501#define DPM_TABLE_322__Smio_16_MASK 0xffffffff 2502#define DPM_TABLE_322__Smio_16__SHIFT 0x0 2503#define DPM_TABLE_323__Smio_17_MASK 0xffffffff 2504#define DPM_TABLE_323__Smio_17__SHIFT 0x0 2505#define DPM_TABLE_324__Smio_18_MASK 0xffffffff 2506#define DPM_TABLE_324__Smio_18__SHIFT 0x0 2507#define DPM_TABLE_325__Smio_19_MASK 0xffffffff 2508#define DPM_TABLE_325__Smio_19__SHIFT 0x0 2509#define DPM_TABLE_326__Smio_20_MASK 0xffffffff 2510#define DPM_TABLE_326__Smio_20__SHIFT 0x0 2511#define DPM_TABLE_327__Smio_21_MASK 0xffffffff 2512#define DPM_TABLE_327__Smio_21__SHIFT 0x0 2513#define DPM_TABLE_328__Smio_22_MASK 0xffffffff 2514#define DPM_TABLE_328__Smio_22__SHIFT 0x0 2515#define DPM_TABLE_329__Smio_23_MASK 0xffffffff 2516#define DPM_TABLE_329__Smio_23__SHIFT 0x0 2517#define DPM_TABLE_330__Smio_24_MASK 0xffffffff 2518#define DPM_TABLE_330__Smio_24__SHIFT 0x0 2519#define DPM_TABLE_331__Smio_25_MASK 0xffffffff 2520#define DPM_TABLE_331__Smio_25__SHIFT 0x0 2521#define DPM_TABLE_332__Smio_26_MASK 0xffffffff 2522#define DPM_TABLE_332__Smio_26__SHIFT 0x0 2523#define DPM_TABLE_333__Smio_27_MASK 0xffffffff 2524#define DPM_TABLE_333__Smio_27__SHIFT 0x0 2525#define DPM_TABLE_334__Smio_28_MASK 0xffffffff 2526#define DPM_TABLE_334__Smio_28__SHIFT 0x0 2527#define DPM_TABLE_335__Smio_29_MASK 0xffffffff 2528#define DPM_TABLE_335__Smio_29__SHIFT 0x0 2529#define DPM_TABLE_336__Smio_30_MASK 0xffffffff 2530#define DPM_TABLE_336__Smio_30__SHIFT 0x0 2531#define DPM_TABLE_337__Smio_31_MASK 0xffffffff 2532#define DPM_TABLE_337__Smio_31__SHIFT 0x0 2533#define DPM_TABLE_338__GraphicsInterval_MASK 0xff 2534#define DPM_TABLE_338__GraphicsInterval__SHIFT 0x0 2535#define DPM_TABLE_338__GraphicsThermThrottleEnable_MASK 0xff00 2536#define DPM_TABLE_338__GraphicsThermThrottleEnable__SHIFT 0x8 2537#define DPM_TABLE_338__GraphicsVoltageChangeEnable_MASK 0xff0000 2538#define DPM_TABLE_338__GraphicsVoltageChangeEnable__SHIFT 0x10 2539#define DPM_TABLE_338__GraphicsBootLevel_MASK 0xff000000 2540#define DPM_TABLE_338__GraphicsBootLevel__SHIFT 0x18 2541#define DPM_TABLE_339__TemperatureLimitHigh_MASK 0xffff 2542#define DPM_TABLE_339__TemperatureLimitHigh__SHIFT 0x0 2543#define DPM_TABLE_339__ThermalInterval_MASK 0xff0000 2544#define DPM_TABLE_339__ThermalInterval__SHIFT 0x10 2545#define DPM_TABLE_339__VoltageInterval_MASK 0xff000000 2546#define DPM_TABLE_339__VoltageInterval__SHIFT 0x18 2547#define DPM_TABLE_340__MemoryVoltageChangeEnable_MASK 0xff 2548#define DPM_TABLE_340__MemoryVoltageChangeEnable__SHIFT 0x0 2549#define DPM_TABLE_340__MemoryBootLevel_MASK 0xff00 2550#define DPM_TABLE_340__MemoryBootLevel__SHIFT 0x8 2551#define DPM_TABLE_340__TemperatureLimitLow_MASK 0xffff0000 2552#define DPM_TABLE_340__TemperatureLimitLow__SHIFT 0x10 2553#define DPM_TABLE_341__padding2_MASK 0xff 2554#define DPM_TABLE_341__padding2__SHIFT 0x0 2555#define DPM_TABLE_341__MergedVddci_MASK 0xff00 2556#define DPM_TABLE_341__MergedVddci__SHIFT 0x8 2557#define DPM_TABLE_341__MemoryThermThrottleEnable_MASK 0xff0000 2558#define DPM_TABLE_341__MemoryThermThrottleEnable__SHIFT 0x10 2559#define DPM_TABLE_341__MemoryInterval_MASK 0xff000000 2560#define DPM_TABLE_341__MemoryInterval__SHIFT 0x18 2561#define DPM_TABLE_342__PhaseResponseTime_MASK 0xffff 2562#define DPM_TABLE_342__PhaseResponseTime__SHIFT 0x0 2563#define DPM_TABLE_342__VoltageResponseTime_MASK 0xffff0000 2564#define DPM_TABLE_342__VoltageResponseTime__SHIFT 0x10 2565#define DPM_TABLE_343__DTEMode_MASK 0xff 2566#define DPM_TABLE_343__DTEMode__SHIFT 0x0 2567#define DPM_TABLE_343__DTEInterval_MASK 0xff00 2568#define DPM_TABLE_343__DTEInterval__SHIFT 0x8 2569#define DPM_TABLE_343__PCIeGenInterval_MASK 0xff0000 2570#define DPM_TABLE_343__PCIeGenInterval__SHIFT 0x10 2571#define DPM_TABLE_343__PCIeBootLinkLevel_MASK 0xff000000 2572#define DPM_TABLE_343__PCIeBootLinkLevel__SHIFT 0x18 2573#define DPM_TABLE_344__ThermGpio_MASK 0xff 2574#define DPM_TABLE_344__ThermGpio__SHIFT 0x0 2575#define DPM_TABLE_344__AcDcGpio_MASK 0xff00 2576#define DPM_TABLE_344__AcDcGpio__SHIFT 0x8 2577#define DPM_TABLE_344__VRHotGpio_MASK 0xff0000 2578#define DPM_TABLE_344__VRHotGpio__SHIFT 0x10 2579#define DPM_TABLE_344__SVI2Enable_MASK 0xff000000 2580#define DPM_TABLE_344__SVI2Enable__SHIFT 0x18 2581#define DPM_TABLE_345__DisplayCac_MASK 0xffffffff 2582#define DPM_TABLE_345__DisplayCac__SHIFT 0x0 2583#define DPM_TABLE_346__NomPwr_MASK 0xffff 2584#define DPM_TABLE_346__NomPwr__SHIFT 0x0 2585#define DPM_TABLE_346__MaxPwr_MASK 0xffff0000 2586#define DPM_TABLE_346__MaxPwr__SHIFT 0x10 2587#define DPM_TABLE_347__FpsLowThreshold_MASK 0xffff 2588#define DPM_TABLE_347__FpsLowThreshold__SHIFT 0x0 2589#define DPM_TABLE_347__FpsHighThreshold_MASK 0xffff0000 2590#define DPM_TABLE_347__FpsHighThreshold__SHIFT 0x10 2591#define DPM_TABLE_348__BAPMTI_R_0_1_0_MASK 0xffff 2592#define DPM_TABLE_348__BAPMTI_R_0_1_0__SHIFT 0x0 2593#define DPM_TABLE_348__BAPMTI_R_0_0_0_MASK 0xffff0000 2594#define DPM_TABLE_348__BAPMTI_R_0_0_0__SHIFT 0x10 2595#define DPM_TABLE_349__BAPMTI_R_1_0_0_MASK 0xffff 2596#define DPM_TABLE_349__BAPMTI_R_1_0_0__SHIFT 0x0 2597#define DPM_TABLE_349__BAPMTI_R_0_2_0_MASK 0xffff0000 2598#define DPM_TABLE_349__BAPMTI_R_0_2_0__SHIFT 0x10 2599#define DPM_TABLE_350__BAPMTI_R_1_2_0_MASK 0xffff 2600#define DPM_TABLE_350__BAPMTI_R_1_2_0__SHIFT 0x0 2601#define DPM_TABLE_350__BAPMTI_R_1_1_0_MASK 0xffff0000 2602#define DPM_TABLE_350__BAPMTI_R_1_1_0__SHIFT 0x10 2603#define DPM_TABLE_351__BAPMTI_R_2_1_0_MASK 0xffff 2604#define DPM_TABLE_351__BAPMTI_R_2_1_0__SHIFT 0x0 2605#define DPM_TABLE_351__BAPMTI_R_2_0_0_MASK 0xffff0000 2606#define DPM_TABLE_351__BAPMTI_R_2_0_0__SHIFT 0x10 2607#define DPM_TABLE_352__BAPMTI_R_3_0_0_MASK 0xffff 2608#define DPM_TABLE_352__BAPMTI_R_3_0_0__SHIFT 0x0 2609#define DPM_TABLE_352__BAPMTI_R_2_2_0_MASK 0xffff0000 2610#define DPM_TABLE_352__BAPMTI_R_2_2_0__SHIFT 0x10 2611#define DPM_TABLE_353__BAPMTI_R_3_2_0_MASK 0xffff 2612#define DPM_TABLE_353__BAPMTI_R_3_2_0__SHIFT 0x0 2613#define DPM_TABLE_353__BAPMTI_R_3_1_0_MASK 0xffff0000 2614#define DPM_TABLE_353__BAPMTI_R_3_1_0__SHIFT 0x10 2615#define DPM_TABLE_354__BAPMTI_R_4_1_0_MASK 0xffff 2616#define DPM_TABLE_354__BAPMTI_R_4_1_0__SHIFT 0x0 2617#define DPM_TABLE_354__BAPMTI_R_4_0_0_MASK 0xffff0000 2618#define DPM_TABLE_354__BAPMTI_R_4_0_0__SHIFT 0x10 2619#define DPM_TABLE_355__BAPMTI_RC_0_0_0_MASK 0xffff 2620#define DPM_TABLE_355__BAPMTI_RC_0_0_0__SHIFT 0x0 2621#define DPM_TABLE_355__BAPMTI_R_4_2_0_MASK 0xffff0000 2622#define DPM_TABLE_355__BAPMTI_R_4_2_0__SHIFT 0x10 2623#define DPM_TABLE_356__BAPMTI_RC_0_2_0_MASK 0xffff 2624#define DPM_TABLE_356__BAPMTI_RC_0_2_0__SHIFT 0x0 2625#define DPM_TABLE_356__BAPMTI_RC_0_1_0_MASK 0xffff0000 2626#define DPM_TABLE_356__BAPMTI_RC_0_1_0__SHIFT 0x10 2627#define DPM_TABLE_357__BAPMTI_RC_1_1_0_MASK 0xffff 2628#define DPM_TABLE_357__BAPMTI_RC_1_1_0__SHIFT 0x0 2629#define DPM_TABLE_357__BAPMTI_RC_1_0_0_MASK 0xffff0000 2630#define DPM_TABLE_357__BAPMTI_RC_1_0_0__SHIFT 0x10 2631#define DPM_TABLE_358__BAPMTI_RC_2_0_0_MASK 0xffff 2632#define DPM_TABLE_358__BAPMTI_RC_2_0_0__SHIFT 0x0 2633#define DPM_TABLE_358__BAPMTI_RC_1_2_0_MASK 0xffff0000 2634#define DPM_TABLE_358__BAPMTI_RC_1_2_0__SHIFT 0x10 2635#define DPM_TABLE_359__BAPMTI_RC_2_2_0_MASK 0xffff 2636#define DPM_TABLE_359__BAPMTI_RC_2_2_0__SHIFT 0x0 2637#define DPM_TABLE_359__BAPMTI_RC_2_1_0_MASK 0xffff0000 2638#define DPM_TABLE_359__BAPMTI_RC_2_1_0__SHIFT 0x10 2639#define DPM_TABLE_360__BAPMTI_RC_3_1_0_MASK 0xffff 2640#define DPM_TABLE_360__BAPMTI_RC_3_1_0__SHIFT 0x0 2641#define DPM_TABLE_360__BAPMTI_RC_3_0_0_MASK 0xffff0000 2642#define DPM_TABLE_360__BAPMTI_RC_3_0_0__SHIFT 0x10 2643#define DPM_TABLE_361__BAPMTI_RC_4_0_0_MASK 0xffff 2644#define DPM_TABLE_361__BAPMTI_RC_4_0_0__SHIFT 0x0 2645#define DPM_TABLE_361__BAPMTI_RC_3_2_0_MASK 0xffff0000 2646#define DPM_TABLE_361__BAPMTI_RC_3_2_0__SHIFT 0x10 2647#define DPM_TABLE_362__BAPMTI_RC_4_2_0_MASK 0xffff 2648#define DPM_TABLE_362__BAPMTI_RC_4_2_0__SHIFT 0x0 2649#define DPM_TABLE_362__BAPMTI_RC_4_1_0_MASK 0xffff0000 2650#define DPM_TABLE_362__BAPMTI_RC_4_1_0__SHIFT 0x10 2651#define DPM_TABLE_363__GpuTjHyst_MASK 0xff 2652#define DPM_TABLE_363__GpuTjHyst__SHIFT 0x0 2653#define DPM_TABLE_363__GpuTjMax_MASK 0xff00 2654#define DPM_TABLE_363__GpuTjMax__SHIFT 0x8 2655#define DPM_TABLE_363__DTETjOffset_MASK 0xff0000 2656#define DPM_TABLE_363__DTETjOffset__SHIFT 0x10 2657#define DPM_TABLE_363__DTEAmbientTempBase_MASK 0xff000000 2658#define DPM_TABLE_363__DTEAmbientTempBase__SHIFT 0x18 2659#define DPM_TABLE_364__BootVddci_MASK 0xffff 2660#define DPM_TABLE_364__BootVddci__SHIFT 0x0 2661#define DPM_TABLE_364__BootVddc_MASK 0xffff0000 2662#define DPM_TABLE_364__BootVddc__SHIFT 0x10 2663#define DPM_TABLE_365__padding_MASK 0xffff 2664#define DPM_TABLE_365__padding__SHIFT 0x0 2665#define DPM_TABLE_365__BootMVdd_MASK 0xffff0000 2666#define DPM_TABLE_365__BootMVdd__SHIFT 0x10 2667#define DPM_TABLE_366__BAPM_TEMP_GRADIENT_MASK 0xffffffff 2668#define DPM_TABLE_366__BAPM_TEMP_GRADIENT__SHIFT 0x0 2669#define DPM_TABLE_367__LowSclkInterruptThreshold_MASK 0xffffffff 2670#define DPM_TABLE_367__LowSclkInterruptThreshold__SHIFT 0x0 2671#define DPM_TABLE_368__VddGfxReChkWait_MASK 0xffffffff 2672#define DPM_TABLE_368__VddGfxReChkWait__SHIFT 0x0 2673#define DPM_TABLE_369__PPM_TemperatureLimit_MASK 0xffff 2674#define DPM_TABLE_369__PPM_TemperatureLimit__SHIFT 0x0 2675#define DPM_TABLE_369__PPM_PkgPwrLimit_MASK 0xffff0000 2676#define DPM_TABLE_369__PPM_PkgPwrLimit__SHIFT 0x10 2677#define DPM_TABLE_370__TargetTdp_MASK 0xffff 2678#define DPM_TABLE_370__TargetTdp__SHIFT 0x0 2679#define DPM_TABLE_370__DefaultTdp_MASK 0xffff0000 2680#define DPM_TABLE_370__DefaultTdp__SHIFT 0x10 2681#define SOFT_REGISTERS_TABLE_1__RefClockFrequency_MASK 0xffffffff 2682#define SOFT_REGISTERS_TABLE_1__RefClockFrequency__SHIFT 0x0 2683#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod_MASK 0xffffffff 2684#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod__SHIFT 0x0 2685#define SOFT_REGISTERS_TABLE_3__FeatureEnables_MASK 0xffffffff 2686#define SOFT_REGISTERS_TABLE_3__FeatureEnables__SHIFT 0x0 2687#define SOFT_REGISTERS_TABLE_4__PreVBlankGap_MASK 0xffffffff 2688#define SOFT_REGISTERS_TABLE_4__PreVBlankGap__SHIFT 0x0 2689#define SOFT_REGISTERS_TABLE_5__VBlankTimeout_MASK 0xffffffff 2690#define SOFT_REGISTERS_TABLE_5__VBlankTimeout__SHIFT 0x0 2691#define SOFT_REGISTERS_TABLE_6__TrainTimeGap_MASK 0xffffffff 2692#define SOFT_REGISTERS_TABLE_6__TrainTimeGap__SHIFT 0x0 2693#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime_MASK 0xffffffff 2694#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime__SHIFT 0x0 2695#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime_MASK 0xffffffff 2696#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime__SHIFT 0x0 2697#define SOFT_REGISTERS_TABLE_9__AcpiDelay_MASK 0xffffffff 2698#define SOFT_REGISTERS_TABLE_9__AcpiDelay__SHIFT 0x0 2699#define SOFT_REGISTERS_TABLE_10__G5TrainTime_MASK 0xffffffff 2700#define SOFT_REGISTERS_TABLE_10__G5TrainTime__SHIFT 0x0 2701#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron_MASK 0xffffffff 2702#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron__SHIFT 0x0 2703#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout_MASK 0xffffffff 2704#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout__SHIFT 0x0 2705#define SOFT_REGISTERS_TABLE_13__HandshakeDisables_MASK 0xffffffff 2706#define SOFT_REGISTERS_TABLE_13__HandshakeDisables__SHIFT 0x0 2707#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK 0xff 2708#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config__SHIFT 0x0 2709#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config_MASK 0xff00 2710#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config__SHIFT 0x8 2711#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config_MASK 0xff0000 2712#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config__SHIFT 0x10 2713#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config_MASK 0xff000000 2714#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config__SHIFT 0x18 2715#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config_MASK 0xff 2716#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config__SHIFT 0x0 2717#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK 0xff00 2718#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config__SHIFT 0x8 2719#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK 0xff0000 2720#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT 0x10 2721#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config_MASK 0xff000000 2722#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config__SHIFT 0x18 2723#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity_MASK 0xffffffff 2724#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity__SHIFT 0x0 2725#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity_MASK 0xffffffff 2726#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity__SHIFT 0x0 2727#define SOFT_REGISTERS_TABLE_18__AverageGioActivity_MASK 0xffffffff 2728#define SOFT_REGISTERS_TABLE_18__AverageGioActivity__SHIFT 0x0 2729#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels_MASK 0xff 2730#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels__SHIFT 0x0 2731#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels_MASK 0xff00 2732#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels__SHIFT 0x8 2733#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels_MASK 0xff0000 2734#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels__SHIFT 0x10 2735#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels_MASK 0xff000000 2736#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels__SHIFT 0x18 2737#define SOFT_REGISTERS_TABLE_20__DRAM_LOG_ADDR_H_MASK 0xffffffff 2738#define SOFT_REGISTERS_TABLE_20__DRAM_LOG_ADDR_H__SHIFT 0x0 2739#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_L_MASK 0xffffffff 2740#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_L__SHIFT 0x0 2741#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_PHY_ADDR_H_MASK 0xffffffff 2742#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_PHY_ADDR_H__SHIFT 0x0 2743#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_L_MASK 0xffffffff 2744#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_L__SHIFT 0x0 2745#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_BUFF_SIZE_MASK 0xffffffff 2746#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_BUFF_SIZE__SHIFT 0x0 2747#define SOFT_REGISTERS_TABLE_25__UlvEnterCount_MASK 0xffffffff 2748#define SOFT_REGISTERS_TABLE_25__UlvEnterCount__SHIFT 0x0 2749#define SOFT_REGISTERS_TABLE_26__UlvTime_MASK 0xffffffff 2750#define SOFT_REGISTERS_TABLE_26__UlvTime__SHIFT 0x0 2751#define SOFT_REGISTERS_TABLE_27__UcodeLoadStatus_MASK 0xffffffff 2752#define SOFT_REGISTERS_TABLE_27__UcodeLoadStatus__SHIFT 0x0 2753#define SOFT_REGISTERS_TABLE_28__Reserved_0_MASK 0xffffffff 2754#define SOFT_REGISTERS_TABLE_28__Reserved_0__SHIFT 0x0 2755#define SOFT_REGISTERS_TABLE_29__Reserved_1_MASK 0xffffffff 2756#define SOFT_REGISTERS_TABLE_29__Reserved_1__SHIFT 0x0 2757#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1 2758#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 2759#define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe 2760#define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 2761#define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000 2762#define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18 2763#define TDC_STATUS__VDD_Boost_MASK 0xff 2764#define TDC_STATUS__VDD_Boost__SHIFT 0x0 2765#define TDC_STATUS__VDD_Throttle_MASK 0xff00 2766#define TDC_STATUS__VDD_Throttle__SHIFT 0x8 2767#define TDC_STATUS__VDDC_Boost_MASK 0xff0000 2768#define TDC_STATUS__VDDC_Boost__SHIFT 0x10 2769#define TDC_STATUS__VDDC_Throttle_MASK 0xff000000 2770#define TDC_STATUS__VDDC_Throttle__SHIFT 0x18 2771#define TDC_MV_AVERAGE__IDD_MASK 0xffff 2772#define TDC_MV_AVERAGE__IDD__SHIFT 0x0 2773#define TDC_MV_AVERAGE__IDDC_MASK 0xffff0000 2774#define TDC_MV_AVERAGE__IDDC__SHIFT 0x10 2775#define TDC_VRM_LIMIT__IDD_MASK 0xffff 2776#define TDC_VRM_LIMIT__IDD__SHIFT 0x0 2777#define TDC_VRM_LIMIT__IDDC_MASK 0xffff0000 2778#define TDC_VRM_LIMIT__IDDC__SHIFT 0x10 2779#define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1 2780#define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0 2781#define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2 2782#define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1 2783#define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4 2784#define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2 2785#define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8 2786#define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3 2787#define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10 2788#define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4 2789#define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x20 2790#define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x5 2791#define FEATURE_STATUS__ACP_DPM_ON_MASK 0x40 2792#define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x6 2793#define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80 2794#define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7 2795#define FEATURE_STATUS__BAPM_ON_MASK 0x100 2796#define FEATURE_STATUS__BAPM_ON__SHIFT 0x8 2797#define FEATURE_STATUS__LPMX_ON_MASK 0x200 2798#define FEATURE_STATUS__LPMX_ON__SHIFT 0x9 2799#define FEATURE_STATUS__NBDPM_ON_MASK 0x400 2800#define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa 2801#define FEATURE_STATUS__LHTC_ON_MASK 0x800 2802#define FEATURE_STATUS__LHTC_ON__SHIFT 0xb 2803#define FEATURE_STATUS__VPC_ON_MASK 0x1000 2804#define FEATURE_STATUS__VPC_ON__SHIFT 0xc 2805#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000 2806#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd 2807#define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000 2808#define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe 2809#define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000 2810#define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf 2811#define FEATURE_STATUS__AVS_ON_MASK 0x10000 2812#define FEATURE_STATUS__AVS_ON__SHIFT 0x10 2813#define FEATURE_STATUS__SPMI_ON_MASK 0x20000 2814#define FEATURE_STATUS__SPMI_ON__SHIFT 0x11 2815#define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000 2816#define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12 2817#define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000 2818#define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13 2819#define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000 2820#define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14 2821#define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000 2822#define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15 2823#define FEATURE_STATUS__RESERVED_MASK 0xffc00000 2824#define FEATURE_STATUS__RESERVED__SHIFT 0x16 2825#define ENTITY_TEMPERATURES_1__GPU_MASK 0xffffffff 2826#define ENTITY_TEMPERATURES_1__GPU__SHIFT 0x0 2827#define PM_FUSES_1__BapmVddCVidHiSidd_3_MASK 0xff 2828#define PM_FUSES_1__BapmVddCVidHiSidd_3__SHIFT 0x0 2829#define PM_FUSES_1__BapmVddCVidHiSidd_2_MASK 0xff00 2830#define PM_FUSES_1__BapmVddCVidHiSidd_2__SHIFT 0x8 2831#define PM_FUSES_1__BapmVddCVidHiSidd_1_MASK 0xff0000 2832#define PM_FUSES_1__BapmVddCVidHiSidd_1__SHIFT 0x10 2833#define PM_FUSES_1__BapmVddCVidHiSidd_0_MASK 0xff000000 2834#define PM_FUSES_1__BapmVddCVidHiSidd_0__SHIFT 0x18 2835#define PM_FUSES_2__BapmVddCVidHiSidd_7_MASK 0xff 2836#define PM_FUSES_2__BapmVddCVidHiSidd_7__SHIFT 0x0 2837#define PM_FUSES_2__BapmVddCVidHiSidd_6_MASK 0xff00 2838#define PM_FUSES_2__BapmVddCVidHiSidd_6__SHIFT 0x8 2839#define PM_FUSES_2__BapmVddCVidHiSidd_5_MASK 0xff0000 2840#define PM_FUSES_2__BapmVddCVidHiSidd_5__SHIFT 0x10 2841#define PM_FUSES_2__BapmVddCVidHiSidd_4_MASK 0xff000000 2842#define PM_FUSES_2__BapmVddCVidHiSidd_4__SHIFT 0x18 2843#define PM_FUSES_3__BapmVddCVidLoSidd_3_MASK 0xff 2844#define PM_FUSES_3__BapmVddCVidLoSidd_3__SHIFT 0x0 2845#define PM_FUSES_3__BapmVddCVidLoSidd_2_MASK 0xff00 2846#define PM_FUSES_3__BapmVddCVidLoSidd_2__SHIFT 0x8 2847#define PM_FUSES_3__BapmVddCVidLoSidd_1_MASK 0xff0000 2848#define PM_FUSES_3__BapmVddCVidLoSidd_1__SHIFT 0x10 2849#define PM_FUSES_3__BapmVddCVidLoSidd_0_MASK 0xff000000 2850#define PM_FUSES_3__BapmVddCVidLoSidd_0__SHIFT 0x18 2851#define PM_FUSES_4__BapmVddCVidLoSidd_7_MASK 0xff 2852#define PM_FUSES_4__BapmVddCVidLoSidd_7__SHIFT 0x0 2853#define PM_FUSES_4__BapmVddCVidLoSidd_6_MASK 0xff00 2854#define PM_FUSES_4__BapmVddCVidLoSidd_6__SHIFT 0x8 2855#define PM_FUSES_4__BapmVddCVidLoSidd_5_MASK 0xff0000 2856#define PM_FUSES_4__BapmVddCVidLoSidd_5__SHIFT 0x10 2857#define PM_FUSES_4__BapmVddCVidLoSidd_4_MASK 0xff000000 2858#define PM_FUSES_4__BapmVddCVidLoSidd_4__SHIFT 0x18 2859#define PM_FUSES_5__VddCVid_3_MASK 0xff 2860#define PM_FUSES_5__VddCVid_3__SHIFT 0x0 2861#define PM_FUSES_5__VddCVid_2_MASK 0xff00 2862#define PM_FUSES_5__VddCVid_2__SHIFT 0x8 2863#define PM_FUSES_5__VddCVid_1_MASK 0xff0000 2864#define PM_FUSES_5__VddCVid_1__SHIFT 0x10 2865#define PM_FUSES_5__VddCVid_0_MASK 0xff000000 2866#define PM_FUSES_5__VddCVid_0__SHIFT 0x18 2867#define PM_FUSES_6__VddCVid_7_MASK 0xff 2868#define PM_FUSES_6__VddCVid_7__SHIFT 0x0 2869#define PM_FUSES_6__VddCVid_6_MASK 0xff00 2870#define PM_FUSES_6__VddCVid_6__SHIFT 0x8 2871#define PM_FUSES_6__VddCVid_5_MASK 0xff0000 2872#define PM_FUSES_6__VddCVid_5__SHIFT 0x10 2873#define PM_FUSES_6__VddCVid_4_MASK 0xff000000 2874#define PM_FUSES_6__VddCVid_4__SHIFT 0x18 2875#define PM_FUSES_7__SviLoadLineOffsetVddC_MASK 0xff 2876#define PM_FUSES_7__SviLoadLineOffsetVddC__SHIFT 0x0 2877#define PM_FUSES_7__SviLoadLineTrimVddC_MASK 0xff00 2878#define PM_FUSES_7__SviLoadLineTrimVddC__SHIFT 0x8 2879#define PM_FUSES_7__SviLoadLineVddC_MASK 0xff0000 2880#define PM_FUSES_7__SviLoadLineVddC__SHIFT 0x10 2881#define PM_FUSES_7__SviLoadLineEn_MASK 0xff000000 2882#define PM_FUSES_7__SviLoadLineEn__SHIFT 0x18 2883#define PM_FUSES_8__TDC_MAWt_MASK 0xff 2884#define PM_FUSES_8__TDC_MAWt__SHIFT 0x0 2885#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc_MASK 0xff00 2886#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc__SHIFT 0x8 2887#define PM_FUSES_8__TDC_VDDC_PkgLimit_MASK 0xffff0000 2888#define PM_FUSES_8__TDC_VDDC_PkgLimit__SHIFT 0x10 2889#define PM_FUSES_9__Reserved_MASK 0xff 2890#define PM_FUSES_9__Reserved__SHIFT 0x0 2891#define PM_FUSES_9__LPMLTemperatureMax_MASK 0xff00 2892#define PM_FUSES_9__LPMLTemperatureMax__SHIFT 0x8 2893#define PM_FUSES_9__LPMLTemperatureMin_MASK 0xff0000 2894#define PM_FUSES_9__LPMLTemperatureMin__SHIFT 0x10 2895#define PM_FUSES_9__TdcWaterfallCtl_MASK 0xff000000 2896#define PM_FUSES_9__TdcWaterfallCtl__SHIFT 0x18 2897#define PM_FUSES_10__LPMLTemperatureScaler_3_MASK 0xff 2898#define PM_FUSES_10__LPMLTemperatureScaler_3__SHIFT 0x0 2899#define PM_FUSES_10__LPMLTemperatureScaler_2_MASK 0xff00 2900#define PM_FUSES_10__LPMLTemperatureScaler_2__SHIFT 0x8 2901#define PM_FUSES_10__LPMLTemperatureScaler_1_MASK 0xff0000 2902#define PM_FUSES_10__LPMLTemperatureScaler_1__SHIFT 0x10 2903#define PM_FUSES_10__LPMLTemperatureScaler_0_MASK 0xff000000 2904#define PM_FUSES_10__LPMLTemperatureScaler_0__SHIFT 0x18 2905#define PM_FUSES_11__LPMLTemperatureScaler_7_MASK 0xff 2906#define PM_FUSES_11__LPMLTemperatureScaler_7__SHIFT 0x0 2907#define PM_FUSES_11__LPMLTemperatureScaler_6_MASK 0xff00 2908#define PM_FUSES_11__LPMLTemperatureScaler_6__SHIFT 0x8 2909#define PM_FUSES_11__LPMLTemperatureScaler_5_MASK 0xff0000 2910#define PM_FUSES_11__LPMLTemperatureScaler_5__SHIFT 0x10 2911#define PM_FUSES_11__LPMLTemperatureScaler_4_MASK 0xff000000 2912#define PM_FUSES_11__LPMLTemperatureScaler_4__SHIFT 0x18 2913#define PM_FUSES_12__LPMLTemperatureScaler_11_MASK 0xff 2914#define PM_FUSES_12__LPMLTemperatureScaler_11__SHIFT 0x0 2915#define PM_FUSES_12__LPMLTemperatureScaler_10_MASK 0xff00 2916#define PM_FUSES_12__LPMLTemperatureScaler_10__SHIFT 0x8 2917#define PM_FUSES_12__LPMLTemperatureScaler_9_MASK 0xff0000 2918#define PM_FUSES_12__LPMLTemperatureScaler_9__SHIFT 0x10 2919#define PM_FUSES_12__LPMLTemperatureScaler_8_MASK 0xff000000 2920#define PM_FUSES_12__LPMLTemperatureScaler_8__SHIFT 0x18 2921#define PM_FUSES_13__LPMLTemperatureScaler_15_MASK 0xff 2922#define PM_FUSES_13__LPMLTemperatureScaler_15__SHIFT 0x0 2923#define PM_FUSES_13__LPMLTemperatureScaler_14_MASK 0xff00 2924#define PM_FUSES_13__LPMLTemperatureScaler_14__SHIFT 0x8 2925#define PM_FUSES_13__LPMLTemperatureScaler_13_MASK 0xff0000 2926#define PM_FUSES_13__LPMLTemperatureScaler_13__SHIFT 0x10 2927#define PM_FUSES_13__LPMLTemperatureScaler_12_MASK 0xff000000 2928#define PM_FUSES_13__LPMLTemperatureScaler_12__SHIFT 0x18 2929#define PM_FUSES_14__FuzzyFan_ErrorRateSetDelta_MASK 0xffff 2930#define PM_FUSES_14__FuzzyFan_ErrorRateSetDelta__SHIFT 0x0 2931#define PM_FUSES_14__FuzzyFan_ErrorSetDelta_MASK 0xffff0000 2932#define PM_FUSES_14__FuzzyFan_ErrorSetDelta__SHIFT 0x10 2933#define PM_FUSES_15__Reserved6_MASK 0xffff 2934#define PM_FUSES_15__Reserved6__SHIFT 0x0 2935#define PM_FUSES_15__FuzzyFan_PwmSetDelta_MASK 0xffff0000 2936#define PM_FUSES_15__FuzzyFan_PwmSetDelta__SHIFT 0x10 2937#define PM_FUSES_16__GnbLPML_3_MASK 0xff 2938#define PM_FUSES_16__GnbLPML_3__SHIFT 0x0 2939#define PM_FUSES_16__GnbLPML_2_MASK 0xff00 2940#define PM_FUSES_16__GnbLPML_2__SHIFT 0x8 2941#define PM_FUSES_16__GnbLPML_1_MASK 0xff0000 2942#define PM_FUSES_16__GnbLPML_1__SHIFT 0x10 2943#define PM_FUSES_16__GnbLPML_0_MASK 0xff000000 2944#define PM_FUSES_16__GnbLPML_0__SHIFT 0x18 2945#define PM_FUSES_17__GnbLPML_7_MASK 0xff 2946#define PM_FUSES_17__GnbLPML_7__SHIFT 0x0 2947#define PM_FUSES_17__GnbLPML_6_MASK 0xff00 2948#define PM_FUSES_17__GnbLPML_6__SHIFT 0x8 2949#define PM_FUSES_17__GnbLPML_5_MASK 0xff0000 2950#define PM_FUSES_17__GnbLPML_5__SHIFT 0x10 2951#define PM_FUSES_17__GnbLPML_4_MASK 0xff000000 2952#define PM_FUSES_17__GnbLPML_4__SHIFT 0x18 2953#define PM_FUSES_18__GnbLPML_11_MASK 0xff 2954#define PM_FUSES_18__GnbLPML_11__SHIFT 0x0 2955#define PM_FUSES_18__GnbLPML_10_MASK 0xff00 2956#define PM_FUSES_18__GnbLPML_10__SHIFT 0x8 2957#define PM_FUSES_18__GnbLPML_9_MASK 0xff0000 2958#define PM_FUSES_18__GnbLPML_9__SHIFT 0x10 2959#define PM_FUSES_18__GnbLPML_8_MASK 0xff000000 2960#define PM_FUSES_18__GnbLPML_8__SHIFT 0x18 2961#define PM_FUSES_19__GnbLPML_15_MASK 0xff 2962#define PM_FUSES_19__GnbLPML_15__SHIFT 0x0 2963#define PM_FUSES_19__GnbLPML_14_MASK 0xff00 2964#define PM_FUSES_19__GnbLPML_14__SHIFT 0x8 2965#define PM_FUSES_19__GnbLPML_13_MASK 0xff0000 2966#define PM_FUSES_19__GnbLPML_13__SHIFT 0x10 2967#define PM_FUSES_19__GnbLPML_12_MASK 0xff000000 2968#define PM_FUSES_19__GnbLPML_12__SHIFT 0x18 2969#define PM_FUSES_20__Reserved1_1_MASK 0xff 2970#define PM_FUSES_20__Reserved1_1__SHIFT 0x0 2971#define PM_FUSES_20__Reserved1_0_MASK 0xff00 2972#define PM_FUSES_20__Reserved1_0__SHIFT 0x8 2973#define PM_FUSES_20__GnbLPMLMinVid_MASK 0xff0000 2974#define PM_FUSES_20__GnbLPMLMinVid__SHIFT 0x10 2975#define PM_FUSES_20__GnbLPMLMaxVid_MASK 0xff000000 2976#define PM_FUSES_20__GnbLPMLMaxVid__SHIFT 0x18 2977#define PM_FUSES_21__BapmVddCBaseLeakageLoSidd_MASK 0xffff 2978#define PM_FUSES_21__BapmVddCBaseLeakageLoSidd__SHIFT 0x0 2979#define PM_FUSES_21__BapmVddCBaseLeakageHiSidd_MASK 0xffff0000 2980#define PM_FUSES_21__BapmVddCBaseLeakageHiSidd__SHIFT 0x10 2981#define SMU_PM_STATUS_0__DATA_MASK 0xffffffff 2982#define SMU_PM_STATUS_0__DATA__SHIFT 0x0 2983#define SMU_PM_STATUS_1__DATA_MASK 0xffffffff 2984#define SMU_PM_STATUS_1__DATA__SHIFT 0x0 2985#define SMU_PM_STATUS_2__DATA_MASK 0xffffffff 2986#define SMU_PM_STATUS_2__DATA__SHIFT 0x0 2987#define SMU_PM_STATUS_3__DATA_MASK 0xffffffff 2988#define SMU_PM_STATUS_3__DATA__SHIFT 0x0 2989#define SMU_PM_STATUS_4__DATA_MASK 0xffffffff 2990#define SMU_PM_STATUS_4__DATA__SHIFT 0x0 2991#define SMU_PM_STATUS_5__DATA_MASK 0xffffffff 2992#define SMU_PM_STATUS_5__DATA__SHIFT 0x0 2993#define SMU_PM_STATUS_6__DATA_MASK 0xffffffff 2994#define SMU_PM_STATUS_6__DATA__SHIFT 0x0 2995#define SMU_PM_STATUS_7__DATA_MASK 0xffffffff 2996#define SMU_PM_STATUS_7__DATA__SHIFT 0x0 2997#define SMU_PM_STATUS_8__DATA_MASK 0xffffffff 2998#define SMU_PM_STATUS_8__DATA__SHIFT 0x0 2999#define SMU_PM_STATUS_9__DATA_MASK 0xffffffff 3000#define SMU_PM_STATUS_9__DATA__SHIFT 0x0 3001#define SMU_PM_STATUS_10__DATA_MASK 0xffffffff 3002#define SMU_PM_STATUS_10__DATA__SHIFT 0x0 3003#define SMU_PM_STATUS_11__DATA_MASK 0xffffffff 3004#define SMU_PM_STATUS_11__DATA__SHIFT 0x0 3005#define SMU_PM_STATUS_12__DATA_MASK 0xffffffff 3006#define SMU_PM_STATUS_12__DATA__SHIFT 0x0 3007#define SMU_PM_STATUS_13__DATA_MASK 0xffffffff 3008#define SMU_PM_STATUS_13__DATA__SHIFT 0x0 3009#define SMU_PM_STATUS_14__DATA_MASK 0xffffffff 3010#define SMU_PM_STATUS_14__DATA__SHIFT 0x0 3011#define SMU_PM_STATUS_15__DATA_MASK 0xffffffff 3012#define SMU_PM_STATUS_15__DATA__SHIFT 0x0 3013#define SMU_PM_STATUS_16__DATA_MASK 0xffffffff 3014#define SMU_PM_STATUS_16__DATA__SHIFT 0x0 3015#define SMU_PM_STATUS_17__DATA_MASK 0xffffffff 3016#define SMU_PM_STATUS_17__DATA__SHIFT 0x0 3017#define SMU_PM_STATUS_18__DATA_MASK 0xffffffff 3018#define SMU_PM_STATUS_18__DATA__SHIFT 0x0 3019#define SMU_PM_STATUS_19__DATA_MASK 0xffffffff 3020#define SMU_PM_STATUS_19__DATA__SHIFT 0x0 3021#define SMU_PM_STATUS_20__DATA_MASK 0xffffffff 3022#define SMU_PM_STATUS_20__DATA__SHIFT 0x0 3023#define SMU_PM_STATUS_21__DATA_MASK 0xffffffff 3024#define SMU_PM_STATUS_21__DATA__SHIFT 0x0 3025#define SMU_PM_STATUS_22__DATA_MASK 0xffffffff 3026#define SMU_PM_STATUS_22__DATA__SHIFT 0x0 3027#define SMU_PM_STATUS_23__DATA_MASK 0xffffffff 3028#define SMU_PM_STATUS_23__DATA__SHIFT 0x0 3029#define SMU_PM_STATUS_24__DATA_MASK 0xffffffff 3030#define SMU_PM_STATUS_24__DATA__SHIFT 0x0 3031#define SMU_PM_STATUS_25__DATA_MASK 0xffffffff 3032#define SMU_PM_STATUS_25__DATA__SHIFT 0x0 3033#define SMU_PM_STATUS_26__DATA_MASK 0xffffffff 3034#define SMU_PM_STATUS_26__DATA__SHIFT 0x0 3035#define SMU_PM_STATUS_27__DATA_MASK 0xffffffff 3036#define SMU_PM_STATUS_27__DATA__SHIFT 0x0 3037#define SMU_PM_STATUS_28__DATA_MASK 0xffffffff 3038#define SMU_PM_STATUS_28__DATA__SHIFT 0x0 3039#define SMU_PM_STATUS_29__DATA_MASK 0xffffffff 3040#define SMU_PM_STATUS_29__DATA__SHIFT 0x0 3041#define SMU_PM_STATUS_30__DATA_MASK 0xffffffff 3042#define SMU_PM_STATUS_30__DATA__SHIFT 0x0 3043#define SMU_PM_STATUS_31__DATA_MASK 0xffffffff 3044#define SMU_PM_STATUS_31__DATA__SHIFT 0x0 3045#define SMU_PM_STATUS_32__DATA_MASK 0xffffffff 3046#define SMU_PM_STATUS_32__DATA__SHIFT 0x0 3047#define SMU_PM_STATUS_33__DATA_MASK 0xffffffff 3048#define SMU_PM_STATUS_33__DATA__SHIFT 0x0 3049#define SMU_PM_STATUS_34__DATA_MASK 0xffffffff 3050#define SMU_PM_STATUS_34__DATA__SHIFT 0x0 3051#define SMU_PM_STATUS_35__DATA_MASK 0xffffffff 3052#define SMU_PM_STATUS_35__DATA__SHIFT 0x0 3053#define SMU_PM_STATUS_36__DATA_MASK 0xffffffff 3054#define SMU_PM_STATUS_36__DATA__SHIFT 0x0 3055#define SMU_PM_STATUS_37__DATA_MASK 0xffffffff 3056#define SMU_PM_STATUS_37__DATA__SHIFT 0x0 3057#define SMU_PM_STATUS_38__DATA_MASK 0xffffffff 3058#define SMU_PM_STATUS_38__DATA__SHIFT 0x0 3059#define SMU_PM_STATUS_39__DATA_MASK 0xffffffff 3060#define SMU_PM_STATUS_39__DATA__SHIFT 0x0 3061#define SMU_PM_STATUS_40__DATA_MASK 0xffffffff 3062#define SMU_PM_STATUS_40__DATA__SHIFT 0x0 3063#define SMU_PM_STATUS_41__DATA_MASK 0xffffffff 3064#define SMU_PM_STATUS_41__DATA__SHIFT 0x0 3065#define SMU_PM_STATUS_42__DATA_MASK 0xffffffff 3066#define SMU_PM_STATUS_42__DATA__SHIFT 0x0 3067#define SMU_PM_STATUS_43__DATA_MASK 0xffffffff 3068#define SMU_PM_STATUS_43__DATA__SHIFT 0x0 3069#define SMU_PM_STATUS_44__DATA_MASK 0xffffffff 3070#define SMU_PM_STATUS_44__DATA__SHIFT 0x0 3071#define SMU_PM_STATUS_45__DATA_MASK 0xffffffff 3072#define SMU_PM_STATUS_45__DATA__SHIFT 0x0 3073#define SMU_PM_STATUS_46__DATA_MASK 0xffffffff 3074#define SMU_PM_STATUS_46__DATA__SHIFT 0x0 3075#define SMU_PM_STATUS_47__DATA_MASK 0xffffffff 3076#define SMU_PM_STATUS_47__DATA__SHIFT 0x0 3077#define SMU_PM_STATUS_48__DATA_MASK 0xffffffff 3078#define SMU_PM_STATUS_48__DATA__SHIFT 0x0 3079#define SMU_PM_STATUS_49__DATA_MASK 0xffffffff 3080#define SMU_PM_STATUS_49__DATA__SHIFT 0x0 3081#define SMU_PM_STATUS_50__DATA_MASK 0xffffffff 3082#define SMU_PM_STATUS_50__DATA__SHIFT 0x0 3083#define SMU_PM_STATUS_51__DATA_MASK 0xffffffff 3084#define SMU_PM_STATUS_51__DATA__SHIFT 0x0 3085#define SMU_PM_STATUS_52__DATA_MASK 0xffffffff 3086#define SMU_PM_STATUS_52__DATA__SHIFT 0x0 3087#define SMU_PM_STATUS_53__DATA_MASK 0xffffffff 3088#define SMU_PM_STATUS_53__DATA__SHIFT 0x0 3089#define SMU_PM_STATUS_54__DATA_MASK 0xffffffff 3090#define SMU_PM_STATUS_54__DATA__SHIFT 0x0 3091#define SMU_PM_STATUS_55__DATA_MASK 0xffffffff 3092#define SMU_PM_STATUS_55__DATA__SHIFT 0x0 3093#define SMU_PM_STATUS_56__DATA_MASK 0xffffffff 3094#define SMU_PM_STATUS_56__DATA__SHIFT 0x0 3095#define SMU_PM_STATUS_57__DATA_MASK 0xffffffff 3096#define SMU_PM_STATUS_57__DATA__SHIFT 0x0 3097#define SMU_PM_STATUS_58__DATA_MASK 0xffffffff 3098#define SMU_PM_STATUS_58__DATA__SHIFT 0x0 3099#define SMU_PM_STATUS_59__DATA_MASK 0xffffffff 3100#define SMU_PM_STATUS_59__DATA__SHIFT 0x0 3101#define SMU_PM_STATUS_60__DATA_MASK 0xffffffff 3102#define SMU_PM_STATUS_60__DATA__SHIFT 0x0 3103#define SMU_PM_STATUS_61__DATA_MASK 0xffffffff 3104#define SMU_PM_STATUS_61__DATA__SHIFT 0x0 3105#define SMU_PM_STATUS_62__DATA_MASK 0xffffffff 3106#define SMU_PM_STATUS_62__DATA__SHIFT 0x0 3107#define SMU_PM_STATUS_63__DATA_MASK 0xffffffff 3108#define SMU_PM_STATUS_63__DATA__SHIFT 0x0 3109#define SMU_PM_STATUS_64__DATA_MASK 0xffffffff 3110#define SMU_PM_STATUS_64__DATA__SHIFT 0x0 3111#define SMU_PM_STATUS_65__DATA_MASK 0xffffffff 3112#define SMU_PM_STATUS_65__DATA__SHIFT 0x0 3113#define SMU_PM_STATUS_66__DATA_MASK 0xffffffff 3114#define SMU_PM_STATUS_66__DATA__SHIFT 0x0 3115#define SMU_PM_STATUS_67__DATA_MASK 0xffffffff 3116#define SMU_PM_STATUS_67__DATA__SHIFT 0x0 3117#define SMU_PM_STATUS_68__DATA_MASK 0xffffffff 3118#define SMU_PM_STATUS_68__DATA__SHIFT 0x0 3119#define SMU_PM_STATUS_69__DATA_MASK 0xffffffff 3120#define SMU_PM_STATUS_69__DATA__SHIFT 0x0 3121#define SMU_PM_STATUS_70__DATA_MASK 0xffffffff 3122#define SMU_PM_STATUS_70__DATA__SHIFT 0x0 3123#define SMU_PM_STATUS_71__DATA_MASK 0xffffffff 3124#define SMU_PM_STATUS_71__DATA__SHIFT 0x0 3125#define SMU_PM_STATUS_72__DATA_MASK 0xffffffff 3126#define SMU_PM_STATUS_72__DATA__SHIFT 0x0 3127#define SMU_PM_STATUS_73__DATA_MASK 0xffffffff 3128#define SMU_PM_STATUS_73__DATA__SHIFT 0x0 3129#define SMU_PM_STATUS_74__DATA_MASK 0xffffffff 3130#define SMU_PM_STATUS_74__DATA__SHIFT 0x0 3131#define SMU_PM_STATUS_75__DATA_MASK 0xffffffff 3132#define SMU_PM_STATUS_75__DATA__SHIFT 0x0 3133#define SMU_PM_STATUS_76__DATA_MASK 0xffffffff 3134#define SMU_PM_STATUS_76__DATA__SHIFT 0x0 3135#define SMU_PM_STATUS_77__DATA_MASK 0xffffffff 3136#define SMU_PM_STATUS_77__DATA__SHIFT 0x0 3137#define SMU_PM_STATUS_78__DATA_MASK 0xffffffff 3138#define SMU_PM_STATUS_78__DATA__SHIFT 0x0 3139#define SMU_PM_STATUS_79__DATA_MASK 0xffffffff 3140#define SMU_PM_STATUS_79__DATA__SHIFT 0x0 3141#define SMU_PM_STATUS_80__DATA_MASK 0xffffffff 3142#define SMU_PM_STATUS_80__DATA__SHIFT 0x0 3143#define SMU_PM_STATUS_81__DATA_MASK 0xffffffff 3144#define SMU_PM_STATUS_81__DATA__SHIFT 0x0 3145#define SMU_PM_STATUS_82__DATA_MASK 0xffffffff 3146#define SMU_PM_STATUS_82__DATA__SHIFT 0x0 3147#define SMU_PM_STATUS_83__DATA_MASK 0xffffffff 3148#define SMU_PM_STATUS_83__DATA__SHIFT 0x0 3149#define SMU_PM_STATUS_84__DATA_MASK 0xffffffff 3150#define SMU_PM_STATUS_84__DATA__SHIFT 0x0 3151#define SMU_PM_STATUS_85__DATA_MASK 0xffffffff 3152#define SMU_PM_STATUS_85__DATA__SHIFT 0x0 3153#define SMU_PM_STATUS_86__DATA_MASK 0xffffffff 3154#define SMU_PM_STATUS_86__DATA__SHIFT 0x0 3155#define SMU_PM_STATUS_87__DATA_MASK 0xffffffff 3156#define SMU_PM_STATUS_87__DATA__SHIFT 0x0 3157#define SMU_PM_STATUS_88__DATA_MASK 0xffffffff 3158#define SMU_PM_STATUS_88__DATA__SHIFT 0x0 3159#define SMU_PM_STATUS_89__DATA_MASK 0xffffffff 3160#define SMU_PM_STATUS_89__DATA__SHIFT 0x0 3161#define SMU_PM_STATUS_90__DATA_MASK 0xffffffff 3162#define SMU_PM_STATUS_90__DATA__SHIFT 0x0 3163#define SMU_PM_STATUS_91__DATA_MASK 0xffffffff 3164#define SMU_PM_STATUS_91__DATA__SHIFT 0x0 3165#define SMU_PM_STATUS_92__DATA_MASK 0xffffffff 3166#define SMU_PM_STATUS_92__DATA__SHIFT 0x0 3167#define SMU_PM_STATUS_93__DATA_MASK 0xffffffff 3168#define SMU_PM_STATUS_93__DATA__SHIFT 0x0 3169#define SMU_PM_STATUS_94__DATA_MASK 0xffffffff 3170#define SMU_PM_STATUS_94__DATA__SHIFT 0x0 3171#define SMU_PM_STATUS_95__DATA_MASK 0xffffffff 3172#define SMU_PM_STATUS_95__DATA__SHIFT 0x0 3173#define SMU_PM_STATUS_96__DATA_MASK 0xffffffff 3174#define SMU_PM_STATUS_96__DATA__SHIFT 0x0 3175#define SMU_PM_STATUS_97__DATA_MASK 0xffffffff 3176#define SMU_PM_STATUS_97__DATA__SHIFT 0x0 3177#define SMU_PM_STATUS_98__DATA_MASK 0xffffffff 3178#define SMU_PM_STATUS_98__DATA__SHIFT 0x0 3179#define SMU_PM_STATUS_99__DATA_MASK 0xffffffff 3180#define SMU_PM_STATUS_99__DATA__SHIFT 0x0 3181#define SMU_PM_STATUS_100__DATA_MASK 0xffffffff 3182#define SMU_PM_STATUS_100__DATA__SHIFT 0x0 3183#define SMU_PM_STATUS_101__DATA_MASK 0xffffffff 3184#define SMU_PM_STATUS_101__DATA__SHIFT 0x0 3185#define SMU_PM_STATUS_102__DATA_MASK 0xffffffff 3186#define SMU_PM_STATUS_102__DATA__SHIFT 0x0 3187#define SMU_PM_STATUS_103__DATA_MASK 0xffffffff 3188#define SMU_PM_STATUS_103__DATA__SHIFT 0x0 3189#define SMU_PM_STATUS_104__DATA_MASK 0xffffffff 3190#define SMU_PM_STATUS_104__DATA__SHIFT 0x0 3191#define SMU_PM_STATUS_105__DATA_MASK 0xffffffff 3192#define SMU_PM_STATUS_105__DATA__SHIFT 0x0 3193#define SMU_PM_STATUS_106__DATA_MASK 0xffffffff 3194#define SMU_PM_STATUS_106__DATA__SHIFT 0x0 3195#define SMU_PM_STATUS_107__DATA_MASK 0xffffffff 3196#define SMU_PM_STATUS_107__DATA__SHIFT 0x0 3197#define SMU_PM_STATUS_108__DATA_MASK 0xffffffff 3198#define SMU_PM_STATUS_108__DATA__SHIFT 0x0 3199#define SMU_PM_STATUS_109__DATA_MASK 0xffffffff 3200#define SMU_PM_STATUS_109__DATA__SHIFT 0x0 3201#define SMU_PM_STATUS_110__DATA_MASK 0xffffffff 3202#define SMU_PM_STATUS_110__DATA__SHIFT 0x0 3203#define SMU_PM_STATUS_111__DATA_MASK 0xffffffff 3204#define SMU_PM_STATUS_111__DATA__SHIFT 0x0 3205#define SMU_PM_STATUS_112__DATA_MASK 0xffffffff 3206#define SMU_PM_STATUS_112__DATA__SHIFT 0x0 3207#define SMU_PM_STATUS_113__DATA_MASK 0xffffffff 3208#define SMU_PM_STATUS_113__DATA__SHIFT 0x0 3209#define SMU_PM_STATUS_114__DATA_MASK 0xffffffff 3210#define SMU_PM_STATUS_114__DATA__SHIFT 0x0 3211#define SMU_PM_STATUS_115__DATA_MASK 0xffffffff 3212#define SMU_PM_STATUS_115__DATA__SHIFT 0x0 3213#define SMU_PM_STATUS_116__DATA_MASK 0xffffffff 3214#define SMU_PM_STATUS_116__DATA__SHIFT 0x0 3215#define SMU_PM_STATUS_117__DATA_MASK 0xffffffff 3216#define SMU_PM_STATUS_117__DATA__SHIFT 0x0 3217#define SMU_PM_STATUS_118__DATA_MASK 0xffffffff 3218#define SMU_PM_STATUS_118__DATA__SHIFT 0x0 3219#define SMU_PM_STATUS_119__DATA_MASK 0xffffffff 3220#define SMU_PM_STATUS_119__DATA__SHIFT 0x0 3221#define SMU_PM_STATUS_120__DATA_MASK 0xffffffff 3222#define SMU_PM_STATUS_120__DATA__SHIFT 0x0 3223#define SMU_PM_STATUS_121__DATA_MASK 0xffffffff 3224#define SMU_PM_STATUS_121__DATA__SHIFT 0x0 3225#define SMU_PM_STATUS_122__DATA_MASK 0xffffffff 3226#define SMU_PM_STATUS_122__DATA__SHIFT 0x0 3227#define SMU_PM_STATUS_123__DATA_MASK 0xffffffff 3228#define SMU_PM_STATUS_123__DATA__SHIFT 0x0 3229#define SMU_PM_STATUS_124__DATA_MASK 0xffffffff 3230#define SMU_PM_STATUS_124__DATA__SHIFT 0x0 3231#define SMU_PM_STATUS_125__DATA_MASK 0xffffffff 3232#define SMU_PM_STATUS_125__DATA__SHIFT 0x0 3233#define SMU_PM_STATUS_126__DATA_MASK 0xffffffff 3234#define SMU_PM_STATUS_126__DATA__SHIFT 0x0 3235#define SMU_PM_STATUS_127__DATA_MASK 0xffffffff 3236#define SMU_PM_STATUS_127__DATA__SHIFT 0x0 3237#define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1 3238#define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0 3239#define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2 3240#define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1 3241#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4 3242#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2 3243#define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8 3244#define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3 3245#define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10 3246#define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 3247#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20 3248#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5 3249#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff 3250#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0 3251#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00 3252#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8 3253#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000 3254#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10 3255#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000 3256#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18 3257#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000 3258#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19 3259#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000 3260#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a 3261#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000 3262#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b 3263#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000 3264#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c 3265#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1 3266#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0 3267#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2 3268#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1 3269#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4 3270#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2 3271#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8 3272#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3 3273#define CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK 0x7 3274#define CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT 0x0 3275#define CG_THERMAL_CTRL__THERM_INC_CLK_MASK 0x8 3276#define CG_THERMAL_CTRL__THERM_INC_CLK__SHIFT 0x3 3277#define CG_THERMAL_CTRL__SPARE_MASK 0x3ff0 3278#define CG_THERMAL_CTRL__SPARE__SHIFT 0x4 3279#define CG_THERMAL_CTRL__DIG_THERM_DPM_MASK 0x3fc000 3280#define CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT 0xe 3281#define CG_THERMAL_CTRL__RESERVED_MASK 0x1c00000 3282#define CG_THERMAL_CTRL__RESERVED__SHIFT 0x16 3283#define CG_THERMAL_CTRL__CTF_PAD_POLARITY_MASK 0x2000000 3284#define CG_THERMAL_CTRL__CTF_PAD_POLARITY__SHIFT 0x19 3285#define CG_THERMAL_CTRL__CTF_PAD_EN_MASK 0x4000000 3286#define CG_THERMAL_CTRL__CTF_PAD_EN__SHIFT 0x1a 3287#define CG_THERMAL_STATUS__SPARE_MASK 0x1ff 3288#define CG_THERMAL_STATUS__SPARE__SHIFT 0x0 3289#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x1fe00 3290#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9 3291#define CG_THERMAL_STATUS__THERM_ALERT_MASK 0x20000 3292#define CG_THERMAL_STATUS__THERM_ALERT__SHIFT 0x11 3293#define CG_THERMAL_STATUS__GEN_STATUS_MASK 0x3c0000 3294#define CG_THERMAL_STATUS__GEN_STATUS__SHIFT 0x12 3295#define CG_THERMAL_INT__DIG_THERM_CTF_MASK 0xff 3296#define CG_THERMAL_INT__DIG_THERM_CTF__SHIFT 0x0 3297#define CG_THERMAL_INT__DIG_THERM_INTH_MASK 0xff00 3298#define CG_THERMAL_INT__DIG_THERM_INTH__SHIFT 0x8 3299#define CG_THERMAL_INT__DIG_THERM_INTL_MASK 0xff0000 3300#define CG_THERMAL_INT__DIG_THERM_INTL__SHIFT 0x10 3301#define CG_THERMAL_INT__THERM_INT_MASK_MASK 0xf000000 3302#define CG_THERMAL_INT__THERM_INT_MASK__SHIFT 0x18 3303#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0xf 3304#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0 3305#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0xf0 3306#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4 3307#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x200 3308#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9 3309#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0xff00000 3310#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14 3311#define CG_MULT_THERMAL_CTRL__THM_READY_CLEAR_MASK 0x10000000 3312#define CG_MULT_THERMAL_CTRL__THM_READY_CLEAR__SHIFT 0x1c 3313#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x1ff 3314#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0 3315#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x3fe00 3316#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9 3317#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0xff 3318#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0 3319#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0xff00 3320#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8 3321#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x10000 3322#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10 3323#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x7e0000 3324#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11 3325#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x800000 3326#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17 3327#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xff000000 3328#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18 3329#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0xff 3330#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0 3331#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0xff00 3332#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8 3333#define CG_FDO_CTRL1__M_MASK 0xff0000 3334#define CG_FDO_CTRL1__M__SHIFT 0x10 3335#define CG_FDO_CTRL1__RESERVED_MASK 0x3f000000 3336#define CG_FDO_CTRL1__RESERVED__SHIFT 0x18 3337#define CG_FDO_CTRL1__FDO_PWRDNB_MASK 0x40000000 3338#define CG_FDO_CTRL1__FDO_PWRDNB__SHIFT 0x1e 3339#define CG_FDO_CTRL2__TMIN_MASK 0xff 3340#define CG_FDO_CTRL2__TMIN__SHIFT 0x0 3341#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x700 3342#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8 3343#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x3800 3344#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb 3345#define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x1c000 3346#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe 3347#define CG_FDO_CTRL2__TMAX_MASK 0x1fe0000 3348#define CG_FDO_CTRL2__TMAX__SHIFT 0x11 3349#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xfe000000 3350#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19 3351#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x7 3352#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0 3353#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xfffffff8 3354#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3 3355#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xffffffff 3356#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0 3357#define CC_THM_STRAPS0__TMON0_BGADJ_MASK 0x1fe 3358#define CC_THM_STRAPS0__TMON0_BGADJ__SHIFT 0x1 3359#define CC_THM_STRAPS0__TMON1_BGADJ_MASK 0x1fe00 3360#define CC_THM_STRAPS0__TMON1_BGADJ__SHIFT 0x9 3361#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL_MASK 0x20000 3362#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL__SHIFT 0x11 3363#define CC_THM_STRAPS0__NUM_ACQ_MASK 0x1c0000 3364#define CC_THM_STRAPS0__NUM_ACQ__SHIFT 0x12 3365#define CC_THM_STRAPS0__TMON_CLK_SEL_MASK 0xe00000 3366#define CC_THM_STRAPS0__TMON_CLK_SEL__SHIFT 0x15 3367#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE_MASK 0x1000000 3368#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE__SHIFT 0x18 3369#define CC_THM_STRAPS0__CTF_DISABLE_MASK 0x2000000 3370#define CC_THM_STRAPS0__CTF_DISABLE__SHIFT 0x19 3371#define CC_THM_STRAPS0__TMON0_DISABLE_MASK 0x4000000 3372#define CC_THM_STRAPS0__TMON0_DISABLE__SHIFT 0x1a 3373#define CC_THM_STRAPS0__TMON1_DISABLE_MASK 0x8000000 3374#define CC_THM_STRAPS0__TMON1_DISABLE__SHIFT 0x1b 3375#define CC_THM_STRAPS0__TMON2_DISABLE_MASK 0x10000000 3376#define CC_THM_STRAPS0__TMON2_DISABLE__SHIFT 0x1c 3377#define CC_THM_STRAPS0__TMON3_DISABLE_MASK 0x20000000 3378#define CC_THM_STRAPS0__TMON3_DISABLE__SHIFT 0x1d 3379#define CC_THM_STRAPS0__UNUSED_MASK 0x80000000 3380#define CC_THM_STRAPS0__UNUSED__SHIFT 0x1f 3381#define THM_TMON0_RDIL0_DATA__Z_MASK 0x7ff 3382#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0 3383#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x800 3384#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb 3385#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0xfff000 3386#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc 3387#define THM_TMON0_RDIL1_DATA__Z_MASK 0x7ff 3388#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0 3389#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x800 3390#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb 3391#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0xfff000 3392#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc 3393#define THM_TMON0_RDIL2_DATA__Z_MASK 0x7ff 3394#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0 3395#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x800 3396#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb 3397#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0xfff000 3398#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc 3399#define THM_TMON0_RDIL3_DATA__Z_MASK 0x7ff 3400#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0 3401#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x800 3402#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb 3403#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0xfff000 3404#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc 3405#define THM_TMON0_RDIL4_DATA__Z_MASK 0x7ff 3406#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0 3407#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x800 3408#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb 3409#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0xfff000 3410#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc 3411#define THM_TMON0_RDIL5_DATA__Z_MASK 0x7ff 3412#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0 3413#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x800 3414#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb 3415#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0xfff000 3416#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc 3417#define THM_TMON0_RDIL6_DATA__Z_MASK 0x7ff 3418#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0 3419#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x800 3420#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb 3421#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0xfff000 3422#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc 3423#define THM_TMON0_RDIL7_DATA__Z_MASK 0x7ff 3424#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0 3425#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x800 3426#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb 3427#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0xfff000 3428#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc 3429#define THM_TMON0_RDIL8_DATA__Z_MASK 0x7ff 3430#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0 3431#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x800 3432#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb 3433#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0xfff000 3434#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc 3435#define THM_TMON0_RDIL9_DATA__Z_MASK 0x7ff 3436#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0 3437#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x800 3438#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb 3439#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0xfff000 3440#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc 3441#define THM_TMON0_RDIL10_DATA__Z_MASK 0x7ff 3442#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0 3443#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x800 3444#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb 3445#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0xfff000 3446#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc 3447#define THM_TMON0_RDIL11_DATA__Z_MASK 0x7ff 3448#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0 3449#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x800 3450#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb 3451#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0xfff000 3452#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc 3453#define THM_TMON0_RDIL12_DATA__Z_MASK 0x7ff 3454#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0 3455#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x800 3456#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb 3457#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0xfff000 3458#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc 3459#define THM_TMON0_RDIL13_DATA__Z_MASK 0x7ff 3460#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0 3461#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x800 3462#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb 3463#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0xfff000 3464#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc 3465#define THM_TMON0_RDIL14_DATA__Z_MASK 0x7ff 3466#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0 3467#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x800 3468#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb 3469#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0xfff000 3470#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc 3471#define THM_TMON0_RDIL15_DATA__Z_MASK 0x7ff 3472#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0 3473#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x800 3474#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb 3475#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0xfff000 3476#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc 3477#define THM_TMON0_RDIR0_DATA__Z_MASK 0x7ff 3478#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0 3479#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x800 3480#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb 3481#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0xfff000 3482#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc 3483#define THM_TMON0_RDIR1_DATA__Z_MASK 0x7ff 3484#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0 3485#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x800 3486#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb 3487#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0xfff000 3488#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc 3489#define THM_TMON0_RDIR2_DATA__Z_MASK 0x7ff 3490#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0 3491#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x800 3492#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb 3493#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0xfff000 3494#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc 3495#define THM_TMON0_RDIR3_DATA__Z_MASK 0x7ff 3496#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0 3497#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x800 3498#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb 3499#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0xfff000 3500#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc 3501#define THM_TMON0_RDIR4_DATA__Z_MASK 0x7ff 3502#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0 3503#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x800 3504#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb 3505#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0xfff000 3506#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc 3507#define THM_TMON0_RDIR5_DATA__Z_MASK 0x7ff 3508#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0 3509#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x800 3510#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb 3511#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0xfff000 3512#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc 3513#define THM_TMON0_RDIR6_DATA__Z_MASK 0x7ff 3514#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0 3515#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x800 3516#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb 3517#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0xfff000 3518#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc 3519#define THM_TMON0_RDIR7_DATA__Z_MASK 0x7ff 3520#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0 3521#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x800 3522#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb 3523#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0xfff000 3524#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc 3525#define THM_TMON0_RDIR8_DATA__Z_MASK 0x7ff 3526#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0 3527#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x800 3528#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb 3529#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0xfff000 3530#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc 3531#define THM_TMON0_RDIR9_DATA__Z_MASK 0x7ff 3532#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0 3533#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x800 3534#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb 3535#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0xfff000 3536#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc 3537#define THM_TMON0_RDIR10_DATA__Z_MASK 0x7ff 3538#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0 3539#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x800 3540#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb 3541#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0xfff000 3542#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc 3543#define THM_TMON0_RDIR11_DATA__Z_MASK 0x7ff 3544#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0 3545#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x800 3546#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb 3547#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0xfff000 3548#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc 3549#define THM_TMON0_RDIR12_DATA__Z_MASK 0x7ff 3550#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0 3551#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x800 3552#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb 3553#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0xfff000 3554#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc 3555#define THM_TMON0_RDIR13_DATA__Z_MASK 0x7ff 3556#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0 3557#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x800 3558#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb 3559#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0xfff000 3560#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc 3561#define THM_TMON0_RDIR14_DATA__Z_MASK 0x7ff 3562#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0 3563#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x800 3564#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb 3565#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0xfff000 3566#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc 3567#define THM_TMON0_RDIR15_DATA__Z_MASK 0x7ff 3568#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0 3569#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x800 3570#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb 3571#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0xfff000 3572#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc 3573#define THM_TMON0_INT_DATA__Z_MASK 0x7ff 3574#define THM_TMON0_INT_DATA__Z__SHIFT 0x0 3575#define THM_TMON0_INT_DATA__VALID_MASK 0x800 3576#define THM_TMON0_INT_DATA__VALID__SHIFT 0xb 3577#define THM_TMON0_INT_DATA__TEMP_MASK 0xfff000 3578#define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc 3579#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x1f 3580#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x0 3581#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0xffe0 3582#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x5 3583#define THM_TMON0_STATUS__CURRENT_RDI_MASK 0x1f 3584#define THM_TMON0_STATUS__CURRENT_RDI__SHIFT 0x0 3585#define THM_TMON0_STATUS__MEAS_DONE_MASK 0x20 3586#define THM_TMON0_STATUS__MEAS_DONE__SHIFT 0x5 3587#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1 3588#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0 3589#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2 3590#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1 3591#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4 3592#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2 3593#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8 3594#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3 3595#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40 3596#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6 3597#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100 3598#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8 3599#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200 3600#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9 3601#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400 3602#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa 3603#define GENERAL_PWRMGT__SPARE11_MASK 0x800 3604#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb 3605#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000 3606#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe 3607#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000 3608#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf 3609#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000 3610#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10 3611#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000 3612#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11 3613#define GENERAL_PWRMGT__SPARE18_MASK 0x40000 3614#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12 3615#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000 3616#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13 3617#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000 3618#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17 3619#define GENERAL_PWRMGT__SPARE27_MASK 0x8000000 3620#define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b 3621#define GENERAL_PWRMGT__SPARE_MASK 0xf0000000 3622#define GENERAL_PWRMGT__SPARE__SHIFT 0x1c 3623#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3 3624#define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0 3625#define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4 3626#define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2 3627#define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8 3628#define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3 3629#define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10 3630#define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4 3631#define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0 3632#define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5 3633#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x1 3634#define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x0 3635#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10 3636#define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4 3637#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20 3638#define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5 3639#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x4000 3640#define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0xe 3641#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP_MASK 0x8000 3642#define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP__SHIFT 0xf 3643#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER_MASK 0x1f0000 3644#define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER__SHIFT 0x10 3645#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK 0x200000 3646#define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN__SHIFT 0x15 3647#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE_MASK 0xf 3648#define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE__SHIFT 0x0 3649#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_MASK 0xf0 3650#define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4 3651#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00 3652#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8 3653#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000 3654#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc 3655#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000 3656#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10 3657#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000 3658#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15 3659#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000 3660#define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a 3661#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000 3662#define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d 3663#define PWR_PCC_CONTROL__PCC_POLARITY_MASK 0x1 3664#define PWR_PCC_CONTROL__PCC_POLARITY__SHIFT 0x0 3665#define PWR_PCC_GPIO_SELECT__GPIO_MASK 0xffffffff 3666#define PWR_PCC_GPIO_SELECT__GPIO__SHIFT 0x0 3667#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 3668#define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 3669#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 3670#define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 3671#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 3672#define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 3673#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 3674#define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 3675#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 3676#define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 3677#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 3678#define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 3679#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 3680#define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 3681#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 3682#define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 3683#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 3684#define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 3685#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 3686#define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 3687#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 3688#define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 3689#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 3690#define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 3691#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 3692#define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc 3693#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 3694#define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 3695#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 3696#define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 3697#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 3698#define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 3699#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 3700#define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 3701#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 3702#define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 3703#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 3704#define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 3705#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 3706#define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 3707#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 3708#define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 3709#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 3710#define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 3711#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 3712#define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 3713#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 3714#define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 3715#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 3716#define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 3717#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 3718#define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 3719#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 3720#define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 3721#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 3722#define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 3723#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 3724#define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 3725#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 3726#define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 3727#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 3728#define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 3729#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 3730#define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 3731#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 3732#define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 3733#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 3734#define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 3735#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 3736#define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 3737#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 3738#define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 3739#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 3740#define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 3741#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 3742#define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 3743#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 3744#define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 3745#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 3746#define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 3747#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 3748#define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 3749#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 3750#define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 3751#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 3752#define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 3753#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 3754#define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc 3755#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 3756#define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 3757#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 3758#define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 3759#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 3760#define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 3761#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 3762#define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 3763#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 3764#define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 3765#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 3766#define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 3767#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 3768#define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 3769#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 3770#define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 3771#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 3772#define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 3773#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 3774#define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 3775#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 3776#define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 3777#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 3778#define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 3779#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 3780#define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 3781#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 3782#define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 3783#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 3784#define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 3785#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 3786#define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 3787#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 3788#define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 3789#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 3790#define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 3791#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 3792#define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 3793#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 3794#define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 3795#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 3796#define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 3797#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 3798#define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 3799#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 3800#define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 3801#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 3802#define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 3803#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 3804#define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 3805#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 3806#define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 3807#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 3808#define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 3809#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 3810#define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 3811#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 3812#define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 3813#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 3814#define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 3815#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 3816#define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc 3817#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 3818#define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 3819#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 3820#define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 3821#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 3822#define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 3823#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 3824#define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 3825#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 3826#define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 3827#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 3828#define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 3829#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 3830#define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 3831#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 3832#define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 3833#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 3834#define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 3835#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 3836#define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 3837#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 3838#define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 3839#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 3840#define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 3841#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 3842#define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 3843#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 3844#define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 3845#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 3846#define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 3847#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 3848#define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 3849#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 3850#define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 3851#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 3852#define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 3853#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 3854#define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 3855#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 3856#define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 3857#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 3858#define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 3859#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 3860#define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 3861#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 3862#define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 3863#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 3864#define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 3865#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 3866#define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 3867#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 3868#define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 3869#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 3870#define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 3871#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 3872#define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 3873#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 3874#define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 3875#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 3876#define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 3877#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 3878#define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc 3879#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 3880#define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 3881#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 3882#define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 3883#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 3884#define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 3885#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 3886#define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 3887#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 3888#define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 3889#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 3890#define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 3891#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 3892#define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 3893#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 3894#define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 3895#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 3896#define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 3897#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 3898#define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 3899#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 3900#define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 3901#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 3902#define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 3903#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 3904#define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 3905#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 3906#define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 3907#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 3908#define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 3909#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 3910#define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 3911#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 3912#define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 3913#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 3914#define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 3915#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 3916#define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 3917#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 3918#define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 3919#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 3920#define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 3921#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 3922#define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 3923#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 3924#define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 3925#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 3926#define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 3927#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 3928#define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 3929#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 3930#define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 3931#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 3932#define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 3933#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 3934#define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 3935#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 3936#define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 3937#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 3938#define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 3939#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 3940#define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc 3941#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 3942#define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 3943#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 3944#define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 3945#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 3946#define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 3947#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 3948#define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 3949#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 3950#define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 3951#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 3952#define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 3953#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 3954#define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 3955#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 3956#define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 3957#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 3958#define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 3959#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 3960#define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 3961#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 3962#define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 3963#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 3964#define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 3965#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 3966#define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 3967#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 3968#define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 3969#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 3970#define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 3971#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 3972#define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 3973#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 3974#define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 3975#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 3976#define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 3977#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 3978#define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 3979#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 3980#define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 3981#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 3982#define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 3983#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 3984#define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 3985#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 3986#define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 3987#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 3988#define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 3989#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 3990#define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 3991#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 3992#define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 3993#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 3994#define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 3995#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 3996#define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 3997#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 3998#define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 3999#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 4000#define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 4001#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 4002#define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc 4003#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 4004#define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 4005#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 4006#define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 4007#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 4008#define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 4009#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 4010#define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 4011#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 4012#define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 4013#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 4014#define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 4015#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 4016#define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 4017#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 4018#define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 4019#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 4020#define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 4021#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 4022#define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 4023#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 4024#define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 4025#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 4026#define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 4027#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 4028#define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 4029#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 4030#define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 4031#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 4032#define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 4033#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 4034#define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 4035#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 4036#define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 4037#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 4038#define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 4039#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 4040#define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 4041#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 4042#define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 4043#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 4044#define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 4045#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 4046#define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 4047#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 4048#define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 4049#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 4050#define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 4051#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 4052#define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 4053#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 4054#define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 4055#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 4056#define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 4057#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 4058#define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 4059#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 4060#define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 4061#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 4062#define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 4063#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 4064#define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc 4065#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 4066#define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 4067#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 4068#define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 4069#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 4070#define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 4071#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 4072#define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 4073#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 4074#define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 4075#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 4076#define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 4077#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 4078#define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 4079#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 4080#define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 4081#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 4082#define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 4083#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 4084#define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 4085#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 4086#define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 4087#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 4088#define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 4089#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 4090#define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 4091#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 4092#define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 4093#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 4094#define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 4095#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 4096#define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 4097#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 4098#define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 4099#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 4100#define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 4101#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 4102#define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 4103#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 4104#define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 4105#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 4106#define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 4107#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 4108#define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 4109#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 4110#define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 4111#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 4112#define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 4113#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 4114#define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 4115#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 4116#define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 4117#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 4118#define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 4119#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 4120#define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 4121#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 4122#define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 4123#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 4124#define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 4125#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 4126#define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc 4127#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 4128#define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 4129#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 4130#define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 4131#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 4132#define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 4133#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 4134#define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 4135#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 4136#define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 4137#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 4138#define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 4139#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 4140#define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 4141#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 4142#define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 4143#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 4144#define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 4145#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 4146#define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 4147#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 4148#define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 4149#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 4150#define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 4151#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 4152#define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 4153#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 4154#define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 4155#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 4156#define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 4157#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 4158#define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 4159#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 4160#define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 4161#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 4162#define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 4163#define PLL_TEST_CNTL__TST_SRC_SEL_MASK 0xf 4164#define PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0 4165#define PLL_TEST_CNTL__TST_REF_SEL_MASK 0xf0 4166#define PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x4 4167#define PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x7f00 4168#define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8 4169#define PLL_TEST_CNTL__TST_RESET_MASK 0x8000 4170#define PLL_TEST_CNTL__TST_RESET__SHIFT 0xf 4171#define PLL_TEST_CNTL__TEST_COUNT_MASK 0xfffe0000 4172#define PLL_TEST_CNTL__TEST_COUNT__SHIFT 0x11 4173#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff 4174#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0 4175#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000 4176#define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10 4177#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK 0x3 4178#define CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT 0x0 4179#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x3fff0 4180#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x4 4181#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x700000 4182#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x14 4183#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK 0x3000000 4184#define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT 0x18 4185#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE_MASK 0x10000000 4186#define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE__SHIFT 0x1c 4187#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION_MASK 0xffffffff 4188#define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION__SHIFT 0x0 4189#define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f 4190#define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0 4191#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80 4192#define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7 4193#define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 4194#define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 4195#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 4196#define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 4197#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 4198#define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 4199#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000 4200#define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10 4201#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000 4202#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11 4203#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000 4204#define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12 4205#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000 4206#define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13 4207#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000 4208#define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14 4209#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000 4210#define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15 4211#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000 4212#define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16 4213#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000 4214#define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17 4215#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000 4216#define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18 4217#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000 4218#define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19 4219#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000 4220#define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a 4221#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000 4222#define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b 4223#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000 4224#define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c 4225#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK_MASK 0x20000000 4226#define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK__SHIFT 0x1d 4227#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000 4228#define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e 4229#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 4230#define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f 4231#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1 4232#define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0 4233#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2 4234#define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1 4235#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4 4236#define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2 4237#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8 4238#define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3 4239#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10 4240#define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4 4241#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40 4242#define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6 4243#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80 4244#define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7 4245#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100 4246#define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8 4247#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200 4248#define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9 4249#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400 4250#define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa 4251#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK_MASK 0x800 4252#define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK__SHIFT 0xb 4253#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK_MASK 0x1000 4254#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK__SHIFT 0xc 4255#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK_MASK 0x2000 4256#define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK__SHIFT 0xd 4257#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x4000 4258#define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0xe 4259#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID_MASK 0xe00000 4260#define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID__SHIFT 0x15 4261#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000 4262#define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18 4263#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1 4264#define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0 4265#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2 4266#define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1 4267#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4 4268#define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2 4269#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8 4270#define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3 4271#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10 4272#define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4 4273#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20 4274#define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5 4275#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40 4276#define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6 4277#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80 4278#define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7 4279#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100 4280#define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8 4281#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200 4282#define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9 4283#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400 4284#define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa 4285#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800 4286#define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb 4287#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000 4288#define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc 4289#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000 4290#define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd 4291#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000 4292#define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe 4293#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000 4294#define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf 4295#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7 4296#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0 4297#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38 4298#define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3 4299#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000 4300#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10 4301#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000 4302#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11 4303#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000 4304#define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14 4305#define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 4306#define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 4307#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 4308#define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 4309#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 4310#define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 4311#define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000 4312#define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10 4313#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 4314#define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f 4315#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1 4316#define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0 4317#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2 4318#define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1 4319#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4 4320#define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2 4321#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8 4322#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3 4323#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10 4324#define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4 4325#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20 4326#define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5 4327#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40 4328#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6 4329#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80 4330#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7 4331#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100 4332#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8 4333#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200 4334#define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9 4335#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400 4336#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa 4337#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800 4338#define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb 4339#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000 4340#define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc 4341#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000 4342#define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd 4343#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000 4344#define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe 4345#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000 4346#define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf 4347#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000 4348#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10 4349#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000 4350#define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11 4351#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000 4352#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12 4353#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000 4354#define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13 4355#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000 4356#define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14 4357#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x200000 4358#define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0x15 4359#define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xffc00000 4360#define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x16 4361#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf 4362#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0 4363#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0 4364#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4 4365#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00 4366#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8 4367#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000 4368#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc 4369#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000 4370#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10 4371#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000 4372#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14 4373#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000 4374#define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18 4375#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000 4376#define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c 4377#define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff 4378#define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0 4379#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000 4380#define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10 4381#define SCLK_MIN_DIV__FRACV_MASK 0xfff 4382#define SCLK_MIN_DIV__FRACV__SHIFT 0x0 4383#define SCLK_MIN_DIV__INTV_MASK 0x7f000 4384#define SCLK_MIN_DIV__INTV__SHIFT 0xc 4385#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff 4386#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 4387#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 4388#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 4389#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 4390#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a 4391#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 4392#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 4393#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 4394#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c 4395#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 4396#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4397#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_MASK 0x40000000 4398#define PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT__SHIFT 0x1e 4399#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff 4400#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 4401#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 4402#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 4403#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 4404#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a 4405#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 4406#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 4407#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 4408#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c 4409#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 4410#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4411#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_MASK 0x40000000 4412#define PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT__SHIFT 0x1e 4413#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff 4414#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 4415#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 4416#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 4417#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 4418#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a 4419#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 4420#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 4421#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 4422#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c 4423#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 4424#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4425#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_MASK 0x40000000 4426#define PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT__SHIFT 0x1e 4427#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff 4428#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 4429#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 4430#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 4431#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 4432#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a 4433#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 4434#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 4435#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 4436#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c 4437#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 4438#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4439#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_MASK 0x40000000 4440#define PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT__SHIFT 0x1e 4441#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff 4442#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 4443#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 4444#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 4445#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 4446#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a 4447#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 4448#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 4449#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 4450#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c 4451#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 4452#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4453#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_MASK 0x40000000 4454#define PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT__SHIFT 0x1e 4455#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff 4456#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 4457#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 4458#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 4459#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 4460#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a 4461#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 4462#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 4463#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 4464#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c 4465#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 4466#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4467#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_MASK 0x40000000 4468#define PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT__SHIFT 0x1e 4469#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff 4470#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 4471#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 4472#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 4473#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 4474#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a 4475#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 4476#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 4477#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 4478#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c 4479#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 4480#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4481#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_MASK 0x40000000 4482#define PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT__SHIFT 0x1e 4483#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff 4484#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 4485#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 4486#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 4487#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 4488#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a 4489#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 4490#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 4491#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 4492#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c 4493#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 4494#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4495#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_MASK 0x40000000 4496#define PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT__SHIFT 0x1e 4497#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff 4498#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 4499#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 4500#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 4501#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 4502#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a 4503#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 4504#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 4505#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 4506#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c 4507#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 4508#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4509#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_MASK 0x40000000 4510#define PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT__SHIFT 0x1e 4511#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff 4512#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 4513#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 4514#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 4515#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 4516#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a 4517#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 4518#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 4519#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 4520#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c 4521#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 4522#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4523#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_MASK 0x40000000 4524#define PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT__SHIFT 0x1e 4525#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff 4526#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 4527#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 4528#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 4529#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 4530#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a 4531#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 4532#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 4533#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 4534#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c 4535#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 4536#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4537#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_MASK 0x40000000 4538#define PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT__SHIFT 0x1e 4539#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff 4540#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 4541#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 4542#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 4543#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 4544#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a 4545#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 4546#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 4547#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 4548#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c 4549#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 4550#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4551#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_MASK 0x40000000 4552#define PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT__SHIFT 0x1e 4553#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff 4554#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 4555#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 4556#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 4557#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 4558#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a 4559#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 4560#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 4561#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 4562#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c 4563#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 4564#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4565#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_MASK 0x40000000 4566#define PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT__SHIFT 0x1e 4567#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff 4568#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 4569#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 4570#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 4571#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 4572#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a 4573#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 4574#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 4575#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 4576#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c 4577#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 4578#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4579#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_MASK 0x40000000 4580#define PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT__SHIFT 0x1e 4581#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff 4582#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 4583#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 4584#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 4585#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 4586#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a 4587#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 4588#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 4589#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 4590#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c 4591#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 4592#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4593#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_MASK 0x40000000 4594#define PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT__SHIFT 0x1e 4595#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff 4596#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 4597#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 4598#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 4599#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 4600#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a 4601#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 4602#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 4603#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 4604#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c 4605#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 4606#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d 4607#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_MASK 0x40000000 4608#define PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT__SHIFT 0x1e 4609#define PWR_DISP_TIMER_CONTROL2__DISP_TIMER_PULSE_WIDTH_MASK 0x3ff 4610#define PWR_DISP_TIMER_CONTROL2__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0 4611#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_MASK 0xffff 4612#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD__SHIFT 0x0 4613#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT_MASK 0xf0000 4614#define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT__SHIFT 0x10 4615#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN_MASK 0x1 4616#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN__SHIFT 0x0 4617#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT_MASK 0x2 4618#define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT__SHIFT 0x1 4619#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT_MASK 0x4 4620#define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT__SHIFT 0x2 4621#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE_MASK 0x8 4622#define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE__SHIFT 0x3 4623#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ_MASK 0x1 4624#define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ__SHIFT 0x0 4625#define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1 4626#define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0 4627#define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe 4628#define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1 4629#define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000 4630#define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11 4631#define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000 4632#define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16 4633#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff 4634#define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0 4635#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff 4636#define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0 4637#define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1 4638#define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0 4639#define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe 4640#define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1 4641#define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000 4642#define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11 4643#define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000 4644#define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16 4645#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff 4646#define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0 4647#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff 4648#define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0 4649#define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1 4650#define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0 4651#define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe 4652#define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1 4653#define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000 4654#define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11 4655#define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000 4656#define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16 4657#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff 4658#define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0 4659#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff 4660#define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0 4661#define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1 4662#define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0 4663#define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe 4664#define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1 4665#define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000 4666#define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11 4667#define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000 4668#define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16 4669#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff 4670#define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0 4671#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff 4672#define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0 4673#define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1 4674#define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0 4675#define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe 4676#define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1 4677#define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000 4678#define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11 4679#define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000 4680#define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16 4681#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff 4682#define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0 4683#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff 4684#define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0 4685#define ROM_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 4686#define ROM_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 4687#define ROM_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 4688#define ROM_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 4689#define ROM_CNTL__SCK_OVERWRITE_MASK 0x2 4690#define ROM_CNTL__SCK_OVERWRITE__SHIFT 0x1 4691#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x4 4692#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x2 4693#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME_MASK 0xff00 4694#define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME__SHIFT 0x8 4695#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME_MASK 0xff0000 4696#define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME__SHIFT 0x10 4697#define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0xf000000 4698#define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18 4699#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK_MASK 0xf0000000 4700#define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK__SHIFT 0x1c 4701#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0xffffff 4702#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0 4703#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x1000000 4704#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x18 4705#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x2000000 4706#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19 4707#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0xc000000 4708#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a 4709#define ROM_STATUS__ROM_BUSY_MASK 0x1 4710#define ROM_STATUS__ROM_BUSY__SHIFT 0x0 4711#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0xf 4712#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0 4713#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0 4714#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 4715#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000 4716#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e 4717#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000 4718#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f 4719#define ROM_INDEX__ROM_INDEX_MASK 0xffffff 4720#define ROM_INDEX__ROM_INDEX__SHIFT 0x0 4721#define ROM_DATA__ROM_DATA_MASK 0xffffffff 4722#define ROM_DATA__ROM_DATA__SHIFT 0x0 4723#define ROM_START__ROM_START_MASK 0xffffff 4724#define ROM_START__ROM_START__SHIFT 0x0 4725#define ROM_SW_CNTL__DATA_SIZE_MASK 0xffff 4726#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0 4727#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x30000 4728#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10 4729#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x40000 4730#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12 4731#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x1 4732#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0 4733#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0xff 4734#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0 4735#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xffffff00 4736#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8 4737#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xffffffff 4738#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0 4739#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xffffffff 4740#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0 4741#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xffffffff 4742#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0 4743#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xffffffff 4744#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0 4745#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xffffffff 4746#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0 4747#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xffffffff 4748#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0 4749#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xffffffff 4750#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0 4751#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xffffffff 4752#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0 4753#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xffffffff 4754#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0 4755#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xffffffff 4756#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0 4757#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xffffffff 4758#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0 4759#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xffffffff 4760#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0 4761#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xffffffff 4762#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0 4763#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xffffffff 4764#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0 4765#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xffffffff 4766#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0 4767#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xffffffff 4768#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0 4769#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xffffffff 4770#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0 4771#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xffffffff 4772#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0 4773#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xffffffff 4774#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0 4775#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xffffffff 4776#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0 4777#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xffffffff 4778#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0 4779#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xffffffff 4780#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0 4781#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xffffffff 4782#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0 4783#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xffffffff 4784#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0 4785#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xffffffff 4786#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0 4787#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xffffffff 4788#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0 4789#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xffffffff 4790#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0 4791#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xffffffff 4792#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0 4793#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xffffffff 4794#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0 4795#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xffffffff 4796#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0 4797#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xffffffff 4798#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0 4799#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xffffffff 4800#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0 4801#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xffffffff 4802#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0 4803#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xffffffff 4804#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0 4805#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xffffffff 4806#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0 4807#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xffffffff 4808#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0 4809#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xffffffff 4810#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0 4811#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xffffffff 4812#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0 4813#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xffffffff 4814#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0 4815#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xffffffff 4816#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0 4817#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xffffffff 4818#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0 4819#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xffffffff 4820#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0 4821#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xffffffff 4822#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0 4823#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xffffffff 4824#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0 4825#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xffffffff 4826#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0 4827#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xffffffff 4828#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0 4829#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xffffffff 4830#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0 4831#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xffffffff 4832#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0 4833#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xffffffff 4834#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0 4835#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xffffffff 4836#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0 4837#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xffffffff 4838#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0 4839#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xffffffff 4840#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0 4841#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xffffffff 4842#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0 4843#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xffffffff 4844#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0 4845#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xffffffff 4846#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0 4847#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xffffffff 4848#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0 4849#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xffffffff 4850#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0 4851#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xffffffff 4852#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0 4853#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xffffffff 4854#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0 4855#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xffffffff 4856#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0 4857#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xffffffff 4858#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0 4859#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xffffffff 4860#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0 4861#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xffffffff 4862#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0 4863#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff 4864#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0 4865#define CURRENT_PG_STATUS__VCE_PG_STATUS_MASK 0x00000002 4866#define CURRENT_PG_STATUS__UVD_PG_STATUS_MASK 0x00000004 4867 4868#endif /* SMU_7_1_1_SH_MASK_H */ 4869