1/* $NetBSD: sdma6_4_2_2_offset.h,v 1.2 2021/12/18 23:45:23 riastradh Exp $ */ 2 3/* 4 * Copyright (C) 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#ifndef _sdma6_4_2_2_OFFSET_HEADER 24#define _sdma6_4_2_2_OFFSET_HEADER 25 26 27 28// addressBlock: sdma6_sdma6dec 29// base address: 0x7c000 30#define mmSDMA6_UCODE_ADDR 0x0000 31#define mmSDMA6_UCODE_ADDR_BASE_IDX 1 32#define mmSDMA6_UCODE_DATA 0x0001 33#define mmSDMA6_UCODE_DATA_BASE_IDX 1 34#define mmSDMA6_VM_CNTL 0x0004 35#define mmSDMA6_VM_CNTL_BASE_IDX 1 36#define mmSDMA6_VM_CTX_LO 0x0005 37#define mmSDMA6_VM_CTX_LO_BASE_IDX 1 38#define mmSDMA6_VM_CTX_HI 0x0006 39#define mmSDMA6_VM_CTX_HI_BASE_IDX 1 40#define mmSDMA6_ACTIVE_FCN_ID 0x0007 41#define mmSDMA6_ACTIVE_FCN_ID_BASE_IDX 1 42#define mmSDMA6_VM_CTX_CNTL 0x0008 43#define mmSDMA6_VM_CTX_CNTL_BASE_IDX 1 44#define mmSDMA6_VIRT_RESET_REQ 0x0009 45#define mmSDMA6_VIRT_RESET_REQ_BASE_IDX 1 46#define mmSDMA6_VF_ENABLE 0x000a 47#define mmSDMA6_VF_ENABLE_BASE_IDX 1 48#define mmSDMA6_CONTEXT_REG_TYPE0 0x000b 49#define mmSDMA6_CONTEXT_REG_TYPE0_BASE_IDX 1 50#define mmSDMA6_CONTEXT_REG_TYPE1 0x000c 51#define mmSDMA6_CONTEXT_REG_TYPE1_BASE_IDX 1 52#define mmSDMA6_CONTEXT_REG_TYPE2 0x000d 53#define mmSDMA6_CONTEXT_REG_TYPE2_BASE_IDX 1 54#define mmSDMA6_CONTEXT_REG_TYPE3 0x000e 55#define mmSDMA6_CONTEXT_REG_TYPE3_BASE_IDX 1 56#define mmSDMA6_PUB_REG_TYPE0 0x000f 57#define mmSDMA6_PUB_REG_TYPE0_BASE_IDX 1 58#define mmSDMA6_PUB_REG_TYPE1 0x0010 59#define mmSDMA6_PUB_REG_TYPE1_BASE_IDX 1 60#define mmSDMA6_PUB_REG_TYPE2 0x0011 61#define mmSDMA6_PUB_REG_TYPE2_BASE_IDX 1 62#define mmSDMA6_PUB_REG_TYPE3 0x0012 63#define mmSDMA6_PUB_REG_TYPE3_BASE_IDX 1 64#define mmSDMA6_MMHUB_CNTL 0x0013 65#define mmSDMA6_MMHUB_CNTL_BASE_IDX 1 66#define mmSDMA6_CONTEXT_GROUP_BOUNDARY 0x0019 67#define mmSDMA6_CONTEXT_GROUP_BOUNDARY_BASE_IDX 1 68#define mmSDMA6_POWER_CNTL 0x001a 69#define mmSDMA6_POWER_CNTL_BASE_IDX 1 70#define mmSDMA6_CLK_CTRL 0x001b 71#define mmSDMA6_CLK_CTRL_BASE_IDX 1 72#define mmSDMA6_CNTL 0x001c 73#define mmSDMA6_CNTL_BASE_IDX 1 74#define mmSDMA6_CHICKEN_BITS 0x001d 75#define mmSDMA6_CHICKEN_BITS_BASE_IDX 1 76#define mmSDMA6_GB_ADDR_CONFIG 0x001e 77#define mmSDMA6_GB_ADDR_CONFIG_BASE_IDX 1 78#define mmSDMA6_GB_ADDR_CONFIG_READ 0x001f 79#define mmSDMA6_GB_ADDR_CONFIG_READ_BASE_IDX 1 80#define mmSDMA6_RB_RPTR_FETCH_HI 0x0020 81#define mmSDMA6_RB_RPTR_FETCH_HI_BASE_IDX 1 82#define mmSDMA6_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 83#define mmSDMA6_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 1 84#define mmSDMA6_RB_RPTR_FETCH 0x0022 85#define mmSDMA6_RB_RPTR_FETCH_BASE_IDX 1 86#define mmSDMA6_IB_OFFSET_FETCH 0x0023 87#define mmSDMA6_IB_OFFSET_FETCH_BASE_IDX 1 88#define mmSDMA6_PROGRAM 0x0024 89#define mmSDMA6_PROGRAM_BASE_IDX 1 90#define mmSDMA6_STATUS_REG 0x0025 91#define mmSDMA6_STATUS_REG_BASE_IDX 1 92#define mmSDMA6_STATUS1_REG 0x0026 93#define mmSDMA6_STATUS1_REG_BASE_IDX 1 94#define mmSDMA6_RD_BURST_CNTL 0x0027 95#define mmSDMA6_RD_BURST_CNTL_BASE_IDX 1 96#define mmSDMA6_HBM_PAGE_CONFIG 0x0028 97#define mmSDMA6_HBM_PAGE_CONFIG_BASE_IDX 1 98#define mmSDMA6_UCODE_CHECKSUM 0x0029 99#define mmSDMA6_UCODE_CHECKSUM_BASE_IDX 1 100#define mmSDMA6_F32_CNTL 0x002a 101#define mmSDMA6_F32_CNTL_BASE_IDX 1 102#define mmSDMA6_FREEZE 0x002b 103#define mmSDMA6_FREEZE_BASE_IDX 1 104#define mmSDMA6_PHASE0_QUANTUM 0x002c 105#define mmSDMA6_PHASE0_QUANTUM_BASE_IDX 1 106#define mmSDMA6_PHASE1_QUANTUM 0x002d 107#define mmSDMA6_PHASE1_QUANTUM_BASE_IDX 1 108#define mmSDMA6_EDC_CONFIG 0x0032 109#define mmSDMA6_EDC_CONFIG_BASE_IDX 1 110#define mmSDMA6_BA_THRESHOLD 0x0033 111#define mmSDMA6_BA_THRESHOLD_BASE_IDX 1 112#define mmSDMA6_ID 0x0034 113#define mmSDMA6_ID_BASE_IDX 1 114#define mmSDMA6_VERSION 0x0035 115#define mmSDMA6_VERSION_BASE_IDX 1 116#define mmSDMA6_EDC_COUNTER 0x0036 117#define mmSDMA6_EDC_COUNTER_BASE_IDX 1 118#define mmSDMA6_EDC_COUNTER_CLEAR 0x0037 119#define mmSDMA6_EDC_COUNTER_CLEAR_BASE_IDX 1 120#define mmSDMA6_STATUS2_REG 0x0038 121#define mmSDMA6_STATUS2_REG_BASE_IDX 1 122#define mmSDMA6_ATOMIC_CNTL 0x0039 123#define mmSDMA6_ATOMIC_CNTL_BASE_IDX 1 124#define mmSDMA6_ATOMIC_PREOP_LO 0x003a 125#define mmSDMA6_ATOMIC_PREOP_LO_BASE_IDX 1 126#define mmSDMA6_ATOMIC_PREOP_HI 0x003b 127#define mmSDMA6_ATOMIC_PREOP_HI_BASE_IDX 1 128#define mmSDMA6_UTCL1_CNTL 0x003c 129#define mmSDMA6_UTCL1_CNTL_BASE_IDX 1 130#define mmSDMA6_UTCL1_WATERMK 0x003d 131#define mmSDMA6_UTCL1_WATERMK_BASE_IDX 1 132#define mmSDMA6_UTCL1_RD_STATUS 0x003e 133#define mmSDMA6_UTCL1_RD_STATUS_BASE_IDX 1 134#define mmSDMA6_UTCL1_WR_STATUS 0x003f 135#define mmSDMA6_UTCL1_WR_STATUS_BASE_IDX 1 136#define mmSDMA6_UTCL1_INV0 0x0040 137#define mmSDMA6_UTCL1_INV0_BASE_IDX 1 138#define mmSDMA6_UTCL1_INV1 0x0041 139#define mmSDMA6_UTCL1_INV1_BASE_IDX 1 140#define mmSDMA6_UTCL1_INV2 0x0042 141#define mmSDMA6_UTCL1_INV2_BASE_IDX 1 142#define mmSDMA6_UTCL1_RD_XNACK0 0x0043 143#define mmSDMA6_UTCL1_RD_XNACK0_BASE_IDX 1 144#define mmSDMA6_UTCL1_RD_XNACK1 0x0044 145#define mmSDMA6_UTCL1_RD_XNACK1_BASE_IDX 1 146#define mmSDMA6_UTCL1_WR_XNACK0 0x0045 147#define mmSDMA6_UTCL1_WR_XNACK0_BASE_IDX 1 148#define mmSDMA6_UTCL1_WR_XNACK1 0x0046 149#define mmSDMA6_UTCL1_WR_XNACK1_BASE_IDX 1 150#define mmSDMA6_UTCL1_TIMEOUT 0x0047 151#define mmSDMA6_UTCL1_TIMEOUT_BASE_IDX 1 152#define mmSDMA6_UTCL1_PAGE 0x0048 153#define mmSDMA6_UTCL1_PAGE_BASE_IDX 1 154#define mmSDMA6_POWER_CNTL_IDLE 0x0049 155#define mmSDMA6_POWER_CNTL_IDLE_BASE_IDX 1 156#define mmSDMA6_RELAX_ORDERING_LUT 0x004a 157#define mmSDMA6_RELAX_ORDERING_LUT_BASE_IDX 1 158#define mmSDMA6_CHICKEN_BITS_2 0x004b 159#define mmSDMA6_CHICKEN_BITS_2_BASE_IDX 1 160#define mmSDMA6_STATUS3_REG 0x004c 161#define mmSDMA6_STATUS3_REG_BASE_IDX 1 162#define mmSDMA6_PHYSICAL_ADDR_LO 0x004d 163#define mmSDMA6_PHYSICAL_ADDR_LO_BASE_IDX 1 164#define mmSDMA6_PHYSICAL_ADDR_HI 0x004e 165#define mmSDMA6_PHYSICAL_ADDR_HI_BASE_IDX 1 166#define mmSDMA6_PHASE2_QUANTUM 0x004f 167#define mmSDMA6_PHASE2_QUANTUM_BASE_IDX 1 168#define mmSDMA6_ERROR_LOG 0x0050 169#define mmSDMA6_ERROR_LOG_BASE_IDX 1 170#define mmSDMA6_PUB_DUMMY_REG0 0x0051 171#define mmSDMA6_PUB_DUMMY_REG0_BASE_IDX 1 172#define mmSDMA6_PUB_DUMMY_REG1 0x0052 173#define mmSDMA6_PUB_DUMMY_REG1_BASE_IDX 1 174#define mmSDMA6_PUB_DUMMY_REG2 0x0053 175#define mmSDMA6_PUB_DUMMY_REG2_BASE_IDX 1 176#define mmSDMA6_PUB_DUMMY_REG3 0x0054 177#define mmSDMA6_PUB_DUMMY_REG3_BASE_IDX 1 178#define mmSDMA6_F32_COUNTER 0x0055 179#define mmSDMA6_F32_COUNTER_BASE_IDX 1 180#define mmSDMA6_UNBREAKABLE 0x0056 181#define mmSDMA6_UNBREAKABLE_BASE_IDX 1 182#define mmSDMA6_PERFMON_CNTL 0x0057 183#define mmSDMA6_PERFMON_CNTL_BASE_IDX 1 184#define mmSDMA6_PERFCOUNTER0_RESULT 0x0058 185#define mmSDMA6_PERFCOUNTER0_RESULT_BASE_IDX 1 186#define mmSDMA6_PERFCOUNTER1_RESULT 0x0059 187#define mmSDMA6_PERFCOUNTER1_RESULT_BASE_IDX 1 188#define mmSDMA6_PERFCOUNTER_TAG_DELAY_RANGE 0x005a 189#define mmSDMA6_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 1 190#define mmSDMA6_CRD_CNTL 0x005b 191#define mmSDMA6_CRD_CNTL_BASE_IDX 1 192#define mmSDMA6_GPU_IOV_VIOLATION_LOG 0x005d 193#define mmSDMA6_GPU_IOV_VIOLATION_LOG_BASE_IDX 1 194#define mmSDMA6_ULV_CNTL 0x005e 195#define mmSDMA6_ULV_CNTL_BASE_IDX 1 196#define mmSDMA6_EA_DBIT_ADDR_DATA 0x0060 197#define mmSDMA6_EA_DBIT_ADDR_DATA_BASE_IDX 1 198#define mmSDMA6_EA_DBIT_ADDR_INDEX 0x0061 199#define mmSDMA6_EA_DBIT_ADDR_INDEX_BASE_IDX 1 200#define mmSDMA6_GPU_IOV_VIOLATION_LOG2 0x0062 201#define mmSDMA6_GPU_IOV_VIOLATION_LOG2_BASE_IDX 1 202#define mmSDMA6_GFX_RB_CNTL 0x0080 203#define mmSDMA6_GFX_RB_CNTL_BASE_IDX 1 204#define mmSDMA6_GFX_RB_BASE 0x0081 205#define mmSDMA6_GFX_RB_BASE_BASE_IDX 1 206#define mmSDMA6_GFX_RB_BASE_HI 0x0082 207#define mmSDMA6_GFX_RB_BASE_HI_BASE_IDX 1 208#define mmSDMA6_GFX_RB_RPTR 0x0083 209#define mmSDMA6_GFX_RB_RPTR_BASE_IDX 1 210#define mmSDMA6_GFX_RB_RPTR_HI 0x0084 211#define mmSDMA6_GFX_RB_RPTR_HI_BASE_IDX 1 212#define mmSDMA6_GFX_RB_WPTR 0x0085 213#define mmSDMA6_GFX_RB_WPTR_BASE_IDX 1 214#define mmSDMA6_GFX_RB_WPTR_HI 0x0086 215#define mmSDMA6_GFX_RB_WPTR_HI_BASE_IDX 1 216#define mmSDMA6_GFX_RB_WPTR_POLL_CNTL 0x0087 217#define mmSDMA6_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 1 218#define mmSDMA6_GFX_RB_RPTR_ADDR_HI 0x0088 219#define mmSDMA6_GFX_RB_RPTR_ADDR_HI_BASE_IDX 1 220#define mmSDMA6_GFX_RB_RPTR_ADDR_LO 0x0089 221#define mmSDMA6_GFX_RB_RPTR_ADDR_LO_BASE_IDX 1 222#define mmSDMA6_GFX_IB_CNTL 0x008a 223#define mmSDMA6_GFX_IB_CNTL_BASE_IDX 1 224#define mmSDMA6_GFX_IB_RPTR 0x008b 225#define mmSDMA6_GFX_IB_RPTR_BASE_IDX 1 226#define mmSDMA6_GFX_IB_OFFSET 0x008c 227#define mmSDMA6_GFX_IB_OFFSET_BASE_IDX 1 228#define mmSDMA6_GFX_IB_BASE_LO 0x008d 229#define mmSDMA6_GFX_IB_BASE_LO_BASE_IDX 1 230#define mmSDMA6_GFX_IB_BASE_HI 0x008e 231#define mmSDMA6_GFX_IB_BASE_HI_BASE_IDX 1 232#define mmSDMA6_GFX_IB_SIZE 0x008f 233#define mmSDMA6_GFX_IB_SIZE_BASE_IDX 1 234#define mmSDMA6_GFX_SKIP_CNTL 0x0090 235#define mmSDMA6_GFX_SKIP_CNTL_BASE_IDX 1 236#define mmSDMA6_GFX_CONTEXT_STATUS 0x0091 237#define mmSDMA6_GFX_CONTEXT_STATUS_BASE_IDX 1 238#define mmSDMA6_GFX_DOORBELL 0x0092 239#define mmSDMA6_GFX_DOORBELL_BASE_IDX 1 240#define mmSDMA6_GFX_CONTEXT_CNTL 0x0093 241#define mmSDMA6_GFX_CONTEXT_CNTL_BASE_IDX 1 242#define mmSDMA6_GFX_STATUS 0x00a8 243#define mmSDMA6_GFX_STATUS_BASE_IDX 1 244#define mmSDMA6_GFX_DOORBELL_LOG 0x00a9 245#define mmSDMA6_GFX_DOORBELL_LOG_BASE_IDX 1 246#define mmSDMA6_GFX_WATERMARK 0x00aa 247#define mmSDMA6_GFX_WATERMARK_BASE_IDX 1 248#define mmSDMA6_GFX_DOORBELL_OFFSET 0x00ab 249#define mmSDMA6_GFX_DOORBELL_OFFSET_BASE_IDX 1 250#define mmSDMA6_GFX_CSA_ADDR_LO 0x00ac 251#define mmSDMA6_GFX_CSA_ADDR_LO_BASE_IDX 1 252#define mmSDMA6_GFX_CSA_ADDR_HI 0x00ad 253#define mmSDMA6_GFX_CSA_ADDR_HI_BASE_IDX 1 254#define mmSDMA6_GFX_IB_SUB_REMAIN 0x00af 255#define mmSDMA6_GFX_IB_SUB_REMAIN_BASE_IDX 1 256#define mmSDMA6_GFX_PREEMPT 0x00b0 257#define mmSDMA6_GFX_PREEMPT_BASE_IDX 1 258#define mmSDMA6_GFX_DUMMY_REG 0x00b1 259#define mmSDMA6_GFX_DUMMY_REG_BASE_IDX 1 260#define mmSDMA6_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 261#define mmSDMA6_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 262#define mmSDMA6_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 263#define mmSDMA6_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 264#define mmSDMA6_GFX_RB_AQL_CNTL 0x00b4 265#define mmSDMA6_GFX_RB_AQL_CNTL_BASE_IDX 1 266#define mmSDMA6_GFX_MINOR_PTR_UPDATE 0x00b5 267#define mmSDMA6_GFX_MINOR_PTR_UPDATE_BASE_IDX 1 268#define mmSDMA6_GFX_MIDCMD_DATA0 0x00c0 269#define mmSDMA6_GFX_MIDCMD_DATA0_BASE_IDX 1 270#define mmSDMA6_GFX_MIDCMD_DATA1 0x00c1 271#define mmSDMA6_GFX_MIDCMD_DATA1_BASE_IDX 1 272#define mmSDMA6_GFX_MIDCMD_DATA2 0x00c2 273#define mmSDMA6_GFX_MIDCMD_DATA2_BASE_IDX 1 274#define mmSDMA6_GFX_MIDCMD_DATA3 0x00c3 275#define mmSDMA6_GFX_MIDCMD_DATA3_BASE_IDX 1 276#define mmSDMA6_GFX_MIDCMD_DATA4 0x00c4 277#define mmSDMA6_GFX_MIDCMD_DATA4_BASE_IDX 1 278#define mmSDMA6_GFX_MIDCMD_DATA5 0x00c5 279#define mmSDMA6_GFX_MIDCMD_DATA5_BASE_IDX 1 280#define mmSDMA6_GFX_MIDCMD_DATA6 0x00c6 281#define mmSDMA6_GFX_MIDCMD_DATA6_BASE_IDX 1 282#define mmSDMA6_GFX_MIDCMD_DATA7 0x00c7 283#define mmSDMA6_GFX_MIDCMD_DATA7_BASE_IDX 1 284#define mmSDMA6_GFX_MIDCMD_DATA8 0x00c8 285#define mmSDMA6_GFX_MIDCMD_DATA8_BASE_IDX 1 286#define mmSDMA6_GFX_MIDCMD_CNTL 0x00c9 287#define mmSDMA6_GFX_MIDCMD_CNTL_BASE_IDX 1 288#define mmSDMA6_PAGE_RB_CNTL 0x00d8 289#define mmSDMA6_PAGE_RB_CNTL_BASE_IDX 1 290#define mmSDMA6_PAGE_RB_BASE 0x00d9 291#define mmSDMA6_PAGE_RB_BASE_BASE_IDX 1 292#define mmSDMA6_PAGE_RB_BASE_HI 0x00da 293#define mmSDMA6_PAGE_RB_BASE_HI_BASE_IDX 1 294#define mmSDMA6_PAGE_RB_RPTR 0x00db 295#define mmSDMA6_PAGE_RB_RPTR_BASE_IDX 1 296#define mmSDMA6_PAGE_RB_RPTR_HI 0x00dc 297#define mmSDMA6_PAGE_RB_RPTR_HI_BASE_IDX 1 298#define mmSDMA6_PAGE_RB_WPTR 0x00dd 299#define mmSDMA6_PAGE_RB_WPTR_BASE_IDX 1 300#define mmSDMA6_PAGE_RB_WPTR_HI 0x00de 301#define mmSDMA6_PAGE_RB_WPTR_HI_BASE_IDX 1 302#define mmSDMA6_PAGE_RB_WPTR_POLL_CNTL 0x00df 303#define mmSDMA6_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 1 304#define mmSDMA6_PAGE_RB_RPTR_ADDR_HI 0x00e0 305#define mmSDMA6_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 1 306#define mmSDMA6_PAGE_RB_RPTR_ADDR_LO 0x00e1 307#define mmSDMA6_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 1 308#define mmSDMA6_PAGE_IB_CNTL 0x00e2 309#define mmSDMA6_PAGE_IB_CNTL_BASE_IDX 1 310#define mmSDMA6_PAGE_IB_RPTR 0x00e3 311#define mmSDMA6_PAGE_IB_RPTR_BASE_IDX 1 312#define mmSDMA6_PAGE_IB_OFFSET 0x00e4 313#define mmSDMA6_PAGE_IB_OFFSET_BASE_IDX 1 314#define mmSDMA6_PAGE_IB_BASE_LO 0x00e5 315#define mmSDMA6_PAGE_IB_BASE_LO_BASE_IDX 1 316#define mmSDMA6_PAGE_IB_BASE_HI 0x00e6 317#define mmSDMA6_PAGE_IB_BASE_HI_BASE_IDX 1 318#define mmSDMA6_PAGE_IB_SIZE 0x00e7 319#define mmSDMA6_PAGE_IB_SIZE_BASE_IDX 1 320#define mmSDMA6_PAGE_SKIP_CNTL 0x00e8 321#define mmSDMA6_PAGE_SKIP_CNTL_BASE_IDX 1 322#define mmSDMA6_PAGE_CONTEXT_STATUS 0x00e9 323#define mmSDMA6_PAGE_CONTEXT_STATUS_BASE_IDX 1 324#define mmSDMA6_PAGE_DOORBELL 0x00ea 325#define mmSDMA6_PAGE_DOORBELL_BASE_IDX 1 326#define mmSDMA6_PAGE_STATUS 0x0100 327#define mmSDMA6_PAGE_STATUS_BASE_IDX 1 328#define mmSDMA6_PAGE_DOORBELL_LOG 0x0101 329#define mmSDMA6_PAGE_DOORBELL_LOG_BASE_IDX 1 330#define mmSDMA6_PAGE_WATERMARK 0x0102 331#define mmSDMA6_PAGE_WATERMARK_BASE_IDX 1 332#define mmSDMA6_PAGE_DOORBELL_OFFSET 0x0103 333#define mmSDMA6_PAGE_DOORBELL_OFFSET_BASE_IDX 1 334#define mmSDMA6_PAGE_CSA_ADDR_LO 0x0104 335#define mmSDMA6_PAGE_CSA_ADDR_LO_BASE_IDX 1 336#define mmSDMA6_PAGE_CSA_ADDR_HI 0x0105 337#define mmSDMA6_PAGE_CSA_ADDR_HI_BASE_IDX 1 338#define mmSDMA6_PAGE_IB_SUB_REMAIN 0x0107 339#define mmSDMA6_PAGE_IB_SUB_REMAIN_BASE_IDX 1 340#define mmSDMA6_PAGE_PREEMPT 0x0108 341#define mmSDMA6_PAGE_PREEMPT_BASE_IDX 1 342#define mmSDMA6_PAGE_DUMMY_REG 0x0109 343#define mmSDMA6_PAGE_DUMMY_REG_BASE_IDX 1 344#define mmSDMA6_PAGE_RB_WPTR_POLL_ADDR_HI 0x010a 345#define mmSDMA6_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 346#define mmSDMA6_PAGE_RB_WPTR_POLL_ADDR_LO 0x010b 347#define mmSDMA6_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 348#define mmSDMA6_PAGE_RB_AQL_CNTL 0x010c 349#define mmSDMA6_PAGE_RB_AQL_CNTL_BASE_IDX 1 350#define mmSDMA6_PAGE_MINOR_PTR_UPDATE 0x010d 351#define mmSDMA6_PAGE_MINOR_PTR_UPDATE_BASE_IDX 1 352#define mmSDMA6_PAGE_MIDCMD_DATA0 0x0118 353#define mmSDMA6_PAGE_MIDCMD_DATA0_BASE_IDX 1 354#define mmSDMA6_PAGE_MIDCMD_DATA1 0x0119 355#define mmSDMA6_PAGE_MIDCMD_DATA1_BASE_IDX 1 356#define mmSDMA6_PAGE_MIDCMD_DATA2 0x011a 357#define mmSDMA6_PAGE_MIDCMD_DATA2_BASE_IDX 1 358#define mmSDMA6_PAGE_MIDCMD_DATA3 0x011b 359#define mmSDMA6_PAGE_MIDCMD_DATA3_BASE_IDX 1 360#define mmSDMA6_PAGE_MIDCMD_DATA4 0x011c 361#define mmSDMA6_PAGE_MIDCMD_DATA4_BASE_IDX 1 362#define mmSDMA6_PAGE_MIDCMD_DATA5 0x011d 363#define mmSDMA6_PAGE_MIDCMD_DATA5_BASE_IDX 1 364#define mmSDMA6_PAGE_MIDCMD_DATA6 0x011e 365#define mmSDMA6_PAGE_MIDCMD_DATA6_BASE_IDX 1 366#define mmSDMA6_PAGE_MIDCMD_DATA7 0x011f 367#define mmSDMA6_PAGE_MIDCMD_DATA7_BASE_IDX 1 368#define mmSDMA6_PAGE_MIDCMD_DATA8 0x0120 369#define mmSDMA6_PAGE_MIDCMD_DATA8_BASE_IDX 1 370#define mmSDMA6_PAGE_MIDCMD_CNTL 0x0121 371#define mmSDMA6_PAGE_MIDCMD_CNTL_BASE_IDX 1 372#define mmSDMA6_RLC0_RB_CNTL 0x0130 373#define mmSDMA6_RLC0_RB_CNTL_BASE_IDX 1 374#define mmSDMA6_RLC0_RB_BASE 0x0131 375#define mmSDMA6_RLC0_RB_BASE_BASE_IDX 1 376#define mmSDMA6_RLC0_RB_BASE_HI 0x0132 377#define mmSDMA6_RLC0_RB_BASE_HI_BASE_IDX 1 378#define mmSDMA6_RLC0_RB_RPTR 0x0133 379#define mmSDMA6_RLC0_RB_RPTR_BASE_IDX 1 380#define mmSDMA6_RLC0_RB_RPTR_HI 0x0134 381#define mmSDMA6_RLC0_RB_RPTR_HI_BASE_IDX 1 382#define mmSDMA6_RLC0_RB_WPTR 0x0135 383#define mmSDMA6_RLC0_RB_WPTR_BASE_IDX 1 384#define mmSDMA6_RLC0_RB_WPTR_HI 0x0136 385#define mmSDMA6_RLC0_RB_WPTR_HI_BASE_IDX 1 386#define mmSDMA6_RLC0_RB_WPTR_POLL_CNTL 0x0137 387#define mmSDMA6_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 1 388#define mmSDMA6_RLC0_RB_RPTR_ADDR_HI 0x0138 389#define mmSDMA6_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 1 390#define mmSDMA6_RLC0_RB_RPTR_ADDR_LO 0x0139 391#define mmSDMA6_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 1 392#define mmSDMA6_RLC0_IB_CNTL 0x013a 393#define mmSDMA6_RLC0_IB_CNTL_BASE_IDX 1 394#define mmSDMA6_RLC0_IB_RPTR 0x013b 395#define mmSDMA6_RLC0_IB_RPTR_BASE_IDX 1 396#define mmSDMA6_RLC0_IB_OFFSET 0x013c 397#define mmSDMA6_RLC0_IB_OFFSET_BASE_IDX 1 398#define mmSDMA6_RLC0_IB_BASE_LO 0x013d 399#define mmSDMA6_RLC0_IB_BASE_LO_BASE_IDX 1 400#define mmSDMA6_RLC0_IB_BASE_HI 0x013e 401#define mmSDMA6_RLC0_IB_BASE_HI_BASE_IDX 1 402#define mmSDMA6_RLC0_IB_SIZE 0x013f 403#define mmSDMA6_RLC0_IB_SIZE_BASE_IDX 1 404#define mmSDMA6_RLC0_SKIP_CNTL 0x0140 405#define mmSDMA6_RLC0_SKIP_CNTL_BASE_IDX 1 406#define mmSDMA6_RLC0_CONTEXT_STATUS 0x0141 407#define mmSDMA6_RLC0_CONTEXT_STATUS_BASE_IDX 1 408#define mmSDMA6_RLC0_DOORBELL 0x0142 409#define mmSDMA6_RLC0_DOORBELL_BASE_IDX 1 410#define mmSDMA6_RLC0_STATUS 0x0158 411#define mmSDMA6_RLC0_STATUS_BASE_IDX 1 412#define mmSDMA6_RLC0_DOORBELL_LOG 0x0159 413#define mmSDMA6_RLC0_DOORBELL_LOG_BASE_IDX 1 414#define mmSDMA6_RLC0_WATERMARK 0x015a 415#define mmSDMA6_RLC0_WATERMARK_BASE_IDX 1 416#define mmSDMA6_RLC0_DOORBELL_OFFSET 0x015b 417#define mmSDMA6_RLC0_DOORBELL_OFFSET_BASE_IDX 1 418#define mmSDMA6_RLC0_CSA_ADDR_LO 0x015c 419#define mmSDMA6_RLC0_CSA_ADDR_LO_BASE_IDX 1 420#define mmSDMA6_RLC0_CSA_ADDR_HI 0x015d 421#define mmSDMA6_RLC0_CSA_ADDR_HI_BASE_IDX 1 422#define mmSDMA6_RLC0_IB_SUB_REMAIN 0x015f 423#define mmSDMA6_RLC0_IB_SUB_REMAIN_BASE_IDX 1 424#define mmSDMA6_RLC0_PREEMPT 0x0160 425#define mmSDMA6_RLC0_PREEMPT_BASE_IDX 1 426#define mmSDMA6_RLC0_DUMMY_REG 0x0161 427#define mmSDMA6_RLC0_DUMMY_REG_BASE_IDX 1 428#define mmSDMA6_RLC0_RB_WPTR_POLL_ADDR_HI 0x0162 429#define mmSDMA6_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 430#define mmSDMA6_RLC0_RB_WPTR_POLL_ADDR_LO 0x0163 431#define mmSDMA6_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 432#define mmSDMA6_RLC0_RB_AQL_CNTL 0x0164 433#define mmSDMA6_RLC0_RB_AQL_CNTL_BASE_IDX 1 434#define mmSDMA6_RLC0_MINOR_PTR_UPDATE 0x0165 435#define mmSDMA6_RLC0_MINOR_PTR_UPDATE_BASE_IDX 1 436#define mmSDMA6_RLC0_MIDCMD_DATA0 0x0170 437#define mmSDMA6_RLC0_MIDCMD_DATA0_BASE_IDX 1 438#define mmSDMA6_RLC0_MIDCMD_DATA1 0x0171 439#define mmSDMA6_RLC0_MIDCMD_DATA1_BASE_IDX 1 440#define mmSDMA6_RLC0_MIDCMD_DATA2 0x0172 441#define mmSDMA6_RLC0_MIDCMD_DATA2_BASE_IDX 1 442#define mmSDMA6_RLC0_MIDCMD_DATA3 0x0173 443#define mmSDMA6_RLC0_MIDCMD_DATA3_BASE_IDX 1 444#define mmSDMA6_RLC0_MIDCMD_DATA4 0x0174 445#define mmSDMA6_RLC0_MIDCMD_DATA4_BASE_IDX 1 446#define mmSDMA6_RLC0_MIDCMD_DATA5 0x0175 447#define mmSDMA6_RLC0_MIDCMD_DATA5_BASE_IDX 1 448#define mmSDMA6_RLC0_MIDCMD_DATA6 0x0176 449#define mmSDMA6_RLC0_MIDCMD_DATA6_BASE_IDX 1 450#define mmSDMA6_RLC0_MIDCMD_DATA7 0x0177 451#define mmSDMA6_RLC0_MIDCMD_DATA7_BASE_IDX 1 452#define mmSDMA6_RLC0_MIDCMD_DATA8 0x0178 453#define mmSDMA6_RLC0_MIDCMD_DATA8_BASE_IDX 1 454#define mmSDMA6_RLC0_MIDCMD_CNTL 0x0179 455#define mmSDMA6_RLC0_MIDCMD_CNTL_BASE_IDX 1 456#define mmSDMA6_RLC1_RB_CNTL 0x0188 457#define mmSDMA6_RLC1_RB_CNTL_BASE_IDX 1 458#define mmSDMA6_RLC1_RB_BASE 0x0189 459#define mmSDMA6_RLC1_RB_BASE_BASE_IDX 1 460#define mmSDMA6_RLC1_RB_BASE_HI 0x018a 461#define mmSDMA6_RLC1_RB_BASE_HI_BASE_IDX 1 462#define mmSDMA6_RLC1_RB_RPTR 0x018b 463#define mmSDMA6_RLC1_RB_RPTR_BASE_IDX 1 464#define mmSDMA6_RLC1_RB_RPTR_HI 0x018c 465#define mmSDMA6_RLC1_RB_RPTR_HI_BASE_IDX 1 466#define mmSDMA6_RLC1_RB_WPTR 0x018d 467#define mmSDMA6_RLC1_RB_WPTR_BASE_IDX 1 468#define mmSDMA6_RLC1_RB_WPTR_HI 0x018e 469#define mmSDMA6_RLC1_RB_WPTR_HI_BASE_IDX 1 470#define mmSDMA6_RLC1_RB_WPTR_POLL_CNTL 0x018f 471#define mmSDMA6_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 1 472#define mmSDMA6_RLC1_RB_RPTR_ADDR_HI 0x0190 473#define mmSDMA6_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 1 474#define mmSDMA6_RLC1_RB_RPTR_ADDR_LO 0x0191 475#define mmSDMA6_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 1 476#define mmSDMA6_RLC1_IB_CNTL 0x0192 477#define mmSDMA6_RLC1_IB_CNTL_BASE_IDX 1 478#define mmSDMA6_RLC1_IB_RPTR 0x0193 479#define mmSDMA6_RLC1_IB_RPTR_BASE_IDX 1 480#define mmSDMA6_RLC1_IB_OFFSET 0x0194 481#define mmSDMA6_RLC1_IB_OFFSET_BASE_IDX 1 482#define mmSDMA6_RLC1_IB_BASE_LO 0x0195 483#define mmSDMA6_RLC1_IB_BASE_LO_BASE_IDX 1 484#define mmSDMA6_RLC1_IB_BASE_HI 0x0196 485#define mmSDMA6_RLC1_IB_BASE_HI_BASE_IDX 1 486#define mmSDMA6_RLC1_IB_SIZE 0x0197 487#define mmSDMA6_RLC1_IB_SIZE_BASE_IDX 1 488#define mmSDMA6_RLC1_SKIP_CNTL 0x0198 489#define mmSDMA6_RLC1_SKIP_CNTL_BASE_IDX 1 490#define mmSDMA6_RLC1_CONTEXT_STATUS 0x0199 491#define mmSDMA6_RLC1_CONTEXT_STATUS_BASE_IDX 1 492#define mmSDMA6_RLC1_DOORBELL 0x019a 493#define mmSDMA6_RLC1_DOORBELL_BASE_IDX 1 494#define mmSDMA6_RLC1_STATUS 0x01b0 495#define mmSDMA6_RLC1_STATUS_BASE_IDX 1 496#define mmSDMA6_RLC1_DOORBELL_LOG 0x01b1 497#define mmSDMA6_RLC1_DOORBELL_LOG_BASE_IDX 1 498#define mmSDMA6_RLC1_WATERMARK 0x01b2 499#define mmSDMA6_RLC1_WATERMARK_BASE_IDX 1 500#define mmSDMA6_RLC1_DOORBELL_OFFSET 0x01b3 501#define mmSDMA6_RLC1_DOORBELL_OFFSET_BASE_IDX 1 502#define mmSDMA6_RLC1_CSA_ADDR_LO 0x01b4 503#define mmSDMA6_RLC1_CSA_ADDR_LO_BASE_IDX 1 504#define mmSDMA6_RLC1_CSA_ADDR_HI 0x01b5 505#define mmSDMA6_RLC1_CSA_ADDR_HI_BASE_IDX 1 506#define mmSDMA6_RLC1_IB_SUB_REMAIN 0x01b7 507#define mmSDMA6_RLC1_IB_SUB_REMAIN_BASE_IDX 1 508#define mmSDMA6_RLC1_PREEMPT 0x01b8 509#define mmSDMA6_RLC1_PREEMPT_BASE_IDX 1 510#define mmSDMA6_RLC1_DUMMY_REG 0x01b9 511#define mmSDMA6_RLC1_DUMMY_REG_BASE_IDX 1 512#define mmSDMA6_RLC1_RB_WPTR_POLL_ADDR_HI 0x01ba 513#define mmSDMA6_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 514#define mmSDMA6_RLC1_RB_WPTR_POLL_ADDR_LO 0x01bb 515#define mmSDMA6_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 516#define mmSDMA6_RLC1_RB_AQL_CNTL 0x01bc 517#define mmSDMA6_RLC1_RB_AQL_CNTL_BASE_IDX 1 518#define mmSDMA6_RLC1_MINOR_PTR_UPDATE 0x01bd 519#define mmSDMA6_RLC1_MINOR_PTR_UPDATE_BASE_IDX 1 520#define mmSDMA6_RLC1_MIDCMD_DATA0 0x01c8 521#define mmSDMA6_RLC1_MIDCMD_DATA0_BASE_IDX 1 522#define mmSDMA6_RLC1_MIDCMD_DATA1 0x01c9 523#define mmSDMA6_RLC1_MIDCMD_DATA1_BASE_IDX 1 524#define mmSDMA6_RLC1_MIDCMD_DATA2 0x01ca 525#define mmSDMA6_RLC1_MIDCMD_DATA2_BASE_IDX 1 526#define mmSDMA6_RLC1_MIDCMD_DATA3 0x01cb 527#define mmSDMA6_RLC1_MIDCMD_DATA3_BASE_IDX 1 528#define mmSDMA6_RLC1_MIDCMD_DATA4 0x01cc 529#define mmSDMA6_RLC1_MIDCMD_DATA4_BASE_IDX 1 530#define mmSDMA6_RLC1_MIDCMD_DATA5 0x01cd 531#define mmSDMA6_RLC1_MIDCMD_DATA5_BASE_IDX 1 532#define mmSDMA6_RLC1_MIDCMD_DATA6 0x01ce 533#define mmSDMA6_RLC1_MIDCMD_DATA6_BASE_IDX 1 534#define mmSDMA6_RLC1_MIDCMD_DATA7 0x01cf 535#define mmSDMA6_RLC1_MIDCMD_DATA7_BASE_IDX 1 536#define mmSDMA6_RLC1_MIDCMD_DATA8 0x01d0 537#define mmSDMA6_RLC1_MIDCMD_DATA8_BASE_IDX 1 538#define mmSDMA6_RLC1_MIDCMD_CNTL 0x01d1 539#define mmSDMA6_RLC1_MIDCMD_CNTL_BASE_IDX 1 540#define mmSDMA6_RLC2_RB_CNTL 0x01e0 541#define mmSDMA6_RLC2_RB_CNTL_BASE_IDX 1 542#define mmSDMA6_RLC2_RB_BASE 0x01e1 543#define mmSDMA6_RLC2_RB_BASE_BASE_IDX 1 544#define mmSDMA6_RLC2_RB_BASE_HI 0x01e2 545#define mmSDMA6_RLC2_RB_BASE_HI_BASE_IDX 1 546#define mmSDMA6_RLC2_RB_RPTR 0x01e3 547#define mmSDMA6_RLC2_RB_RPTR_BASE_IDX 1 548#define mmSDMA6_RLC2_RB_RPTR_HI 0x01e4 549#define mmSDMA6_RLC2_RB_RPTR_HI_BASE_IDX 1 550#define mmSDMA6_RLC2_RB_WPTR 0x01e5 551#define mmSDMA6_RLC2_RB_WPTR_BASE_IDX 1 552#define mmSDMA6_RLC2_RB_WPTR_HI 0x01e6 553#define mmSDMA6_RLC2_RB_WPTR_HI_BASE_IDX 1 554#define mmSDMA6_RLC2_RB_WPTR_POLL_CNTL 0x01e7 555#define mmSDMA6_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 1 556#define mmSDMA6_RLC2_RB_RPTR_ADDR_HI 0x01e8 557#define mmSDMA6_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 1 558#define mmSDMA6_RLC2_RB_RPTR_ADDR_LO 0x01e9 559#define mmSDMA6_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 1 560#define mmSDMA6_RLC2_IB_CNTL 0x01ea 561#define mmSDMA6_RLC2_IB_CNTL_BASE_IDX 1 562#define mmSDMA6_RLC2_IB_RPTR 0x01eb 563#define mmSDMA6_RLC2_IB_RPTR_BASE_IDX 1 564#define mmSDMA6_RLC2_IB_OFFSET 0x01ec 565#define mmSDMA6_RLC2_IB_OFFSET_BASE_IDX 1 566#define mmSDMA6_RLC2_IB_BASE_LO 0x01ed 567#define mmSDMA6_RLC2_IB_BASE_LO_BASE_IDX 1 568#define mmSDMA6_RLC2_IB_BASE_HI 0x01ee 569#define mmSDMA6_RLC2_IB_BASE_HI_BASE_IDX 1 570#define mmSDMA6_RLC2_IB_SIZE 0x01ef 571#define mmSDMA6_RLC2_IB_SIZE_BASE_IDX 1 572#define mmSDMA6_RLC2_SKIP_CNTL 0x01f0 573#define mmSDMA6_RLC2_SKIP_CNTL_BASE_IDX 1 574#define mmSDMA6_RLC2_CONTEXT_STATUS 0x01f1 575#define mmSDMA6_RLC2_CONTEXT_STATUS_BASE_IDX 1 576#define mmSDMA6_RLC2_DOORBELL 0x01f2 577#define mmSDMA6_RLC2_DOORBELL_BASE_IDX 1 578#define mmSDMA6_RLC2_STATUS 0x0208 579#define mmSDMA6_RLC2_STATUS_BASE_IDX 1 580#define mmSDMA6_RLC2_DOORBELL_LOG 0x0209 581#define mmSDMA6_RLC2_DOORBELL_LOG_BASE_IDX 1 582#define mmSDMA6_RLC2_WATERMARK 0x020a 583#define mmSDMA6_RLC2_WATERMARK_BASE_IDX 1 584#define mmSDMA6_RLC2_DOORBELL_OFFSET 0x020b 585#define mmSDMA6_RLC2_DOORBELL_OFFSET_BASE_IDX 1 586#define mmSDMA6_RLC2_CSA_ADDR_LO 0x020c 587#define mmSDMA6_RLC2_CSA_ADDR_LO_BASE_IDX 1 588#define mmSDMA6_RLC2_CSA_ADDR_HI 0x020d 589#define mmSDMA6_RLC2_CSA_ADDR_HI_BASE_IDX 1 590#define mmSDMA6_RLC2_IB_SUB_REMAIN 0x020f 591#define mmSDMA6_RLC2_IB_SUB_REMAIN_BASE_IDX 1 592#define mmSDMA6_RLC2_PREEMPT 0x0210 593#define mmSDMA6_RLC2_PREEMPT_BASE_IDX 1 594#define mmSDMA6_RLC2_DUMMY_REG 0x0211 595#define mmSDMA6_RLC2_DUMMY_REG_BASE_IDX 1 596#define mmSDMA6_RLC2_RB_WPTR_POLL_ADDR_HI 0x0212 597#define mmSDMA6_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 598#define mmSDMA6_RLC2_RB_WPTR_POLL_ADDR_LO 0x0213 599#define mmSDMA6_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 600#define mmSDMA6_RLC2_RB_AQL_CNTL 0x0214 601#define mmSDMA6_RLC2_RB_AQL_CNTL_BASE_IDX 1 602#define mmSDMA6_RLC2_MINOR_PTR_UPDATE 0x0215 603#define mmSDMA6_RLC2_MINOR_PTR_UPDATE_BASE_IDX 1 604#define mmSDMA6_RLC2_MIDCMD_DATA0 0x0220 605#define mmSDMA6_RLC2_MIDCMD_DATA0_BASE_IDX 1 606#define mmSDMA6_RLC2_MIDCMD_DATA1 0x0221 607#define mmSDMA6_RLC2_MIDCMD_DATA1_BASE_IDX 1 608#define mmSDMA6_RLC2_MIDCMD_DATA2 0x0222 609#define mmSDMA6_RLC2_MIDCMD_DATA2_BASE_IDX 1 610#define mmSDMA6_RLC2_MIDCMD_DATA3 0x0223 611#define mmSDMA6_RLC2_MIDCMD_DATA3_BASE_IDX 1 612#define mmSDMA6_RLC2_MIDCMD_DATA4 0x0224 613#define mmSDMA6_RLC2_MIDCMD_DATA4_BASE_IDX 1 614#define mmSDMA6_RLC2_MIDCMD_DATA5 0x0225 615#define mmSDMA6_RLC2_MIDCMD_DATA5_BASE_IDX 1 616#define mmSDMA6_RLC2_MIDCMD_DATA6 0x0226 617#define mmSDMA6_RLC2_MIDCMD_DATA6_BASE_IDX 1 618#define mmSDMA6_RLC2_MIDCMD_DATA7 0x0227 619#define mmSDMA6_RLC2_MIDCMD_DATA7_BASE_IDX 1 620#define mmSDMA6_RLC2_MIDCMD_DATA8 0x0228 621#define mmSDMA6_RLC2_MIDCMD_DATA8_BASE_IDX 1 622#define mmSDMA6_RLC2_MIDCMD_CNTL 0x0229 623#define mmSDMA6_RLC2_MIDCMD_CNTL_BASE_IDX 1 624#define mmSDMA6_RLC3_RB_CNTL 0x0238 625#define mmSDMA6_RLC3_RB_CNTL_BASE_IDX 1 626#define mmSDMA6_RLC3_RB_BASE 0x0239 627#define mmSDMA6_RLC3_RB_BASE_BASE_IDX 1 628#define mmSDMA6_RLC3_RB_BASE_HI 0x023a 629#define mmSDMA6_RLC3_RB_BASE_HI_BASE_IDX 1 630#define mmSDMA6_RLC3_RB_RPTR 0x023b 631#define mmSDMA6_RLC3_RB_RPTR_BASE_IDX 1 632#define mmSDMA6_RLC3_RB_RPTR_HI 0x023c 633#define mmSDMA6_RLC3_RB_RPTR_HI_BASE_IDX 1 634#define mmSDMA6_RLC3_RB_WPTR 0x023d 635#define mmSDMA6_RLC3_RB_WPTR_BASE_IDX 1 636#define mmSDMA6_RLC3_RB_WPTR_HI 0x023e 637#define mmSDMA6_RLC3_RB_WPTR_HI_BASE_IDX 1 638#define mmSDMA6_RLC3_RB_WPTR_POLL_CNTL 0x023f 639#define mmSDMA6_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 1 640#define mmSDMA6_RLC3_RB_RPTR_ADDR_HI 0x0240 641#define mmSDMA6_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 1 642#define mmSDMA6_RLC3_RB_RPTR_ADDR_LO 0x0241 643#define mmSDMA6_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 1 644#define mmSDMA6_RLC3_IB_CNTL 0x0242 645#define mmSDMA6_RLC3_IB_CNTL_BASE_IDX 1 646#define mmSDMA6_RLC3_IB_RPTR 0x0243 647#define mmSDMA6_RLC3_IB_RPTR_BASE_IDX 1 648#define mmSDMA6_RLC3_IB_OFFSET 0x0244 649#define mmSDMA6_RLC3_IB_OFFSET_BASE_IDX 1 650#define mmSDMA6_RLC3_IB_BASE_LO 0x0245 651#define mmSDMA6_RLC3_IB_BASE_LO_BASE_IDX 1 652#define mmSDMA6_RLC3_IB_BASE_HI 0x0246 653#define mmSDMA6_RLC3_IB_BASE_HI_BASE_IDX 1 654#define mmSDMA6_RLC3_IB_SIZE 0x0247 655#define mmSDMA6_RLC3_IB_SIZE_BASE_IDX 1 656#define mmSDMA6_RLC3_SKIP_CNTL 0x0248 657#define mmSDMA6_RLC3_SKIP_CNTL_BASE_IDX 1 658#define mmSDMA6_RLC3_CONTEXT_STATUS 0x0249 659#define mmSDMA6_RLC3_CONTEXT_STATUS_BASE_IDX 1 660#define mmSDMA6_RLC3_DOORBELL 0x024a 661#define mmSDMA6_RLC3_DOORBELL_BASE_IDX 1 662#define mmSDMA6_RLC3_STATUS 0x0260 663#define mmSDMA6_RLC3_STATUS_BASE_IDX 1 664#define mmSDMA6_RLC3_DOORBELL_LOG 0x0261 665#define mmSDMA6_RLC3_DOORBELL_LOG_BASE_IDX 1 666#define mmSDMA6_RLC3_WATERMARK 0x0262 667#define mmSDMA6_RLC3_WATERMARK_BASE_IDX 1 668#define mmSDMA6_RLC3_DOORBELL_OFFSET 0x0263 669#define mmSDMA6_RLC3_DOORBELL_OFFSET_BASE_IDX 1 670#define mmSDMA6_RLC3_CSA_ADDR_LO 0x0264 671#define mmSDMA6_RLC3_CSA_ADDR_LO_BASE_IDX 1 672#define mmSDMA6_RLC3_CSA_ADDR_HI 0x0265 673#define mmSDMA6_RLC3_CSA_ADDR_HI_BASE_IDX 1 674#define mmSDMA6_RLC3_IB_SUB_REMAIN 0x0267 675#define mmSDMA6_RLC3_IB_SUB_REMAIN_BASE_IDX 1 676#define mmSDMA6_RLC3_PREEMPT 0x0268 677#define mmSDMA6_RLC3_PREEMPT_BASE_IDX 1 678#define mmSDMA6_RLC3_DUMMY_REG 0x0269 679#define mmSDMA6_RLC3_DUMMY_REG_BASE_IDX 1 680#define mmSDMA6_RLC3_RB_WPTR_POLL_ADDR_HI 0x026a 681#define mmSDMA6_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 682#define mmSDMA6_RLC3_RB_WPTR_POLL_ADDR_LO 0x026b 683#define mmSDMA6_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 684#define mmSDMA6_RLC3_RB_AQL_CNTL 0x026c 685#define mmSDMA6_RLC3_RB_AQL_CNTL_BASE_IDX 1 686#define mmSDMA6_RLC3_MINOR_PTR_UPDATE 0x026d 687#define mmSDMA6_RLC3_MINOR_PTR_UPDATE_BASE_IDX 1 688#define mmSDMA6_RLC3_MIDCMD_DATA0 0x0278 689#define mmSDMA6_RLC3_MIDCMD_DATA0_BASE_IDX 1 690#define mmSDMA6_RLC3_MIDCMD_DATA1 0x0279 691#define mmSDMA6_RLC3_MIDCMD_DATA1_BASE_IDX 1 692#define mmSDMA6_RLC3_MIDCMD_DATA2 0x027a 693#define mmSDMA6_RLC3_MIDCMD_DATA2_BASE_IDX 1 694#define mmSDMA6_RLC3_MIDCMD_DATA3 0x027b 695#define mmSDMA6_RLC3_MIDCMD_DATA3_BASE_IDX 1 696#define mmSDMA6_RLC3_MIDCMD_DATA4 0x027c 697#define mmSDMA6_RLC3_MIDCMD_DATA4_BASE_IDX 1 698#define mmSDMA6_RLC3_MIDCMD_DATA5 0x027d 699#define mmSDMA6_RLC3_MIDCMD_DATA5_BASE_IDX 1 700#define mmSDMA6_RLC3_MIDCMD_DATA6 0x027e 701#define mmSDMA6_RLC3_MIDCMD_DATA6_BASE_IDX 1 702#define mmSDMA6_RLC3_MIDCMD_DATA7 0x027f 703#define mmSDMA6_RLC3_MIDCMD_DATA7_BASE_IDX 1 704#define mmSDMA6_RLC3_MIDCMD_DATA8 0x0280 705#define mmSDMA6_RLC3_MIDCMD_DATA8_BASE_IDX 1 706#define mmSDMA6_RLC3_MIDCMD_CNTL 0x0281 707#define mmSDMA6_RLC3_MIDCMD_CNTL_BASE_IDX 1 708#define mmSDMA6_RLC4_RB_CNTL 0x0290 709#define mmSDMA6_RLC4_RB_CNTL_BASE_IDX 1 710#define mmSDMA6_RLC4_RB_BASE 0x0291 711#define mmSDMA6_RLC4_RB_BASE_BASE_IDX 1 712#define mmSDMA6_RLC4_RB_BASE_HI 0x0292 713#define mmSDMA6_RLC4_RB_BASE_HI_BASE_IDX 1 714#define mmSDMA6_RLC4_RB_RPTR 0x0293 715#define mmSDMA6_RLC4_RB_RPTR_BASE_IDX 1 716#define mmSDMA6_RLC4_RB_RPTR_HI 0x0294 717#define mmSDMA6_RLC4_RB_RPTR_HI_BASE_IDX 1 718#define mmSDMA6_RLC4_RB_WPTR 0x0295 719#define mmSDMA6_RLC4_RB_WPTR_BASE_IDX 1 720#define mmSDMA6_RLC4_RB_WPTR_HI 0x0296 721#define mmSDMA6_RLC4_RB_WPTR_HI_BASE_IDX 1 722#define mmSDMA6_RLC4_RB_WPTR_POLL_CNTL 0x0297 723#define mmSDMA6_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 1 724#define mmSDMA6_RLC4_RB_RPTR_ADDR_HI 0x0298 725#define mmSDMA6_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 1 726#define mmSDMA6_RLC4_RB_RPTR_ADDR_LO 0x0299 727#define mmSDMA6_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 1 728#define mmSDMA6_RLC4_IB_CNTL 0x029a 729#define mmSDMA6_RLC4_IB_CNTL_BASE_IDX 1 730#define mmSDMA6_RLC4_IB_RPTR 0x029b 731#define mmSDMA6_RLC4_IB_RPTR_BASE_IDX 1 732#define mmSDMA6_RLC4_IB_OFFSET 0x029c 733#define mmSDMA6_RLC4_IB_OFFSET_BASE_IDX 1 734#define mmSDMA6_RLC4_IB_BASE_LO 0x029d 735#define mmSDMA6_RLC4_IB_BASE_LO_BASE_IDX 1 736#define mmSDMA6_RLC4_IB_BASE_HI 0x029e 737#define mmSDMA6_RLC4_IB_BASE_HI_BASE_IDX 1 738#define mmSDMA6_RLC4_IB_SIZE 0x029f 739#define mmSDMA6_RLC4_IB_SIZE_BASE_IDX 1 740#define mmSDMA6_RLC4_SKIP_CNTL 0x02a0 741#define mmSDMA6_RLC4_SKIP_CNTL_BASE_IDX 1 742#define mmSDMA6_RLC4_CONTEXT_STATUS 0x02a1 743#define mmSDMA6_RLC4_CONTEXT_STATUS_BASE_IDX 1 744#define mmSDMA6_RLC4_DOORBELL 0x02a2 745#define mmSDMA6_RLC4_DOORBELL_BASE_IDX 1 746#define mmSDMA6_RLC4_STATUS 0x02b8 747#define mmSDMA6_RLC4_STATUS_BASE_IDX 1 748#define mmSDMA6_RLC4_DOORBELL_LOG 0x02b9 749#define mmSDMA6_RLC4_DOORBELL_LOG_BASE_IDX 1 750#define mmSDMA6_RLC4_WATERMARK 0x02ba 751#define mmSDMA6_RLC4_WATERMARK_BASE_IDX 1 752#define mmSDMA6_RLC4_DOORBELL_OFFSET 0x02bb 753#define mmSDMA6_RLC4_DOORBELL_OFFSET_BASE_IDX 1 754#define mmSDMA6_RLC4_CSA_ADDR_LO 0x02bc 755#define mmSDMA6_RLC4_CSA_ADDR_LO_BASE_IDX 1 756#define mmSDMA6_RLC4_CSA_ADDR_HI 0x02bd 757#define mmSDMA6_RLC4_CSA_ADDR_HI_BASE_IDX 1 758#define mmSDMA6_RLC4_IB_SUB_REMAIN 0x02bf 759#define mmSDMA6_RLC4_IB_SUB_REMAIN_BASE_IDX 1 760#define mmSDMA6_RLC4_PREEMPT 0x02c0 761#define mmSDMA6_RLC4_PREEMPT_BASE_IDX 1 762#define mmSDMA6_RLC4_DUMMY_REG 0x02c1 763#define mmSDMA6_RLC4_DUMMY_REG_BASE_IDX 1 764#define mmSDMA6_RLC4_RB_WPTR_POLL_ADDR_HI 0x02c2 765#define mmSDMA6_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 766#define mmSDMA6_RLC4_RB_WPTR_POLL_ADDR_LO 0x02c3 767#define mmSDMA6_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 768#define mmSDMA6_RLC4_RB_AQL_CNTL 0x02c4 769#define mmSDMA6_RLC4_RB_AQL_CNTL_BASE_IDX 1 770#define mmSDMA6_RLC4_MINOR_PTR_UPDATE 0x02c5 771#define mmSDMA6_RLC4_MINOR_PTR_UPDATE_BASE_IDX 1 772#define mmSDMA6_RLC4_MIDCMD_DATA0 0x02d0 773#define mmSDMA6_RLC4_MIDCMD_DATA0_BASE_IDX 1 774#define mmSDMA6_RLC4_MIDCMD_DATA1 0x02d1 775#define mmSDMA6_RLC4_MIDCMD_DATA1_BASE_IDX 1 776#define mmSDMA6_RLC4_MIDCMD_DATA2 0x02d2 777#define mmSDMA6_RLC4_MIDCMD_DATA2_BASE_IDX 1 778#define mmSDMA6_RLC4_MIDCMD_DATA3 0x02d3 779#define mmSDMA6_RLC4_MIDCMD_DATA3_BASE_IDX 1 780#define mmSDMA6_RLC4_MIDCMD_DATA4 0x02d4 781#define mmSDMA6_RLC4_MIDCMD_DATA4_BASE_IDX 1 782#define mmSDMA6_RLC4_MIDCMD_DATA5 0x02d5 783#define mmSDMA6_RLC4_MIDCMD_DATA5_BASE_IDX 1 784#define mmSDMA6_RLC4_MIDCMD_DATA6 0x02d6 785#define mmSDMA6_RLC4_MIDCMD_DATA6_BASE_IDX 1 786#define mmSDMA6_RLC4_MIDCMD_DATA7 0x02d7 787#define mmSDMA6_RLC4_MIDCMD_DATA7_BASE_IDX 1 788#define mmSDMA6_RLC4_MIDCMD_DATA8 0x02d8 789#define mmSDMA6_RLC4_MIDCMD_DATA8_BASE_IDX 1 790#define mmSDMA6_RLC4_MIDCMD_CNTL 0x02d9 791#define mmSDMA6_RLC4_MIDCMD_CNTL_BASE_IDX 1 792#define mmSDMA6_RLC5_RB_CNTL 0x02e8 793#define mmSDMA6_RLC5_RB_CNTL_BASE_IDX 1 794#define mmSDMA6_RLC5_RB_BASE 0x02e9 795#define mmSDMA6_RLC5_RB_BASE_BASE_IDX 1 796#define mmSDMA6_RLC5_RB_BASE_HI 0x02ea 797#define mmSDMA6_RLC5_RB_BASE_HI_BASE_IDX 1 798#define mmSDMA6_RLC5_RB_RPTR 0x02eb 799#define mmSDMA6_RLC5_RB_RPTR_BASE_IDX 1 800#define mmSDMA6_RLC5_RB_RPTR_HI 0x02ec 801#define mmSDMA6_RLC5_RB_RPTR_HI_BASE_IDX 1 802#define mmSDMA6_RLC5_RB_WPTR 0x02ed 803#define mmSDMA6_RLC5_RB_WPTR_BASE_IDX 1 804#define mmSDMA6_RLC5_RB_WPTR_HI 0x02ee 805#define mmSDMA6_RLC5_RB_WPTR_HI_BASE_IDX 1 806#define mmSDMA6_RLC5_RB_WPTR_POLL_CNTL 0x02ef 807#define mmSDMA6_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 1 808#define mmSDMA6_RLC5_RB_RPTR_ADDR_HI 0x02f0 809#define mmSDMA6_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 1 810#define mmSDMA6_RLC5_RB_RPTR_ADDR_LO 0x02f1 811#define mmSDMA6_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 1 812#define mmSDMA6_RLC5_IB_CNTL 0x02f2 813#define mmSDMA6_RLC5_IB_CNTL_BASE_IDX 1 814#define mmSDMA6_RLC5_IB_RPTR 0x02f3 815#define mmSDMA6_RLC5_IB_RPTR_BASE_IDX 1 816#define mmSDMA6_RLC5_IB_OFFSET 0x02f4 817#define mmSDMA6_RLC5_IB_OFFSET_BASE_IDX 1 818#define mmSDMA6_RLC5_IB_BASE_LO 0x02f5 819#define mmSDMA6_RLC5_IB_BASE_LO_BASE_IDX 1 820#define mmSDMA6_RLC5_IB_BASE_HI 0x02f6 821#define mmSDMA6_RLC5_IB_BASE_HI_BASE_IDX 1 822#define mmSDMA6_RLC5_IB_SIZE 0x02f7 823#define mmSDMA6_RLC5_IB_SIZE_BASE_IDX 1 824#define mmSDMA6_RLC5_SKIP_CNTL 0x02f8 825#define mmSDMA6_RLC5_SKIP_CNTL_BASE_IDX 1 826#define mmSDMA6_RLC5_CONTEXT_STATUS 0x02f9 827#define mmSDMA6_RLC5_CONTEXT_STATUS_BASE_IDX 1 828#define mmSDMA6_RLC5_DOORBELL 0x02fa 829#define mmSDMA6_RLC5_DOORBELL_BASE_IDX 1 830#define mmSDMA6_RLC5_STATUS 0x0310 831#define mmSDMA6_RLC5_STATUS_BASE_IDX 1 832#define mmSDMA6_RLC5_DOORBELL_LOG 0x0311 833#define mmSDMA6_RLC5_DOORBELL_LOG_BASE_IDX 1 834#define mmSDMA6_RLC5_WATERMARK 0x0312 835#define mmSDMA6_RLC5_WATERMARK_BASE_IDX 1 836#define mmSDMA6_RLC5_DOORBELL_OFFSET 0x0313 837#define mmSDMA6_RLC5_DOORBELL_OFFSET_BASE_IDX 1 838#define mmSDMA6_RLC5_CSA_ADDR_LO 0x0314 839#define mmSDMA6_RLC5_CSA_ADDR_LO_BASE_IDX 1 840#define mmSDMA6_RLC5_CSA_ADDR_HI 0x0315 841#define mmSDMA6_RLC5_CSA_ADDR_HI_BASE_IDX 1 842#define mmSDMA6_RLC5_IB_SUB_REMAIN 0x0317 843#define mmSDMA6_RLC5_IB_SUB_REMAIN_BASE_IDX 1 844#define mmSDMA6_RLC5_PREEMPT 0x0318 845#define mmSDMA6_RLC5_PREEMPT_BASE_IDX 1 846#define mmSDMA6_RLC5_DUMMY_REG 0x0319 847#define mmSDMA6_RLC5_DUMMY_REG_BASE_IDX 1 848#define mmSDMA6_RLC5_RB_WPTR_POLL_ADDR_HI 0x031a 849#define mmSDMA6_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 850#define mmSDMA6_RLC5_RB_WPTR_POLL_ADDR_LO 0x031b 851#define mmSDMA6_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 852#define mmSDMA6_RLC5_RB_AQL_CNTL 0x031c 853#define mmSDMA6_RLC5_RB_AQL_CNTL_BASE_IDX 1 854#define mmSDMA6_RLC5_MINOR_PTR_UPDATE 0x031d 855#define mmSDMA6_RLC5_MINOR_PTR_UPDATE_BASE_IDX 1 856#define mmSDMA6_RLC5_MIDCMD_DATA0 0x0328 857#define mmSDMA6_RLC5_MIDCMD_DATA0_BASE_IDX 1 858#define mmSDMA6_RLC5_MIDCMD_DATA1 0x0329 859#define mmSDMA6_RLC5_MIDCMD_DATA1_BASE_IDX 1 860#define mmSDMA6_RLC5_MIDCMD_DATA2 0x032a 861#define mmSDMA6_RLC5_MIDCMD_DATA2_BASE_IDX 1 862#define mmSDMA6_RLC5_MIDCMD_DATA3 0x032b 863#define mmSDMA6_RLC5_MIDCMD_DATA3_BASE_IDX 1 864#define mmSDMA6_RLC5_MIDCMD_DATA4 0x032c 865#define mmSDMA6_RLC5_MIDCMD_DATA4_BASE_IDX 1 866#define mmSDMA6_RLC5_MIDCMD_DATA5 0x032d 867#define mmSDMA6_RLC5_MIDCMD_DATA5_BASE_IDX 1 868#define mmSDMA6_RLC5_MIDCMD_DATA6 0x032e 869#define mmSDMA6_RLC5_MIDCMD_DATA6_BASE_IDX 1 870#define mmSDMA6_RLC5_MIDCMD_DATA7 0x032f 871#define mmSDMA6_RLC5_MIDCMD_DATA7_BASE_IDX 1 872#define mmSDMA6_RLC5_MIDCMD_DATA8 0x0330 873#define mmSDMA6_RLC5_MIDCMD_DATA8_BASE_IDX 1 874#define mmSDMA6_RLC5_MIDCMD_CNTL 0x0331 875#define mmSDMA6_RLC5_MIDCMD_CNTL_BASE_IDX 1 876#define mmSDMA6_RLC6_RB_CNTL 0x0340 877#define mmSDMA6_RLC6_RB_CNTL_BASE_IDX 1 878#define mmSDMA6_RLC6_RB_BASE 0x0341 879#define mmSDMA6_RLC6_RB_BASE_BASE_IDX 1 880#define mmSDMA6_RLC6_RB_BASE_HI 0x0342 881#define mmSDMA6_RLC6_RB_BASE_HI_BASE_IDX 1 882#define mmSDMA6_RLC6_RB_RPTR 0x0343 883#define mmSDMA6_RLC6_RB_RPTR_BASE_IDX 1 884#define mmSDMA6_RLC6_RB_RPTR_HI 0x0344 885#define mmSDMA6_RLC6_RB_RPTR_HI_BASE_IDX 1 886#define mmSDMA6_RLC6_RB_WPTR 0x0345 887#define mmSDMA6_RLC6_RB_WPTR_BASE_IDX 1 888#define mmSDMA6_RLC6_RB_WPTR_HI 0x0346 889#define mmSDMA6_RLC6_RB_WPTR_HI_BASE_IDX 1 890#define mmSDMA6_RLC6_RB_WPTR_POLL_CNTL 0x0347 891#define mmSDMA6_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 1 892#define mmSDMA6_RLC6_RB_RPTR_ADDR_HI 0x0348 893#define mmSDMA6_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 1 894#define mmSDMA6_RLC6_RB_RPTR_ADDR_LO 0x0349 895#define mmSDMA6_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 1 896#define mmSDMA6_RLC6_IB_CNTL 0x034a 897#define mmSDMA6_RLC6_IB_CNTL_BASE_IDX 1 898#define mmSDMA6_RLC6_IB_RPTR 0x034b 899#define mmSDMA6_RLC6_IB_RPTR_BASE_IDX 1 900#define mmSDMA6_RLC6_IB_OFFSET 0x034c 901#define mmSDMA6_RLC6_IB_OFFSET_BASE_IDX 1 902#define mmSDMA6_RLC6_IB_BASE_LO 0x034d 903#define mmSDMA6_RLC6_IB_BASE_LO_BASE_IDX 1 904#define mmSDMA6_RLC6_IB_BASE_HI 0x034e 905#define mmSDMA6_RLC6_IB_BASE_HI_BASE_IDX 1 906#define mmSDMA6_RLC6_IB_SIZE 0x034f 907#define mmSDMA6_RLC6_IB_SIZE_BASE_IDX 1 908#define mmSDMA6_RLC6_SKIP_CNTL 0x0350 909#define mmSDMA6_RLC6_SKIP_CNTL_BASE_IDX 1 910#define mmSDMA6_RLC6_CONTEXT_STATUS 0x0351 911#define mmSDMA6_RLC6_CONTEXT_STATUS_BASE_IDX 1 912#define mmSDMA6_RLC6_DOORBELL 0x0352 913#define mmSDMA6_RLC6_DOORBELL_BASE_IDX 1 914#define mmSDMA6_RLC6_STATUS 0x0368 915#define mmSDMA6_RLC6_STATUS_BASE_IDX 1 916#define mmSDMA6_RLC6_DOORBELL_LOG 0x0369 917#define mmSDMA6_RLC6_DOORBELL_LOG_BASE_IDX 1 918#define mmSDMA6_RLC6_WATERMARK 0x036a 919#define mmSDMA6_RLC6_WATERMARK_BASE_IDX 1 920#define mmSDMA6_RLC6_DOORBELL_OFFSET 0x036b 921#define mmSDMA6_RLC6_DOORBELL_OFFSET_BASE_IDX 1 922#define mmSDMA6_RLC6_CSA_ADDR_LO 0x036c 923#define mmSDMA6_RLC6_CSA_ADDR_LO_BASE_IDX 1 924#define mmSDMA6_RLC6_CSA_ADDR_HI 0x036d 925#define mmSDMA6_RLC6_CSA_ADDR_HI_BASE_IDX 1 926#define mmSDMA6_RLC6_IB_SUB_REMAIN 0x036f 927#define mmSDMA6_RLC6_IB_SUB_REMAIN_BASE_IDX 1 928#define mmSDMA6_RLC6_PREEMPT 0x0370 929#define mmSDMA6_RLC6_PREEMPT_BASE_IDX 1 930#define mmSDMA6_RLC6_DUMMY_REG 0x0371 931#define mmSDMA6_RLC6_DUMMY_REG_BASE_IDX 1 932#define mmSDMA6_RLC6_RB_WPTR_POLL_ADDR_HI 0x0372 933#define mmSDMA6_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 934#define mmSDMA6_RLC6_RB_WPTR_POLL_ADDR_LO 0x0373 935#define mmSDMA6_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 936#define mmSDMA6_RLC6_RB_AQL_CNTL 0x0374 937#define mmSDMA6_RLC6_RB_AQL_CNTL_BASE_IDX 1 938#define mmSDMA6_RLC6_MINOR_PTR_UPDATE 0x0375 939#define mmSDMA6_RLC6_MINOR_PTR_UPDATE_BASE_IDX 1 940#define mmSDMA6_RLC6_MIDCMD_DATA0 0x0380 941#define mmSDMA6_RLC6_MIDCMD_DATA0_BASE_IDX 1 942#define mmSDMA6_RLC6_MIDCMD_DATA1 0x0381 943#define mmSDMA6_RLC6_MIDCMD_DATA1_BASE_IDX 1 944#define mmSDMA6_RLC6_MIDCMD_DATA2 0x0382 945#define mmSDMA6_RLC6_MIDCMD_DATA2_BASE_IDX 1 946#define mmSDMA6_RLC6_MIDCMD_DATA3 0x0383 947#define mmSDMA6_RLC6_MIDCMD_DATA3_BASE_IDX 1 948#define mmSDMA6_RLC6_MIDCMD_DATA4 0x0384 949#define mmSDMA6_RLC6_MIDCMD_DATA4_BASE_IDX 1 950#define mmSDMA6_RLC6_MIDCMD_DATA5 0x0385 951#define mmSDMA6_RLC6_MIDCMD_DATA5_BASE_IDX 1 952#define mmSDMA6_RLC6_MIDCMD_DATA6 0x0386 953#define mmSDMA6_RLC6_MIDCMD_DATA6_BASE_IDX 1 954#define mmSDMA6_RLC6_MIDCMD_DATA7 0x0387 955#define mmSDMA6_RLC6_MIDCMD_DATA7_BASE_IDX 1 956#define mmSDMA6_RLC6_MIDCMD_DATA8 0x0388 957#define mmSDMA6_RLC6_MIDCMD_DATA8_BASE_IDX 1 958#define mmSDMA6_RLC6_MIDCMD_CNTL 0x0389 959#define mmSDMA6_RLC6_MIDCMD_CNTL_BASE_IDX 1 960#define mmSDMA6_RLC7_RB_CNTL 0x0398 961#define mmSDMA6_RLC7_RB_CNTL_BASE_IDX 1 962#define mmSDMA6_RLC7_RB_BASE 0x0399 963#define mmSDMA6_RLC7_RB_BASE_BASE_IDX 1 964#define mmSDMA6_RLC7_RB_BASE_HI 0x039a 965#define mmSDMA6_RLC7_RB_BASE_HI_BASE_IDX 1 966#define mmSDMA6_RLC7_RB_RPTR 0x039b 967#define mmSDMA6_RLC7_RB_RPTR_BASE_IDX 1 968#define mmSDMA6_RLC7_RB_RPTR_HI 0x039c 969#define mmSDMA6_RLC7_RB_RPTR_HI_BASE_IDX 1 970#define mmSDMA6_RLC7_RB_WPTR 0x039d 971#define mmSDMA6_RLC7_RB_WPTR_BASE_IDX 1 972#define mmSDMA6_RLC7_RB_WPTR_HI 0x039e 973#define mmSDMA6_RLC7_RB_WPTR_HI_BASE_IDX 1 974#define mmSDMA6_RLC7_RB_WPTR_POLL_CNTL 0x039f 975#define mmSDMA6_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 1 976#define mmSDMA6_RLC7_RB_RPTR_ADDR_HI 0x03a0 977#define mmSDMA6_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 1 978#define mmSDMA6_RLC7_RB_RPTR_ADDR_LO 0x03a1 979#define mmSDMA6_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 1 980#define mmSDMA6_RLC7_IB_CNTL 0x03a2 981#define mmSDMA6_RLC7_IB_CNTL_BASE_IDX 1 982#define mmSDMA6_RLC7_IB_RPTR 0x03a3 983#define mmSDMA6_RLC7_IB_RPTR_BASE_IDX 1 984#define mmSDMA6_RLC7_IB_OFFSET 0x03a4 985#define mmSDMA6_RLC7_IB_OFFSET_BASE_IDX 1 986#define mmSDMA6_RLC7_IB_BASE_LO 0x03a5 987#define mmSDMA6_RLC7_IB_BASE_LO_BASE_IDX 1 988#define mmSDMA6_RLC7_IB_BASE_HI 0x03a6 989#define mmSDMA6_RLC7_IB_BASE_HI_BASE_IDX 1 990#define mmSDMA6_RLC7_IB_SIZE 0x03a7 991#define mmSDMA6_RLC7_IB_SIZE_BASE_IDX 1 992#define mmSDMA6_RLC7_SKIP_CNTL 0x03a8 993#define mmSDMA6_RLC7_SKIP_CNTL_BASE_IDX 1 994#define mmSDMA6_RLC7_CONTEXT_STATUS 0x03a9 995#define mmSDMA6_RLC7_CONTEXT_STATUS_BASE_IDX 1 996#define mmSDMA6_RLC7_DOORBELL 0x03aa 997#define mmSDMA6_RLC7_DOORBELL_BASE_IDX 1 998#define mmSDMA6_RLC7_STATUS 0x03c0 999#define mmSDMA6_RLC7_STATUS_BASE_IDX 1 1000#define mmSDMA6_RLC7_DOORBELL_LOG 0x03c1 1001#define mmSDMA6_RLC7_DOORBELL_LOG_BASE_IDX 1 1002#define mmSDMA6_RLC7_WATERMARK 0x03c2 1003#define mmSDMA6_RLC7_WATERMARK_BASE_IDX 1 1004#define mmSDMA6_RLC7_DOORBELL_OFFSET 0x03c3 1005#define mmSDMA6_RLC7_DOORBELL_OFFSET_BASE_IDX 1 1006#define mmSDMA6_RLC7_CSA_ADDR_LO 0x03c4 1007#define mmSDMA6_RLC7_CSA_ADDR_LO_BASE_IDX 1 1008#define mmSDMA6_RLC7_CSA_ADDR_HI 0x03c5 1009#define mmSDMA6_RLC7_CSA_ADDR_HI_BASE_IDX 1 1010#define mmSDMA6_RLC7_IB_SUB_REMAIN 0x03c7 1011#define mmSDMA6_RLC7_IB_SUB_REMAIN_BASE_IDX 1 1012#define mmSDMA6_RLC7_PREEMPT 0x03c8 1013#define mmSDMA6_RLC7_PREEMPT_BASE_IDX 1 1014#define mmSDMA6_RLC7_DUMMY_REG 0x03c9 1015#define mmSDMA6_RLC7_DUMMY_REG_BASE_IDX 1 1016#define mmSDMA6_RLC7_RB_WPTR_POLL_ADDR_HI 0x03ca 1017#define mmSDMA6_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 1018#define mmSDMA6_RLC7_RB_WPTR_POLL_ADDR_LO 0x03cb 1019#define mmSDMA6_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 1020#define mmSDMA6_RLC7_RB_AQL_CNTL 0x03cc 1021#define mmSDMA6_RLC7_RB_AQL_CNTL_BASE_IDX 1 1022#define mmSDMA6_RLC7_MINOR_PTR_UPDATE 0x03cd 1023#define mmSDMA6_RLC7_MINOR_PTR_UPDATE_BASE_IDX 1 1024#define mmSDMA6_RLC7_MIDCMD_DATA0 0x03d8 1025#define mmSDMA6_RLC7_MIDCMD_DATA0_BASE_IDX 1 1026#define mmSDMA6_RLC7_MIDCMD_DATA1 0x03d9 1027#define mmSDMA6_RLC7_MIDCMD_DATA1_BASE_IDX 1 1028#define mmSDMA6_RLC7_MIDCMD_DATA2 0x03da 1029#define mmSDMA6_RLC7_MIDCMD_DATA2_BASE_IDX 1 1030#define mmSDMA6_RLC7_MIDCMD_DATA3 0x03db 1031#define mmSDMA6_RLC7_MIDCMD_DATA3_BASE_IDX 1 1032#define mmSDMA6_RLC7_MIDCMD_DATA4 0x03dc 1033#define mmSDMA6_RLC7_MIDCMD_DATA4_BASE_IDX 1 1034#define mmSDMA6_RLC7_MIDCMD_DATA5 0x03dd 1035#define mmSDMA6_RLC7_MIDCMD_DATA5_BASE_IDX 1 1036#define mmSDMA6_RLC7_MIDCMD_DATA6 0x03de 1037#define mmSDMA6_RLC7_MIDCMD_DATA6_BASE_IDX 1 1038#define mmSDMA6_RLC7_MIDCMD_DATA7 0x03df 1039#define mmSDMA6_RLC7_MIDCMD_DATA7_BASE_IDX 1 1040#define mmSDMA6_RLC7_MIDCMD_DATA8 0x03e0 1041#define mmSDMA6_RLC7_MIDCMD_DATA8_BASE_IDX 1 1042#define mmSDMA6_RLC7_MIDCMD_CNTL 0x03e1 1043#define mmSDMA6_RLC7_MIDCMD_CNTL_BASE_IDX 1 1044 1045#endif 1046