1/* $NetBSD: dce_11_2_enum.h,v 1.2 2021/12/18 23:45:10 riastradh Exp $ */ 2 3/* 4 * DCE_11_2 Register documentation 5 * 6 * Copyright (C) 2016 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included 16 * in all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 22 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26#ifndef DCE_11_2_ENUM_H 27#define DCE_11_2_ENUM_H 28 29typedef enum CRTC_CONTROL_CRTC_START_POINT_CNTL { 30 CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0x0, 31 CRTC_CONTROL_CRTC_START_POINT_CNTL_DP = 0x1, 32} CRTC_CONTROL_CRTC_START_POINT_CNTL; 33typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL { 34 CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0x0, 35 CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP = 0x1, 36} CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL; 37typedef enum CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL { 38 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE = 0x0, 39 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT= 0x1, 40 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED = 0x2, 41 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST= 0x3, 42} CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL; 43typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY { 44 CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE = 0x0, 45 CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE = 0x1, 46} CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY; 47typedef enum CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE { 48 CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE= 0x0, 49 CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE = 0x1, 50} CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE; 51typedef enum CRTC_CONTROL_CRTC_SOF_PULL_EN { 52 CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE = 0x0, 53 CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE = 0x1, 54} CRTC_CONTROL_CRTC_SOF_PULL_EN; 55typedef enum CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL { 56 CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE = 0x0, 57 CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE = 0x1, 58} CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL; 59typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL { 60 CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE = 0x0, 61 CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE = 0x1, 62} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL; 63typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL { 64 CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE = 0x0, 65 CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE = 0x1, 66} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL; 67typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN { 68 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE= 0x0, 69 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE= 0x1, 70} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN; 71typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC { 72 CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE= 0x0, 73 CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE= 0x1, 74} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC; 75typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT { 76 CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE= 0x0, 77 CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE= 0x1, 78} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT; 79typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK { 80 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_FRAME_START= 0x0, 81 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CRTC_TRIG_A= 0x1, 82 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CRTC_TRIG_B= 0x2, 83 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CURSOR_CHANGE= 0x3, 84 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_OTHER_CLIENT= 0x4, 85 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION0= 0x5, 86 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION1= 0x6, 87 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION2= 0x7, 88 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION3= 0x8, 89 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_GRAPHIC_UPDATE_PENDING= 0x9, 90 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_RESERVED2= 0xa, 91 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_INVALID= 0xb, 92 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_DOUBLE_BUFFER= 0xc, 93 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_D1CRTC_VERT_COUNT_NOM= 0xd, 94 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_D1CRTC_VERT_COUNT= 0xe, 95 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_RESERVED= 0xf, 96} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK; 97typedef enum CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK { 98 CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE= 0x0, 99 CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE= 0x1, 100} CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK; 101typedef enum CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR { 102 CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE= 0x0, 103 CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE= 0x1, 104} CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR; 105typedef enum CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL { 106 CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE = 0x0, 107 CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE = 0x1, 108} CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL; 109typedef enum CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN { 110 CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE = 0x0, 111 CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE = 0x1, 112} CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN; 113typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT { 114 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER= 0x1, 115 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER= 0x2, 116 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF= 0x5, 117 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE= 0x6, 118 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA = 0x7, 119 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA = 0x8, 120 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB = 0x9, 121 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB = 0xa, 122 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1 = 0xb, 123 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2 = 0xc, 124 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD= 0xd, 125 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC= 0xe, 126 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0 = 0x10, 127 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1 = 0x11, 128 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2 = 0x12, 129 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON = 0x13, 130 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA= 0x14, 131 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB= 0x15, 132 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW= 0x16, 133 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW= 0x17, 134} CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT; 135typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT { 136 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE= 0x1, 137 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA= 0x2, 138 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB= 0x3, 139 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA= 0x4, 140 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB= 0x5, 141 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO = 0x6, 142 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC= 0x7, 143} CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT; 144typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN { 145 CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE= 0x0, 146 CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x1, 147} CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN; 148typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR { 149 CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE = 0x0, 150 CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE = 0x1, 151} CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR; 152typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT { 153 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER= 0x1, 154 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER= 0x2, 155 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF= 0x5, 156 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE= 0x6, 157 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA = 0x7, 158 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA = 0x8, 159 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB = 0x9, 160 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB = 0xa, 161 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1 = 0xb, 162 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2 = 0xc, 163 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD= 0xd, 164 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC= 0xe, 165 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0 = 0x10, 166 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1 = 0x11, 167 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2 = 0x12, 168 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON = 0x13, 169 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA= 0x14, 170 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB= 0x15, 171 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW= 0x16, 172 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW= 0x17, 173} CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT; 174typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT { 175 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE= 0x1, 176 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA= 0x2, 177 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB= 0x3, 178 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA= 0x4, 179 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB= 0x5, 180 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO = 0x6, 181 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC= 0x7, 182} CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT; 183typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN { 184 CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE= 0x0, 185 CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x1, 186} CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN; 187typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR { 188 CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE = 0x0, 189 CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE = 0x1, 190} CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR; 191typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE { 192 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE= 0x0, 193 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT= 0x1, 194 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT= 0x2, 195 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED= 0x3, 196} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE; 197typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK { 198 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE= 0x0, 199 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE= 0x1, 200} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK; 201typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL { 202 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE= 0x0, 203 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE= 0x1, 204} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL; 205typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR { 206 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE= 0x0, 207 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE= 0x1, 208} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR; 209typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT { 210 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0= 0x0, 211 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF= 0x1, 212 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE= 0x2, 213 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1= 0x3, 214 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2= 0x4, 215 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA= 0x5, 216 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK= 0x6, 217 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA= 0x7, 218 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK= 0x8, 219 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK= 0x9, 220 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL= 0xa, 221 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1= 0xb, 222 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB= 0xc, 223 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA= 0xd, 224 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD= 0xe, 225 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC= 0xf, 226} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT; 227typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY { 228 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE= 0x0, 229 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE= 0x1, 230} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY; 231typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY { 232 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE= 0x0, 233 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE= 0x1, 234} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY; 235typedef enum CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE { 236 CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO= 0x0, 237 CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT= 0x1, 238 CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT= 0x2, 239 CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED= 0x3, 240} CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE; 241typedef enum CRTC_CONTROL_CRTC_MASTER_EN { 242 CRTC_CONTROL_CRTC_MASTER_EN_FALSE = 0x0, 243 CRTC_CONTROL_CRTC_MASTER_EN_TRUE = 0x1, 244} CRTC_CONTROL_CRTC_MASTER_EN; 245typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN { 246 CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE = 0x0, 247 CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE = 0x1, 248} CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN; 249typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE { 250 CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE = 0x0, 251 CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE = 0x1, 252} CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE; 253typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE { 254 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE= 0x0, 255 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE= 0x1, 256} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE; 257typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD { 258 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT= 0x0, 259 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD= 0x1, 260 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN= 0x2, 261 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2= 0x3, 262} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD; 263typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY { 264 CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE= 0x0, 265 CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE= 0x1, 266} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY; 267typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT { 268 CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE= 0x0, 269 CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE= 0x1, 270} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT; 271typedef enum CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN { 272 CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE = 0x0, 273 CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE = 0x1, 274} CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN; 275typedef enum CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE { 276 CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE= 0x0, 277 CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE= 0x1, 278} CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE; 279typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR { 280 CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE= 0x0, 281 CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE= 0x1, 282} CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR; 283typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE { 284 CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE= 0x0, 285 CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA= 0x1, 286 CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB= 0x2, 287 CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED= 0x3, 288} CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE; 289typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY { 290 CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE= 0x0, 291 CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE= 0x1, 292} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY; 293typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY { 294 CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE= 0x0, 295 CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE= 0x1, 296} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY; 297typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY { 298 CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE= 0x0, 299 CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE= 0x1, 300} CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY; 301typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EN { 302 CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE = 0x0, 303 CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE = 0x1, 304} CRTC_STEREO_CONTROL_CRTC_STEREO_EN; 305typedef enum CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR { 306 CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE = 0x0, 307 CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE = 0x1, 308} CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR; 309typedef enum CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL { 310 CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE= 0x0, 311 CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA= 0x1, 312 CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB= 0x2, 313 CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED= 0x3, 314} CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL; 315typedef enum CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY { 316 CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE= 0x0, 317 CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE= 0x1, 318} CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY; 319typedef enum CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY { 320 CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE= 0x0, 321 CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE= 0x1, 322} CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY; 323typedef enum CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN { 324 CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE= 0x0, 325 CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE= 0x1, 326} CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN; 327typedef enum CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN { 328 CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE = 0x0, 329 CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE = 0x1, 330} CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN; 331typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK { 332 CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE= 0x0, 333 CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE= 0x1, 334} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK; 335typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE { 336 CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE= 0x0, 337 CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE= 0x1, 338} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE; 339typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK { 340 CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE= 0x0, 341 CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE= 0x1, 342} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK; 343typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE { 344 CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE= 0x0, 345 CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE= 0x1, 346} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE; 347typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK { 348 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE= 0x0, 349 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE= 0x1, 350} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK; 351typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE { 352 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE= 0x0, 353 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE= 0x1, 354} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE; 355typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK { 356 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE= 0x0, 357 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE= 0x1, 358} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK; 359typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE { 360 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE= 0x0, 361 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE= 0x1, 362} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE; 363typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK { 364 CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE = 0x0, 365 CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE = 0x1, 366} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK; 367typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE { 368 CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE = 0x0, 369 CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE = 0x1, 370} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE; 371typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK { 372 CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE = 0x0, 373 CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE = 0x1, 374} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK; 375typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE { 376 CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE = 0x0, 377 CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE = 0x1, 378} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE; 379typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK { 380 CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE= 0x0, 381 CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE= 0x1, 382} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK; 383typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE { 384 CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE= 0x0, 385 CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE= 0x1, 386} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE; 387typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK { 388 CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE= 0x0, 389 CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE= 0x1, 390} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK; 391typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE { 392 CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE= 0x0, 393 CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE= 0x1, 394} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE; 395typedef enum CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK { 396 CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE = 0x0, 397 CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE = 0x1, 398} CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK; 399typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY { 400 CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE= 0x0, 401 CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE= 0x1, 402} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY; 403typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN { 404 CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE= 0x0, 405 CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE= 0x1, 406} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN; 407typedef enum CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE { 408 CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE= 0x0, 409 CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE= 0x1, 410} CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE; 411typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN { 412 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE= 0x0, 413 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE= 0x1, 414} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN; 415typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE { 416 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB= 0x0, 417 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601= 0x1, 418 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709= 0x2, 419 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS= 0x3, 420 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS= 0x4, 421 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB= 0x5, 422 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB= 0x6, 423 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS= 0x7, 424} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE; 425typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE { 426 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE= 0x0, 427 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE= 0x1, 428} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE; 429typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT { 430 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC= 0x0, 431 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC= 0x1, 432 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC= 0x2, 433 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED= 0x3, 434} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT; 435typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK { 436 MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0x0, 437 MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 0x1, 438} MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK; 439typedef enum MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK { 440 MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE= 0x0, 441 MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE= 0x1, 442} MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK; 443typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK { 444 MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE = 0x0, 445 MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE = 0x1, 446} MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK; 447typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_MODE { 448 MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN = 0x0, 449 MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA = 0x1, 450 MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA = 0x2, 451 MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE = 0x3, 452} MASTER_UPDATE_MODE_MASTER_UPDATE_MODE; 453typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE { 454 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH= 0x0, 455 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN= 0x1, 456 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD= 0x2, 457 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED= 0x3, 458} MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE; 459typedef enum CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE { 460 CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE= 0x0, 461 CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG= 0x1, 462 CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL= 0x2, 463} CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE; 464typedef enum CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR { 465 CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE = 0x0, 466 CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE = 0x1, 467} CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR; 468typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR { 469 CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE= 0x0, 470 CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE= 0x1, 471} CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR; 472typedef enum CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR { 473 CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE= 0x0, 474 CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE= 0x1, 475} CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR; 476typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY { 477 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE= 0x0, 478 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE= 0x1, 479} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY; 480typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE { 481 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE= 0x0, 482 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE= 0x1, 483} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE; 484typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR { 485 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE= 0x0, 486 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE= 0x1, 487} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR; 488typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE { 489 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE= 0x0, 490 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE= 0x1, 491} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE; 492typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR { 493 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE= 0x0, 494 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE= 0x1, 495} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR; 496typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE { 497 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE= 0x0, 498 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE= 0x1, 499} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE; 500typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE { 501 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE= 0x0, 502 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE= 0x1, 503} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE; 504typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR { 505 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE= 0x0, 506 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE= 0x1, 507} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR; 508typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE { 509 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE= 0x0, 510 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE= 0x1, 511} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE; 512typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE { 513 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE= 0x0, 514 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE= 0x1, 515} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE; 516typedef enum CRTC_CRC_CNTL_CRTC_CRC_EN { 517 CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE = 0x0, 518 CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE = 0x1, 519} CRTC_CRC_CNTL_CRTC_CRC_EN; 520typedef enum CRTC_CRC_CNTL_CRTC_CRC_CONT_EN { 521 CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE = 0x0, 522 CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE = 0x1, 523} CRTC_CRC_CNTL_CRTC_CRC_CONT_EN; 524typedef enum CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE { 525 CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT = 0x0, 526 CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT = 0x1, 527 CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES = 0x2, 528 CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS = 0x3, 529} CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE; 530typedef enum CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE { 531 CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP = 0x0, 532 CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM = 0x1, 533 CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM= 0x2, 534 CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD = 0x3, 535} CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE; 536typedef enum CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS { 537 CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE= 0x0, 538 CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE= 0x1, 539} CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS; 540typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT { 541 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB = 0x0, 542 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B = 0x1, 543 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB = 0x2, 544 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B = 0x3, 545 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB = 0x4, 546 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B = 0x5, 547 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB = 0x6, 548 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B = 0x7, 549} CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT; 550typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT { 551 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB = 0x0, 552 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B = 0x1, 553 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB = 0x2, 554 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B = 0x3, 555 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB = 0x4, 556 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B = 0x5, 557 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB = 0x6, 558 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B = 0x7, 559} CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT; 560typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE { 561 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_DISABLE= 0x0, 562 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_ONESHOT= 0x1, 563 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_CONTINUOUS= 0x2, 564 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_RESERVED= 0x3, 565} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE; 566typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE { 567 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE= 0x0, 568 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE= 0x1, 569} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE; 570typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE { 571 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE= 0x0, 572 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE= 0x1, 573} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE; 574typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW { 575 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel= 0x0, 576 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel= 0x1, 577 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel= 0x2, 578 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel= 0x3, 579} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW; 580typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE { 581 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE= 0x0, 582 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE= 0x1, 583} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE; 584typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE { 585 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE= 0x0, 586 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE= 0x1, 587} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE; 588typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY { 589 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE= 0x0, 590 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE= 0x1, 591} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY; 592typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY { 593 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE= 0x0, 594 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE= 0x1, 595} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY; 596typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE { 597 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE= 0x0, 598 CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE= 0x1, 599} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE; 600typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE { 601 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE= 0x0, 602 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE= 0x1, 603} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE; 604typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR { 605 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE= 0x0, 606 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE= 0x1, 607} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR; 608typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE { 609 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE= 0x0, 610 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE= 0x1, 611} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE; 612typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT { 613 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME= 0x0, 614 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME= 0x1, 615 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME= 0x2, 616 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME= 0x3, 617 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME= 0x4, 618 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME= 0x5, 619 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME= 0x6, 620 CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME= 0x7, 621} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT; 622typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE { 623 CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_FALSE= 0x0, 624 CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_TRUE= 0x1, 625} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE; 626typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR { 627 CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_FALSE= 0x0, 628 CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_TRUE= 0x1, 629} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR; 630typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE { 631 CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_FALSE= 0x0, 632 CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_TRUE= 0x1, 633} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE; 634typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE { 635 CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE= 0x0, 636 CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE= 0x1, 637} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE; 638typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR { 639 CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE= 0x0, 640 CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE= 0x1, 641} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR; 642typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE { 643 CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE= 0x0, 644 CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE= 0x1, 645} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE; 646typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE { 647 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE= 0x0, 648 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE= 0x1, 649} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE; 650typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR { 651 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE= 0x0, 652 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE= 0x1, 653} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR; 654typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE { 655 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE= 0x0, 656 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE= 0x1, 657} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE; 658typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE { 659 CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_FALSE= 0x0, 660 CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_TRUE= 0x1, 661} CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE; 662typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE { 663 CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_OFF= 0x0, 664 CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_ON= 0x1, 665} CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE; 666typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN { 667 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE= 0x0, 668 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE= 0x1, 669} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN; 670typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB { 671 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE= 0x0, 672 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE= 0x1, 673} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB; 674typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE { 675 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH= 0x0, 676 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE= 0x1, 677 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE= 0x2, 678 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED= 0x3, 679} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE; 680typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR { 681 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE= 0x0, 682 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE= 0x1, 683} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR; 684typedef enum CRTC_V_SYNC_A_POL { 685 CRTC_V_SYNC_A_POL_HIGH = 0x0, 686 CRTC_V_SYNC_A_POL_LOW = 0x1, 687} CRTC_V_SYNC_A_POL; 688typedef enum CRTC_H_SYNC_A_POL { 689 CRTC_H_SYNC_A_POL_HIGH = 0x0, 690 CRTC_H_SYNC_A_POL_LOW = 0x1, 691} CRTC_H_SYNC_A_POL; 692typedef enum CRTC_HORZ_REPETITION_COUNT { 693 CRTC_HORZ_REPETITION_COUNT_0 = 0x0, 694 CRTC_HORZ_REPETITION_COUNT_1 = 0x1, 695 CRTC_HORZ_REPETITION_COUNT_2 = 0x2, 696 CRTC_HORZ_REPETITION_COUNT_3 = 0x3, 697 CRTC_HORZ_REPETITION_COUNT_4 = 0x4, 698 CRTC_HORZ_REPETITION_COUNT_5 = 0x5, 699 CRTC_HORZ_REPETITION_COUNT_6 = 0x6, 700 CRTC_HORZ_REPETITION_COUNT_7 = 0x7, 701 CRTC_HORZ_REPETITION_COUNT_8 = 0x8, 702 CRTC_HORZ_REPETITION_COUNT_9 = 0x9, 703 CRTC_HORZ_REPETITION_COUNT_10 = 0xa, 704 CRTC_HORZ_REPETITION_COUNT_11 = 0xb, 705 CRTC_HORZ_REPETITION_COUNT_12 = 0xc, 706 CRTC_HORZ_REPETITION_COUNT_13 = 0xd, 707 CRTC_HORZ_REPETITION_COUNT_14 = 0xe, 708 CRTC_HORZ_REPETITION_COUNT_15 = 0xf, 709} CRTC_HORZ_REPETITION_COUNT; 710typedef enum PERFCOUNTER_CVALUE_SEL { 711 PERFCOUNTER_CVALUE_SEL_47_0 = 0x0, 712 PERFCOUNTER_CVALUE_SEL_15_0 = 0x1, 713 PERFCOUNTER_CVALUE_SEL_31_16 = 0x2, 714 PERFCOUNTER_CVALUE_SEL_47_32 = 0x3, 715 PERFCOUNTER_CVALUE_SEL_11_0 = 0x4, 716 PERFCOUNTER_CVALUE_SEL_23_12 = 0x5, 717 PERFCOUNTER_CVALUE_SEL_35_24 = 0x6, 718 PERFCOUNTER_CVALUE_SEL_47_36 = 0x7, 719} PERFCOUNTER_CVALUE_SEL; 720typedef enum PERFCOUNTER_INC_MODE { 721 PERFCOUNTER_INC_MODE_MULTI_BIT = 0x0, 722 PERFCOUNTER_INC_MODE_BOTH_EDGE = 0x1, 723 PERFCOUNTER_INC_MODE_LSB = 0x2, 724 PERFCOUNTER_INC_MODE_POS_EDGE = 0x3, 725} PERFCOUNTER_INC_MODE; 726typedef enum PERFCOUNTER_HW_CNTL_SEL { 727 PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0x0, 728 PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 0x1, 729} PERFCOUNTER_HW_CNTL_SEL; 730typedef enum PERFCOUNTER_RUNEN_MODE { 731 PERFCOUNTER_RUNEN_MODE_LEVEL = 0x0, 732 PERFCOUNTER_RUNEN_MODE_EDGE = 0x1, 733} PERFCOUNTER_RUNEN_MODE; 734typedef enum PERFCOUNTER_CNTOFF_START_DIS { 735 PERFCOUNTER_CNTOFF_START_ENABLE = 0x0, 736 PERFCOUNTER_CNTOFF_START_DISABLE = 0x1, 737} PERFCOUNTER_CNTOFF_START_DIS; 738typedef enum PERFCOUNTER_RESTART_EN { 739 PERFCOUNTER_RESTART_DISABLE = 0x0, 740 PERFCOUNTER_RESTART_ENABLE = 0x1, 741} PERFCOUNTER_RESTART_EN; 742typedef enum PERFCOUNTER_INT_EN { 743 PERFCOUNTER_INT_DISABLE = 0x0, 744 PERFCOUNTER_INT_ENABLE = 0x1, 745} PERFCOUNTER_INT_EN; 746typedef enum PERFCOUNTER_OFF_MASK { 747 PERFCOUNTER_OFF_MASK_DISABLE = 0x0, 748 PERFCOUNTER_OFF_MASK_ENABLE = 0x1, 749} PERFCOUNTER_OFF_MASK; 750typedef enum PERFCOUNTER_ACTIVE { 751 PERFCOUNTER_IS_IDLE = 0x0, 752 PERFCOUNTER_IS_ACTIVE = 0x1, 753} PERFCOUNTER_ACTIVE; 754typedef enum PERFCOUNTER_INT_TYPE { 755 PERFCOUNTER_INT_TYPE_LEVEL = 0x0, 756 PERFCOUNTER_INT_TYPE_PULSE = 0x1, 757} PERFCOUNTER_INT_TYPE; 758typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE { 759 PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0x0, 760 PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 0x1, 761} PERFCOUNTER_COUNTED_VALUE_TYPE; 762typedef enum PERFCOUNTER_CNTL_SEL { 763 PERFCOUNTER_CNTL_SEL_0 = 0x0, 764 PERFCOUNTER_CNTL_SEL_1 = 0x1, 765 PERFCOUNTER_CNTL_SEL_2 = 0x2, 766 PERFCOUNTER_CNTL_SEL_3 = 0x3, 767 PERFCOUNTER_CNTL_SEL_4 = 0x4, 768 PERFCOUNTER_CNTL_SEL_5 = 0x5, 769 PERFCOUNTER_CNTL_SEL_6 = 0x6, 770 PERFCOUNTER_CNTL_SEL_7 = 0x7, 771} PERFCOUNTER_CNTL_SEL; 772typedef enum PERFCOUNTER_CNT0_STATE { 773 PERFCOUNTER_CNT0_STATE_RESET = 0x0, 774 PERFCOUNTER_CNT0_STATE_START = 0x1, 775 PERFCOUNTER_CNT0_STATE_FREEZE = 0x2, 776 PERFCOUNTER_CNT0_STATE_HW = 0x3, 777} PERFCOUNTER_CNT0_STATE; 778typedef enum PERFCOUNTER_STATE_SEL0 { 779 PERFCOUNTER_STATE_SEL0_GLOBAL = 0x0, 780 PERFCOUNTER_STATE_SEL0_LOCAL = 0x1, 781} PERFCOUNTER_STATE_SEL0; 782typedef enum PERFCOUNTER_CNT1_STATE { 783 PERFCOUNTER_CNT1_STATE_RESET = 0x0, 784 PERFCOUNTER_CNT1_STATE_START = 0x1, 785 PERFCOUNTER_CNT1_STATE_FREEZE = 0x2, 786 PERFCOUNTER_CNT1_STATE_HW = 0x3, 787} PERFCOUNTER_CNT1_STATE; 788typedef enum PERFCOUNTER_STATE_SEL1 { 789 PERFCOUNTER_STATE_SEL1_GLOBAL = 0x0, 790 PERFCOUNTER_STATE_SEL1_LOCAL = 0x1, 791} PERFCOUNTER_STATE_SEL1; 792typedef enum PERFCOUNTER_CNT2_STATE { 793 PERFCOUNTER_CNT2_STATE_RESET = 0x0, 794 PERFCOUNTER_CNT2_STATE_START = 0x1, 795 PERFCOUNTER_CNT2_STATE_FREEZE = 0x2, 796 PERFCOUNTER_CNT2_STATE_HW = 0x3, 797} PERFCOUNTER_CNT2_STATE; 798typedef enum PERFCOUNTER_STATE_SEL2 { 799 PERFCOUNTER_STATE_SEL2_GLOBAL = 0x0, 800 PERFCOUNTER_STATE_SEL2_LOCAL = 0x1, 801} PERFCOUNTER_STATE_SEL2; 802typedef enum PERFCOUNTER_CNT3_STATE { 803 PERFCOUNTER_CNT3_STATE_RESET = 0x0, 804 PERFCOUNTER_CNT3_STATE_START = 0x1, 805 PERFCOUNTER_CNT3_STATE_FREEZE = 0x2, 806 PERFCOUNTER_CNT3_STATE_HW = 0x3, 807} PERFCOUNTER_CNT3_STATE; 808typedef enum PERFCOUNTER_STATE_SEL3 { 809 PERFCOUNTER_STATE_SEL3_GLOBAL = 0x0, 810 PERFCOUNTER_STATE_SEL3_LOCAL = 0x1, 811} PERFCOUNTER_STATE_SEL3; 812typedef enum PERFCOUNTER_CNT4_STATE { 813 PERFCOUNTER_CNT4_STATE_RESET = 0x0, 814 PERFCOUNTER_CNT4_STATE_START = 0x1, 815 PERFCOUNTER_CNT4_STATE_FREEZE = 0x2, 816 PERFCOUNTER_CNT4_STATE_HW = 0x3, 817} PERFCOUNTER_CNT4_STATE; 818typedef enum PERFCOUNTER_STATE_SEL4 { 819 PERFCOUNTER_STATE_SEL4_GLOBAL = 0x0, 820 PERFCOUNTER_STATE_SEL4_LOCAL = 0x1, 821} PERFCOUNTER_STATE_SEL4; 822typedef enum PERFCOUNTER_CNT5_STATE { 823 PERFCOUNTER_CNT5_STATE_RESET = 0x0, 824 PERFCOUNTER_CNT5_STATE_START = 0x1, 825 PERFCOUNTER_CNT5_STATE_FREEZE = 0x2, 826 PERFCOUNTER_CNT5_STATE_HW = 0x3, 827} PERFCOUNTER_CNT5_STATE; 828typedef enum PERFCOUNTER_STATE_SEL5 { 829 PERFCOUNTER_STATE_SEL5_GLOBAL = 0x0, 830 PERFCOUNTER_STATE_SEL5_LOCAL = 0x1, 831} PERFCOUNTER_STATE_SEL5; 832typedef enum PERFCOUNTER_CNT6_STATE { 833 PERFCOUNTER_CNT6_STATE_RESET = 0x0, 834 PERFCOUNTER_CNT6_STATE_START = 0x1, 835 PERFCOUNTER_CNT6_STATE_FREEZE = 0x2, 836 PERFCOUNTER_CNT6_STATE_HW = 0x3, 837} PERFCOUNTER_CNT6_STATE; 838typedef enum PERFCOUNTER_STATE_SEL6 { 839 PERFCOUNTER_STATE_SEL6_GLOBAL = 0x0, 840 PERFCOUNTER_STATE_SEL6_LOCAL = 0x1, 841} PERFCOUNTER_STATE_SEL6; 842typedef enum PERFCOUNTER_CNT7_STATE { 843 PERFCOUNTER_CNT7_STATE_RESET = 0x0, 844 PERFCOUNTER_CNT7_STATE_START = 0x1, 845 PERFCOUNTER_CNT7_STATE_FREEZE = 0x2, 846 PERFCOUNTER_CNT7_STATE_HW = 0x3, 847} PERFCOUNTER_CNT7_STATE; 848typedef enum PERFCOUNTER_STATE_SEL7 { 849 PERFCOUNTER_STATE_SEL7_GLOBAL = 0x0, 850 PERFCOUNTER_STATE_SEL7_LOCAL = 0x1, 851} PERFCOUNTER_STATE_SEL7; 852typedef enum PERFMON_STATE { 853 PERFMON_STATE_RESET = 0x0, 854 PERFMON_STATE_START = 0x1, 855 PERFMON_STATE_FREEZE = 0x2, 856 PERFMON_STATE_HW = 0x3, 857} PERFMON_STATE; 858typedef enum PERFMON_CNTOFF_AND_OR { 859 PERFMON_CNTOFF_OR = 0x0, 860 PERFMON_CNTOFF_AND = 0x1, 861} PERFMON_CNTOFF_AND_OR; 862typedef enum PERFMON_CNTOFF_INT_EN { 863 PERFMON_CNTOFF_INT_DISABLE = 0x0, 864 PERFMON_CNTOFF_INT_ENABLE = 0x1, 865} PERFMON_CNTOFF_INT_EN; 866typedef enum PERFMON_CNTOFF_INT_TYPE { 867 PERFMON_CNTOFF_INT_TYPE_LEVEL = 0x0, 868 PERFMON_CNTOFF_INT_TYPE_PULSE = 0x1, 869} PERFMON_CNTOFF_INT_TYPE; 870typedef enum ENABLE { 871 DISABLE_THE_FEATURE = 0x0, 872 ENABLE_THE_FEATURE = 0x1, 873} ENABLE; 874typedef enum ENABLE_CLOCK { 875 DISABLE_THE_CLOCK = 0x0, 876 ENABLE_THE_CLOCK = 0x1, 877} ENABLE_CLOCK; 878typedef enum FORCE_VBI { 879 FORCE_VBI_LOW = 0x0, 880 FORCE_VBI_HIGH = 0x1, 881} FORCE_VBI; 882typedef enum OVERRIDE_CGTT_SCLK { 883 OVERRIDE_CGTT_SCLK_NOOP = 0x0, 884 SET_OVERRIDE_CGTT_SCLK = 0x1, 885} OVERRIDE_CGTT_SCLK; 886typedef enum CLEAR_SMU_INTR { 887 SMU_INTR_STATUS_NOOP = 0x0, 888 SMU_INTR_STATUS_CLEAR = 0x1, 889} CLEAR_SMU_INTR; 890typedef enum STATIC_SCREEN_SMU_INTR { 891 STATIC_SCREEN_SMU_INTR_NOOP = 0x0, 892 SET_STATIC_SCREEN_SMU_INTR = 0x1, 893} STATIC_SCREEN_SMU_INTR; 894typedef enum JITTER_REMOVE_DISABLE { 895 ENABLE_JITTER_REMOVAL = 0x0, 896 DISABLE_JITTER_REMOVAL = 0x1, 897} JITTER_REMOVE_DISABLE; 898typedef enum DISABLE_CLOCK_GATING { 899 CLOCK_GATING_ENABLED = 0x0, 900 CLOCK_GATING_DISABLED = 0x1, 901} DISABLE_CLOCK_GATING; 902typedef enum DISABLE_CLOCK_GATING_IN_DCO { 903 CLOCK_GATING_ENABLED_IN_DCO = 0x0, 904 CLOCK_GATING_DISABLED_IN_DCO = 0x1, 905} DISABLE_CLOCK_GATING_IN_DCO; 906typedef enum DCCG_DEEP_COLOR_CNTL { 907 DCCG_DEEP_COLOR_DTO_DISABLE = 0x0, 908 DCCG_DEEP_COLOR_DTO_5_4_RATIO = 0x1, 909 DCCG_DEEP_COLOR_DTO_3_2_RATIO = 0x2, 910 DCCG_DEEP_COLOR_DTO_2_1_RATIO = 0x3, 911} DCCG_DEEP_COLOR_CNTL; 912typedef enum REFCLK_CLOCK_EN { 913 REFCLK_CLOCK_EN_PCIE_REFCLK = 0x0, 914 REFCLK_CLOCK_EN_ALLOW_SRC = 0x1, 915} REFCLK_CLOCK_EN; 916typedef enum REFCLK_SRC_SEL { 917 REFCLK_SRC_SEL_XTALIN = 0x0, 918 REFCLK_SRC_SEL_DISPPLL = 0x1, 919} REFCLK_SRC_SEL; 920typedef enum DPREFCLK_SRC_SEL { 921 DPREFCLK_SRC_SEL_CK = 0x0, 922 DPREFCLK_SRC_SEL_P0PLL = 0x1, 923 DPREFCLK_SRC_SEL_P1PLL = 0x2, 924 DPREFCLK_SRC_SEL_P2PLL = 0x3, 925 DPREFCLK_SRC_SEL_P3PLL = 0x4, 926} DPREFCLK_SRC_SEL; 927typedef enum XTAL_REF_SEL { 928 XTAL_REF_SEL_1X = 0x0, 929 XTAL_REF_SEL_2X = 0x1, 930} XTAL_REF_SEL; 931typedef enum XTAL_REF_CLOCK_SOURCE_SEL { 932 XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0x0, 933 XTAL_REF_CLOCK_SOURCE_SEL_PPLL = 0x1, 934} XTAL_REF_CLOCK_SOURCE_SEL; 935typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL { 936 MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x0, 937 MICROSECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK = 0x1, 938} MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL; 939typedef enum ALLOW_SR_ON_TRANS_REQ { 940 ALLOW_SR_ON_TRANS_REQ_ENABLE = 0x0, 941 ALLOW_SR_ON_TRANS_REQ_DISABLE = 0x1, 942} ALLOW_SR_ON_TRANS_REQ; 943typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL { 944 MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x0, 945 MILLISECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK = 0x1, 946} MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL; 947typedef enum PIPE_PIXEL_RATE_SOURCE { 948 PIPE_PIXEL_RATE_SOURCE_P0PLL = 0x0, 949 PIPE_PIXEL_RATE_SOURCE_P1PLL = 0x1, 950 PIPE_PIXEL_RATE_SOURCE_P2PLL = 0x2, 951} PIPE_PIXEL_RATE_SOURCE; 952typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE { 953 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0x0, 954 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 0x1, 955 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 0x2, 956 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 0x3, 957 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE = 0x4, 958 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF = 0x5, 959 PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYG = 0x6, 960} PIPE_PHYPLL_PIXEL_RATE_SOURCE; 961typedef enum PIPE_PIXEL_RATE_PLL_SOURCE { 962 PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0x0, 963 PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 0x1, 964} PIPE_PIXEL_RATE_PLL_SOURCE; 965typedef enum DP_DTO_DS_DISABLE { 966 DP_DTO_DESPREAD_DISABLE = 0x0, 967 DP_DTO_DESPREAD_ENABLE = 0x1, 968} DP_DTO_DS_DISABLE; 969typedef enum CRTC_ADD_PIXEL { 970 CRTC_ADD_PIXEL_NOOP = 0x0, 971 CRTC_ADD_PIXEL_FORCE = 0x1, 972} CRTC_ADD_PIXEL; 973typedef enum CRTC_DROP_PIXEL { 974 CRTC_DROP_PIXEL_NOOP = 0x0, 975 CRTC_DROP_PIXEL_FORCE = 0x1, 976} CRTC_DROP_PIXEL; 977typedef enum SYMCLK_FE_FORCE_EN { 978 SYMCLK_FE_FORCE_EN_DISABLE = 0x0, 979 SYMCLK_FE_FORCE_EN_ENABLE = 0x1, 980} SYMCLK_FE_FORCE_EN; 981typedef enum SYMCLK_FE_FORCE_SRC { 982 SYMCLK_FE_FORCE_SRC_UNIPHYA = 0x0, 983 SYMCLK_FE_FORCE_SRC_UNIPHYB = 0x1, 984 SYMCLK_FE_FORCE_SRC_UNIPHYC = 0x2, 985 SYMCLK_FE_FORCE_SRC_UNIPHYD = 0x3, 986 SYMCLK_FE_FORCE_SRC_UNIPHYE = 0x4, 987 SYMCLK_FE_FORCE_SRC_UNIPHYF = 0x5, 988 SYMCLK_FE_FORCE_SRC_UNIPHYG = 0x6, 989} SYMCLK_FE_FORCE_SRC; 990typedef enum DPDBG_CLK_FORCE_EN { 991 DPDBG_CLK_FORCE_EN_DISABLE = 0x0, 992 DPDBG_CLK_FORCE_EN_ENABLE = 0x1, 993} DPDBG_CLK_FORCE_EN; 994typedef enum DVOACLK_COARSE_SKEW_CNTL { 995 DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT = 0x0, 996 DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP = 0x1, 997 DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS = 0x2, 998 DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS = 0x3, 999 DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS = 0x4, 1000 DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS = 0x5, 1001 DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS = 0x6, 1002 DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS = 0x7, 1003 DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS = 0x8, 1004 DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS = 0x9, 1005 DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS = 0xa, 1006 DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS = 0xb, 1007 DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS = 0xc, 1008 DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS = 0xd, 1009 DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS = 0xe, 1010 DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS = 0xf, 1011 DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP = 0x10, 1012 DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS = 0x11, 1013 DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS = 0x12, 1014 DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS = 0x13, 1015 DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS = 0x14, 1016 DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS = 0x15, 1017 DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS = 0x16, 1018 DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS = 0x17, 1019 DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS = 0x18, 1020 DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS = 0x19, 1021 DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS = 0x1a, 1022 DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS = 0x1b, 1023 DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS = 0x1c, 1024 DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS = 0x1d, 1025 DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS = 0x1e, 1026} DVOACLK_COARSE_SKEW_CNTL; 1027typedef enum DVOACLK_FINE_SKEW_CNTL { 1028 DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT = 0x0, 1029 DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP = 0x1, 1030 DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS = 0x2, 1031 DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS = 0x3, 1032 DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP = 0x4, 1033 DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS = 0x5, 1034 DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS = 0x6, 1035 DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS = 0x7, 1036} DVOACLK_FINE_SKEW_CNTL; 1037typedef enum DVOACLKD_IN_PHASE { 1038 DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x0, 1039 DVOACLKD_IN_PHASE_WITH_PCLK_DVO = 0x1, 1040} DVOACLKD_IN_PHASE; 1041typedef enum DVOACLKC_IN_PHASE { 1042 DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x0, 1043 DVOACLKC_IN_PHASE_WITH_PCLK_DVO = 0x1, 1044} DVOACLKC_IN_PHASE; 1045typedef enum DVOACLKC_MVP_IN_PHASE { 1046 DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x0, 1047 DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO = 0x1, 1048} DVOACLKC_MVP_IN_PHASE; 1049typedef enum DVOACLKC_MVP_SKEW_PHASE_OVERRIDE { 1050 DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0x0, 1051 DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE = 0x1, 1052} DVOACLKC_MVP_SKEW_PHASE_OVERRIDE; 1053typedef enum MVP_CLK_SRC_SEL { 1054 MVP_CLK_SRC_SEL_RSRV = 0x0, 1055 MVP_CLK_SRC_SEL_IO_1 = 0x1, 1056 MVP_CLK_SRC_SEL_IO_2 = 0x2, 1057 MVP_CLK_SRC_SEL_REFCLK = 0x3, 1058} MVP_CLK_SRC_SEL; 1059typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL { 1060 DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC0 = 0x0, 1061 DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC1 = 0x1, 1062 DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC2 = 0x2, 1063 DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC3 = 0x3, 1064 DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC4 = 0x4, 1065 DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC5 = 0x5, 1066 DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 0x6, 1067} DCCG_AUDIO_DTO0_SOURCE_SEL; 1068typedef enum DCCG_AUDIO_DTO_SEL { 1069 DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0x0, 1070 DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 0x1, 1071 DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 0x2, 1072} DCCG_AUDIO_DTO_SEL; 1073typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL { 1074 DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0x0, 1075 DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1 = 0x1, 1076} DCCG_AUDIO_DTO2_SOURCE_SEL; 1077typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO { 1078 DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0x0, 1079 DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 0x1, 1080} DCCG_AUDIO_DTO_USE_512FBR_DTO; 1081typedef enum DCCG_DBG_EN { 1082 DCCG_DBG_EN_DISABLE = 0x0, 1083 DCCG_DBG_EN_ENABLE = 0x1, 1084} DCCG_DBG_EN; 1085typedef enum DCCG_DBG_BLOCK_SEL { 1086 DCCG_DBG_BLOCK_SEL_DCCG = 0x0, 1087 DCCG_DBG_BLOCK_SEL_PMON = 0x1, 1088 DCCG_DBG_BLOCK_SEL_PMON2 = 0x2, 1089} DCCG_DBG_BLOCK_SEL; 1090typedef enum DCCG_DBG_CLOCK_SEL { 1091 DCCG_DBG_CLOCK_SEL_DISPCLK = 0x0, 1092 DCCG_DBG_CLOCK_SEL_SCLK = 0x1, 1093 DCCG_DBG_CLOCK_SEL_MVPCLK = 0x2, 1094 DCCG_DBG_CLOCK_SEL_DVOCLK = 0x3, 1095 DCCG_DBG_CLOCK_SEL_DACCLK = 0x4, 1096 DCCG_DBG_CLOCK_SEL_REFCLK = 0x5, 1097 DCCG_DBG_CLOCK_SEL_SYMCLKA = 0x6, 1098 DCCG_DBG_CLOCK_SEL_SYMCLKB = 0x7, 1099 DCCG_DBG_CLOCK_SEL_SYMCLKC = 0x8, 1100 DCCG_DBG_CLOCK_SEL_SYMCLKD = 0x9, 1101 DCCG_DBG_CLOCK_SEL_SYMCLKE = 0xa, 1102 DCCG_DBG_CLOCK_SEL_SYMCLKG = 0xb, 1103 DCCG_DBG_CLOCK_SEL_SYMCLKF = 0xc, 1104 DCCG_DBG_CLOCK_SEL_RSRV = 0xd, 1105 DCCG_DBG_CLOCK_SEL_AOMCLK0 = 0xe, 1106 DCCG_DBG_CLOCK_SEL_AOMCLK1 = 0xf, 1107 DCCG_DBG_CLOCK_SEL_AOMCLK2 = 0x10, 1108 DCCG_DBG_CLOCK_SEL_DPREFCLK = 0x11, 1109 DCCG_DBG_CLOCK_SEL_UNB_DB_CLK = 0x12, 1110 DCCG_DBG_CLOCK_SEL_DSICLK = 0x13, 1111 DCCG_DBG_CLOCK_SEL_BYTECLK = 0x14, 1112 DCCG_DBG_CLOCK_SEL_ESCCLK = 0x15, 1113 DCCG_DBG_CLOCK_SEL_SYMCLKLPA = 0x16, 1114 DCCG_DBG_CLOCK_SEL_SYMCLKLPB = 0x17, 1115} DCCG_DBG_CLOCK_SEL; 1116typedef enum DCCG_DBG_OUT_BLOCK_SEL { 1117 DCCG_DBG_OUT_BLOCK_SEL_DCCG = 0x0, 1118 DCCG_DBG_OUT_BLOCK_SEL_DCO = 0x1, 1119 DCCG_DBG_OUT_BLOCK_SEL_DCIO = 0x2, 1120 DCCG_DBG_OUT_BLOCK_SEL_DSI = 0x3, 1121} DCCG_DBG_OUT_BLOCK_SEL; 1122typedef enum DISPCLK_FREQ_RAMP_DONE { 1123 DISPCLK_FREQ_RAMP_IN_PROGRESS = 0x0, 1124 DISPCLK_FREQ_RAMP_COMPLETED = 0x1, 1125} DISPCLK_FREQ_RAMP_DONE; 1126typedef enum DCCG_FIFO_ERRDET_RESET { 1127 DCCG_FIFO_ERRDET_RESET_NOOP = 0x0, 1128 DCCG_FIFO_ERRDET_RESET_FORCE = 0x1, 1129} DCCG_FIFO_ERRDET_RESET; 1130typedef enum DCCG_FIFO_ERRDET_STATE { 1131 DCCG_FIFO_ERRDET_STATE_DETECTION = 0x0, 1132 DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0x1, 1133} DCCG_FIFO_ERRDET_STATE; 1134typedef enum DCCG_FIFO_ERRDET_OVR_EN { 1135 DCCG_FIFO_ERRDET_OVR_DISABLE = 0x0, 1136 DCCG_FIFO_ERRDET_OVR_ENABLE = 0x1, 1137} DCCG_FIFO_ERRDET_OVR_EN; 1138typedef enum DISPCLK_CHG_FWD_CORR_DISABLE { 1139 DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0x0, 1140 DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 0x1, 1141} DISPCLK_CHG_FWD_CORR_DISABLE; 1142typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS { 1143 DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0x0, 1144 DC_MEM_GLOBAL_PWR_REQ_DISABLE = 0x1, 1145} DC_MEM_GLOBAL_PWR_REQ_DIS; 1146typedef enum DCCG_PERF_RUN { 1147 DCCG_PERF_RUN_NOOP = 0x0, 1148 DCCG_PERF_RUN_START = 0x1, 1149} DCCG_PERF_RUN; 1150typedef enum DCCG_PERF_MODE_VSYNC { 1151 DCCG_PERF_MODE_VSYNC_NOOP = 0x0, 1152 DCCG_PERF_MODE_VSYNC_START = 0x1, 1153} DCCG_PERF_MODE_VSYNC; 1154typedef enum DCCG_PERF_MODE_HSYNC { 1155 DCCG_PERF_MODE_HSYNC_NOOP = 0x0, 1156 DCCG_PERF_MODE_HSYNC_START = 0x1, 1157} DCCG_PERF_MODE_HSYNC; 1158typedef enum DCCG_PERF_CRTC_SELECT { 1159 DCCG_PERF_SEL_CRTC0 = 0x0, 1160 DCCG_PERF_SEL_CRTC1 = 0x1, 1161 DCCG_PERF_SEL_CRTC2 = 0x2, 1162 DCCG_PERF_SEL_CRTC3 = 0x3, 1163 DCCG_PERF_SEL_CRTC4 = 0x4, 1164 DCCG_PERF_SEL_CRTC5 = 0x5, 1165} DCCG_PERF_CRTC_SELECT; 1166typedef enum CLOCK_BRANCH_SOFT_RESET { 1167 CLOCK_BRANCH_SOFT_RESET_NOOP = 0x0, 1168 CLOCK_BRANCH_SOFT_RESET_FORCE = 0x1, 1169} CLOCK_BRANCH_SOFT_RESET; 1170typedef enum PLL_CFG_IF_SOFT_RESET { 1171 PLL_CFG_IF_SOFT_RESET_NOOP = 0x0, 1172 PLL_CFG_IF_SOFT_RESET_FORCE = 0x1, 1173} PLL_CFG_IF_SOFT_RESET; 1174typedef enum DVO_ENABLE_RST { 1175 DVO_ENABLE_RST_DISABLE = 0x0, 1176 DVO_ENABLE_RST_ENABLE = 0x1, 1177} DVO_ENABLE_RST; 1178typedef enum LptNumBanks { 1179 LPT_NUM_BANKS_2BANK = 0x0, 1180 LPT_NUM_BANKS_4BANK = 0x1, 1181 LPT_NUM_BANKS_8BANK = 0x2, 1182 LPT_NUM_BANKS_16BANK = 0x3, 1183 LPT_NUM_BANKS_32BANK = 0x4, 1184} LptNumBanks; 1185typedef enum DCIO_DC_GENERICA_SEL { 1186 DCIO_GENERICA_SEL_DACA_STEREOSYNC = 0x0, 1187 DCIO_GENERICA_SEL_STEREOSYNC = 0x1, 1188 DCIO_GENERICA_SEL_DACA_PIXCLK = 0x2, 1189 DCIO_GENERICA_SEL_DACB_PIXCLK = 0x3, 1190 DCIO_GENERICA_SEL_DVOA_CTL3 = 0x4, 1191 DCIO_GENERICA_SEL_P1_PLLCLK = 0x5, 1192 DCIO_GENERICA_SEL_P2_PLLCLK = 0x6, 1193 DCIO_GENERICA_SEL_DVOA_STEREOSYNC = 0x7, 1194 DCIO_GENERICA_SEL_DACA_FIELD_NUMBER = 0x8, 1195 DCIO_GENERICA_SEL_DACB_FIELD_NUMBER = 0x9, 1196 DCIO_GENERICA_SEL_GENERICA_DCCG = 0xa, 1197 DCIO_GENERICA_SEL_SYNCEN = 0xb, 1198 DCIO_GENERICA_SEL_GENERICA_SCG = 0xc, 1199 DCIO_GENERICA_SEL_RESERVED_VALUE13 = 0xd, 1200 DCIO_GENERICA_SEL_RESERVED_VALUE14 = 0xe, 1201 DCIO_GENERICA_SEL_RESERVED_VALUE15 = 0xf, 1202 DCIO_GENERICA_SEL_GENERICA_DPRX = 0x10, 1203 DCIO_GENERICA_SEL_GENERICB_DPRX = 0x11, 1204} DCIO_DC_GENERICA_SEL; 1205typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL { 1206 DCIO_UNIPHYA_TEST_REFDIV_CLK = 0x0, 1207 DCIO_UNIPHYB_TEST_REFDIV_CLK = 0x1, 1208 DCIO_UNIPHYC_TEST_REFDIV_CLK = 0x2, 1209 DCIO_UNIPHYD_TEST_REFDIV_CLK = 0x3, 1210 DCIO_UNIPHYE_TEST_REFDIV_CLK = 0x4, 1211 DCIO_UNIPHYF_TEST_REFDIV_CLK = 0x5, 1212 DCIO_UNIPHYG_TEST_REFDIV_CLK = 0x6, 1213 DCIO_UNIPHYLPA_TEST_REFDIV_CLK = 0x7, 1214 DCIO_UNIPHYLPB_TEST_REFDIV_CLK = 0x8, 1215} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL; 1216typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL { 1217 DCIO_UNIPHYA_FBDIV_CLK = 0x0, 1218 DCIO_UNIPHYB_FBDIV_CLK = 0x1, 1219 DCIO_UNIPHYC_FBDIV_CLK = 0x2, 1220 DCIO_UNIPHYD_FBDIV_CLK = 0x3, 1221 DCIO_UNIPHYE_FBDIV_CLK = 0x4, 1222 DCIO_UNIPHYF_FBDIV_CLK = 0x5, 1223 DCIO_UNIPHYG_FBDIV_CLK = 0x6, 1224 DCIO_UNIPHYLPA_FBDIV_CLK = 0x7, 1225 DCIO_UNIPHYLPB_FBDIV_CLK = 0x8, 1226} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL; 1227typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL { 1228 DCIO_UNIPHYA_FBDIV_SSC_CLK = 0x0, 1229 DCIO_UNIPHYB_FBDIV_SSC_CLK = 0x1, 1230 DCIO_UNIPHYC_FBDIV_SSC_CLK = 0x2, 1231 DCIO_UNIPHYD_FBDIV_SSC_CLK = 0x3, 1232 DCIO_UNIPHYE_FBDIV_SSC_CLK = 0x4, 1233 DCIO_UNIPHYF_FBDIV_SSC_CLK = 0x5, 1234 DCIO_UNIPHYG_FBDIV_SSC_CLK = 0x6, 1235 DCIO_UNIPHYLPA_FBDIV_SSC_CLK = 0x7, 1236 DCIO_UNIPHYLPB_FBDIV_SSC_CLK = 0x8, 1237} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL; 1238typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL { 1239 DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0x0, 1240 DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 0x1, 1241 DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 0x2, 1242 DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 0x3, 1243 DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 0x4, 1244 DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 0x5, 1245 DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 0x6, 1246 DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2 = 0x7, 1247 DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2 = 0x8, 1248} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL; 1249typedef enum DCIO_DC_GENERICB_SEL { 1250 DCIO_GENERICB_SEL_DACA_STEREOSYNC = 0x0, 1251 DCIO_GENERICB_SEL_STEREOSYNC = 0x1, 1252 DCIO_GENERICB_SEL_DACA_PIXCLK = 0x2, 1253 DCIO_GENERICB_SEL_DACB_PIXCLK = 0x3, 1254 DCIO_GENERICB_SEL_DVOA_CTL3 = 0x4, 1255 DCIO_GENERICB_SEL_P1_PLLCLK = 0x5, 1256 DCIO_GENERICB_SEL_P2_PLLCLK = 0x6, 1257 DCIO_GENERICB_SEL_DVOA_STEREOSYNC = 0x7, 1258 DCIO_GENERICB_SEL_DACA_FIELD_NUMBER = 0x8, 1259 DCIO_GENERICB_SEL_DACB_FIELD_NUMBER = 0x9, 1260 DCIO_GENERICB_SEL_GENERICB_DCCG = 0xa, 1261 DCIO_GENERICB_SEL_SYNCEN = 0xb, 1262 DCIO_GENERICB_SEL_GENERICA_SCG = 0xc, 1263 DCIO_GENERICB_SEL_RESERVED_VALUE13 = 0xd, 1264 DCIO_GENERICB_SEL_RESERVED_VALUE14 = 0xe, 1265 DCIO_GENERICB_SEL_RESERVED_VALUE15 = 0xf, 1266} DCIO_DC_GENERICB_SEL; 1267typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL { 1268 DCIO_DC_PAD_EXTERN_SIG_SEL_MVP = 0x0, 1269 DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA = 0x1, 1270 DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK = 0x2, 1271 DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC = 0x3, 1272 DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA = 0x4, 1273 DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB = 0x5, 1274 DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC = 0x6, 1275 DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1 = 0x7, 1276 DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2 = 0x8, 1277 DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK = 0x9, 1278 DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA = 0xa, 1279 DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK = 0xb, 1280 DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA = 0xc, 1281 DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1 = 0xd, 1282 DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0 = 0xe, 1283 DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL = 0xf, 1284} DCIO_DC_PAD_EXTERN_SIG_SEL; 1285typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS { 1286 DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA = 0x0, 1287 DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE = 0x1, 1288 DCIO_MVP_PIXEL_SRC_STATUS_CRTC = 0x2, 1289 DCIO_MVP_PIXEL_SRC_STATUS_LB = 0x3, 1290} DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS; 1291typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL { 1292 DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0x0, 1293 DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 0x1, 1294 DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 0x2, 1295 DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 0x3, 1296} DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL; 1297typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL { 1298 DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0x0, 1299 DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 0x1, 1300 DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 0x2, 1301 DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 0x3, 1302} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL; 1303typedef enum DCIO_DC_GPIO_VIP_DEBUG { 1304 DCIO_DC_GPIO_VIP_DEBUG_NORMAL = 0x0, 1305 DCIO_DC_GPIO_VIP_DEBUG_CG_BIG = 0x1, 1306} DCIO_DC_GPIO_VIP_DEBUG; 1307typedef enum DCIO_DC_GPIO_MACRO_DEBUG { 1308 DCIO_DC_GPIO_MACRO_DEBUG_NORMAL = 0x0, 1309 DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF = 0x1, 1310 DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2 = 0x2, 1311 DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3 = 0x3, 1312} DCIO_DC_GPIO_MACRO_DEBUG; 1313typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL { 1314 DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL = 0x0, 1315 DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP = 0x1, 1316} DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL; 1317typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN { 1318 DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS = 0x0, 1319 DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE = 0x1, 1320} DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN; 1321typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE { 1322 DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0x0, 1323 DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 0x1, 1324} DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE; 1325typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION { 1326 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x0, 1327 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x1, 1328 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS= 0x2, 1329 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS= 0x3, 1330 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS= 0x4, 1331 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS= 0x5, 1332 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS= 0x6, 1333 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS= 0x7, 1334} DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION; 1335typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT { 1336 DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0x0, 1337 DCIO_UNIPHY_CHANNEL_INVERTED = 0x1, 1338} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT; 1339typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK { 1340 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0x0, 1341 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 0x1, 1342 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x2, 1343 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED= 0x3, 1344} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK; 1345typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE { 1346 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0x0, 1347 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 0x1, 1348 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 0x2, 1349 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 0x3, 1350} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE; 1351typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN { 1352 DCIO_VIP_MUX_EN_DVO = 0x0, 1353 DCIO_VIP_MUX_EN_VIP = 0x1, 1354} DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN; 1355typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN { 1356 DCIO_VIP_ALTER_MAPPING_EN_DEFAULT = 0x0, 1357 DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE = 0x1, 1358} DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN; 1359typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN { 1360 DCIO_DVO_ALTER_MAPPING_EN_DEFAULT = 0x0, 1361 DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE = 0x1, 1362} DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN; 1363typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN { 1364 DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE= 0x0, 1365 DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE= 0x1, 1366} DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN; 1367typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE { 1368 DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF = 0x0, 1369 DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON = 0x1, 1370} DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE; 1371typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL { 1372 DCIO_LVTMA_SYNCEN_POL_NON_INVERT = 0x0, 1373 DCIO_LVTMA_SYNCEN_POL_INVERT = 0x1, 1374} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL; 1375typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON { 1376 DCIO_LVTMA_DIGON_OFF = 0x0, 1377 DCIO_LVTMA_DIGON_ON = 0x1, 1378} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON; 1379typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL { 1380 DCIO_LVTMA_DIGON_POL_NON_INVERT = 0x0, 1381 DCIO_LVTMA_DIGON_POL_INVERT = 0x1, 1382} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL; 1383typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON { 1384 DCIO_LVTMA_BLON_OFF = 0x0, 1385 DCIO_LVTMA_BLON_ON = 0x1, 1386} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON; 1387typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL { 1388 DCIO_LVTMA_BLON_POL_NON_INVERT = 0x0, 1389 DCIO_LVTMA_BLON_POL_INVERT = 0x1, 1390} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL; 1391typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN { 1392 DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON = 0x0, 1393 DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE = 0x1, 1394} DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN; 1395typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN { 1396 DCIO_BL_PWM_FRACTIONAL_DISABLE = 0x0, 1397 DCIO_BL_PWM_FRACTIONAL_ENABLE = 0x1, 1398} DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN; 1399typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN { 1400 DCIO_BL_PWM_DISABLE = 0x0, 1401 DCIO_BL_PWM_ENABLE = 0x1, 1402} DCIO_BL_PWM_CNTL_BL_PWM_EN; 1403typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT { 1404 DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0x0, 1405 DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 0x1, 1406 DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 0x2, 1407 DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 0x3, 1408} DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT; 1409typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE { 1410 DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0x0, 1411 DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 0x1, 1412} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE; 1413typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN { 1414 DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL = 0x0, 1415 DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM = 0x1, 1416} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN; 1417typedef enum DCIO_BL_PWM_GRP1_REG_LOCK { 1418 DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE = 0x0, 1419 DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE = 0x1, 1420} DCIO_BL_PWM_GRP1_REG_LOCK; 1421typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START { 1422 DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0x0, 1423 DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 0x1, 1424} DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START; 1425typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL { 1426 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1= 0x0, 1427 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2= 0x1, 1428 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3= 0x2, 1429 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4= 0x3, 1430 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5= 0x4, 1431 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6= 0x5, 1432} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL; 1433typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN { 1434 DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x0, 1435 DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM= 0x1, 1436} DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN; 1437typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN { 1438 DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0x0, 1439 DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 0x1, 1440} DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; 1441typedef enum DCIO_GSL_SEL { 1442 DCIO_GSL_SEL_GROUP_0 = 0x0, 1443 DCIO_GSL_SEL_GROUP_1 = 0x1, 1444 DCIO_GSL_SEL_GROUP_2 = 0x2, 1445} DCIO_GSL_SEL; 1446typedef enum DCIO_GENLK_CLK_GSL_MASK { 1447 DCIO_GENLK_CLK_GSL_MASK_NO = 0x0, 1448 DCIO_GENLK_CLK_GSL_MASK_TIMING = 0x1, 1449 DCIO_GENLK_CLK_GSL_MASK_STEREO = 0x2, 1450} DCIO_GENLK_CLK_GSL_MASK; 1451typedef enum DCIO_GENLK_VSYNC_GSL_MASK { 1452 DCIO_GENLK_VSYNC_GSL_MASK_NO = 0x0, 1453 DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 0x1, 1454 DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 0x2, 1455} DCIO_GENLK_VSYNC_GSL_MASK; 1456typedef enum DCIO_SWAPLOCK_A_GSL_MASK { 1457 DCIO_SWAPLOCK_A_GSL_MASK_NO = 0x0, 1458 DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 0x1, 1459 DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 0x2, 1460} DCIO_SWAPLOCK_A_GSL_MASK; 1461typedef enum DCIO_SWAPLOCK_B_GSL_MASK { 1462 DCIO_SWAPLOCK_B_GSL_MASK_NO = 0x0, 1463 DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 0x1, 1464 DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 0x2, 1465} DCIO_SWAPLOCK_B_GSL_MASK; 1466typedef enum DCIO_GSL_VSYNC_SEL { 1467 DCIO_GSL_VSYNC_SEL_PIPE0 = 0x0, 1468 DCIO_GSL_VSYNC_SEL_PIPE1 = 0x1, 1469 DCIO_GSL_VSYNC_SEL_PIPE2 = 0x2, 1470 DCIO_GSL_VSYNC_SEL_PIPE3 = 0x3, 1471 DCIO_GSL_VSYNC_SEL_PIPE4 = 0x4, 1472 DCIO_GSL_VSYNC_SEL_PIPE5 = 0x5, 1473} DCIO_GSL_VSYNC_SEL; 1474typedef enum DCIO_GSL0_TIMING_SYNC_SEL { 1475 DCIO_GSL0_TIMING_SYNC_SEL_PIPE = 0x0, 1476 DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1, 1477 DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK = 0x2, 1478 DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3, 1479 DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4, 1480} DCIO_GSL0_TIMING_SYNC_SEL; 1481typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL { 1482 DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION = 0x0, 1483 DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1, 1484 DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2, 1485 DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3, 1486 DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4, 1487} DCIO_GSL0_GLOBAL_UNLOCK_SEL; 1488typedef enum DCIO_GSL1_TIMING_SYNC_SEL { 1489 DCIO_GSL1_TIMING_SYNC_SEL_PIPE = 0x0, 1490 DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1, 1491 DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK = 0x2, 1492 DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3, 1493 DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4, 1494} DCIO_GSL1_TIMING_SYNC_SEL; 1495typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL { 1496 DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION = 0x0, 1497 DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1, 1498 DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2, 1499 DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3, 1500 DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4, 1501} DCIO_GSL1_GLOBAL_UNLOCK_SEL; 1502typedef enum DCIO_GSL2_TIMING_SYNC_SEL { 1503 DCIO_GSL2_TIMING_SYNC_SEL_PIPE = 0x0, 1504 DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1, 1505 DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK = 0x2, 1506 DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3, 1507 DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4, 1508} DCIO_GSL2_TIMING_SYNC_SEL; 1509typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL { 1510 DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION = 0x0, 1511 DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1, 1512 DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2, 1513 DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3, 1514 DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4, 1515} DCIO_GSL2_GLOBAL_UNLOCK_SEL; 1516typedef enum DCIO_DC_GPU_TIMER_START_POSITION { 1517 DCIO_GPU_TIMER_START_0_END_27 = 0x0, 1518 DCIO_GPU_TIMER_START_1_END_28 = 0x1, 1519 DCIO_GPU_TIMER_START_2_END_29 = 0x2, 1520 DCIO_GPU_TIMER_START_3_END_30 = 0x3, 1521 DCIO_GPU_TIMER_START_4_END_31 = 0x4, 1522 DCIO_GPU_TIMER_START_6_END_33 = 0x5, 1523 DCIO_GPU_TIMER_START_8_END_35 = 0x6, 1524 DCIO_GPU_TIMER_START_10_END_37 = 0x7, 1525} DCIO_DC_GPU_TIMER_START_POSITION; 1526typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL { 1527 DCIO_TEST_CLK_SEL_DISPCLK = 0x0, 1528 DCIO_TEST_CLK_SEL_GATED_DISPCLK = 0x1, 1529 DCIO_TEST_CLK_SEL_SCLK = 0x2, 1530} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL; 1531typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS { 1532 DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0x0, 1533 DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 0x1, 1534} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS; 1535typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX { 1536 DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0x0, 1537 DCIO_EXT_VSYNC_MUX_CRTC0 = 0x1, 1538 DCIO_EXT_VSYNC_MUX_CRTC1 = 0x2, 1539 DCIO_EXT_VSYNC_MUX_CRTC2 = 0x3, 1540 DCIO_EXT_VSYNC_MUX_CRTC3 = 0x4, 1541 DCIO_EXT_VSYNC_MUX_CRTC4 = 0x5, 1542 DCIO_EXT_VSYNC_MUX_CRTC5 = 0x6, 1543 DCIO_EXT_VSYNC_MUX_GENERICB = 0x7, 1544} DCIO_DCO_DCFE_EXT_VSYNC_MUX; 1545typedef enum DCIO_DCO_EXT_VSYNC_MASK { 1546 DCIO_EXT_VSYNC_MASK_NONE = 0x0, 1547 DCIO_EXT_VSYNC_MASK_PIPE0 = 0x1, 1548 DCIO_EXT_VSYNC_MASK_PIPE1 = 0x2, 1549 DCIO_EXT_VSYNC_MASK_PIPE2 = 0x3, 1550 DCIO_EXT_VSYNC_MASK_PIPE3 = 0x4, 1551 DCIO_EXT_VSYNC_MASK_PIPE4 = 0x5, 1552 DCIO_EXT_VSYNC_MASK_PIPE5 = 0x6, 1553 DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 0x7, 1554} DCIO_DCO_EXT_VSYNC_MASK; 1555typedef enum DCIO_DBG_OUT_PIN_SEL { 1556 DCIO_DBG_OUT_PIN_SEL_LOW_12BIT = 0x0, 1557 DCIO_DBG_OUT_PIN_SEL_HIGH_12BIT = 0x1, 1558} DCIO_DBG_OUT_PIN_SEL; 1559typedef enum DCIO_DBG_OUT_12BIT_SEL { 1560 DCIO_DBG_OUT_12BIT_SEL_LOW_12BIT = 0x0, 1561 DCIO_DBG_OUT_12BIT_SEL_MID_12BIT = 0x1, 1562 DCIO_DBG_OUT_12BIT_SEL_HIGH_12BIT = 0x2, 1563 DCIO_DBG_OUT_12BIT_SEL_OVERRIDE = 0x3, 1564} DCIO_DBG_OUT_12BIT_SEL; 1565typedef enum DCIO_DSYNC_SOFT_RESET { 1566 DCIO_DSYNC_SOFT_RESET_DEASSERT = 0x0, 1567 DCIO_DSYNC_SOFT_RESET_ASSERT = 0x1, 1568} DCIO_DSYNC_SOFT_RESET; 1569typedef enum DCIO_DACA_SOFT_RESET { 1570 DCIO_DACA_SOFT_RESET_DEASSERT = 0x0, 1571 DCIO_DACA_SOFT_RESET_ASSERT = 0x1, 1572} DCIO_DACA_SOFT_RESET; 1573typedef enum DCIO_DCRXPHY_SOFT_RESET { 1574 DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0x0, 1575 DCIO_DCRXPHY_SOFT_RESET_ASSERT = 0x1, 1576} DCIO_DCRXPHY_SOFT_RESET; 1577typedef enum DCIO_DPHY_LANE_SEL { 1578 DCIO_DPHY_LANE_SEL_LANE0 = 0x0, 1579 DCIO_DPHY_LANE_SEL_LANE1 = 0x1, 1580 DCIO_DPHY_LANE_SEL_LANE2 = 0x2, 1581 DCIO_DPHY_LANE_SEL_LANE3 = 0x3, 1582} DCIO_DPHY_LANE_SEL; 1583typedef enum DCIO_DPCS_INTERRUPT_TYPE { 1584 DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0x0, 1585 DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 0x1, 1586} DCIO_DPCS_INTERRUPT_TYPE; 1587typedef enum DCIO_DPCS_INTERRUPT_MASK { 1588 DCIO_DPCS_INTERRUPT_DISABLE = 0x0, 1589 DCIO_DPCS_INTERRUPT_ENABLE = 0x1, 1590} DCIO_DPCS_INTERRUPT_MASK; 1591typedef enum DCIO_DC_GPU_TIMER_READ_SELECT { 1592 DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0x0, 1593 DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 0x1, 1594 DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE = 0x2, 1595 DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE = 0x3, 1596 DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE = 0x4, 1597 DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE = 0x5, 1598 DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE = 0x6, 1599 DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE = 0x7, 1600 DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE = 0x8, 1601 DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE = 0x9, 1602 DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE = 0xa, 1603 DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE = 0xb, 1604 DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 0xc, 1605 DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 0xd, 1606 DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP = 0xe, 1607 DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP = 0xf, 1608 DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP = 0x10, 1609 DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP = 0x11, 1610 DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP = 0x12, 1611 DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP = 0x13, 1612 DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP = 0x14, 1613 DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP = 0x15, 1614 DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP = 0x16, 1615 DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP = 0x17, 1616 DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 0x18, 1617 DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 0x19, 1618 DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM = 0x1a, 1619 DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM = 0x1b, 1620 DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM = 0x1c, 1621 DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM = 0x1d, 1622 DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM = 0x1e, 1623 DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM = 0x1f, 1624 DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM = 0x20, 1625 DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM = 0x21, 1626 DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM = 0x22, 1627 DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM = 0x23, 1628} DCIO_DC_GPU_TIMER_READ_SELECT; 1629typedef enum DCIO_IMPCAL_STEP_DELAY { 1630 DCIO_IMPCAL_STEP_DELAY_1us = 0x0, 1631 DCIO_IMPCAL_STEP_DELAY_2us = 0x1, 1632 DCIO_IMPCAL_STEP_DELAY_3us = 0x2, 1633 DCIO_IMPCAL_STEP_DELAY_4us = 0x3, 1634 DCIO_IMPCAL_STEP_DELAY_5us = 0x4, 1635 DCIO_IMPCAL_STEP_DELAY_6us = 0x5, 1636 DCIO_IMPCAL_STEP_DELAY_7us = 0x6, 1637 DCIO_IMPCAL_STEP_DELAY_8us = 0x7, 1638 DCIO_IMPCAL_STEP_DELAY_9us = 0x8, 1639 DCIO_IMPCAL_STEP_DELAY_10us = 0x9, 1640 DCIO_IMPCAL_STEP_DELAY_11us = 0xa, 1641 DCIO_IMPCAL_STEP_DELAY_12us = 0xb, 1642 DCIO_IMPCAL_STEP_DELAY_13us = 0xc, 1643 DCIO_IMPCAL_STEP_DELAY_14us = 0xd, 1644 DCIO_IMPCAL_STEP_DELAY_15us = 0xe, 1645 DCIO_IMPCAL_STEP_DELAY_16us = 0xf, 1646} DCIO_IMPCAL_STEP_DELAY; 1647typedef enum DCIO_UNIPHY_IMPCAL_SEL { 1648 DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0x0, 1649 DCIO_UNIPHY_IMPCAL_SEL_BINARY = 0x1, 1650} DCIO_UNIPHY_IMPCAL_SEL; 1651typedef enum DCIO_DBG_CLOCK_SEL { 1652 DCIO_DBG_CLOCK_SEL_DISPCLK = 0x0, 1653 DCIO_DBG_CLOCK_SEL_SYMCLKA = 0x1, 1654 DCIO_DBG_CLOCK_SEL_SYMCLKB = 0x2, 1655 DCIO_DBG_CLOCK_SEL_SYMCLKC = 0x3, 1656 DCIO_DBG_CLOCK_SEL_SYMCLKD = 0x4, 1657 DCIO_DBG_CLOCK_SEL_SYMCLKE = 0x5, 1658 DCIO_DBG_CLOCK_SEL_SYMCLKF = 0x6, 1659 DCIO_DBG_CLOCK_SEL_REFCLK = 0xb, 1660} DCIO_DBG_CLOCK_SEL; 1661typedef enum DCIOCHIP_HPD_SEL { 1662 DCIOCHIP_HPD_SEL_ASYNC = 0x0, 1663 DCIOCHIP_HPD_SEL_CLOCKED = 0x1, 1664} DCIOCHIP_HPD_SEL; 1665typedef enum DCIOCHIP_PAD_MODE { 1666 DCIOCHIP_PAD_MODE_DDC = 0x0, 1667 DCIOCHIP_PAD_MODE_DP = 0x1, 1668} DCIOCHIP_PAD_MODE; 1669typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE { 1670 DCIOCHIP_AUXSLAVE_PAD_MODE_I2C = 0x0, 1671 DCIOCHIP_AUXSLAVE_PAD_MODE_AUX = 0x1, 1672} DCIOCHIP_AUXSLAVE_PAD_MODE; 1673typedef enum DCIOCHIP_INVERT { 1674 DCIOCHIP_POL_NON_INVERT = 0x0, 1675 DCIOCHIP_POL_INVERT = 0x1, 1676} DCIOCHIP_INVERT; 1677typedef enum DCIOCHIP_PD_EN { 1678 DCIOCHIP_PD_EN_NOTALLOW = 0x0, 1679 DCIOCHIP_PD_EN_ALLOW = 0x1, 1680} DCIOCHIP_PD_EN; 1681typedef enum DCIOCHIP_GPIO_MASK_EN { 1682 DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0x0, 1683 DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 0x1, 1684} DCIOCHIP_GPIO_MASK_EN; 1685typedef enum DCIOCHIP_MASK { 1686 DCIOCHIP_MASK_DISABLE = 0x0, 1687 DCIOCHIP_MASK_ENABLE = 0x1, 1688} DCIOCHIP_MASK; 1689typedef enum DCIOCHIP_GPIO_I2C_MASK { 1690 DCIOCHIP_GPIO_I2C_MASK_DISABLE = 0x0, 1691 DCIOCHIP_GPIO_I2C_MASK_ENABLE = 0x1, 1692} DCIOCHIP_GPIO_I2C_MASK; 1693typedef enum DCIOCHIP_GPIO_I2C_DRIVE { 1694 DCIOCHIP_GPIO_I2C_DRIVE_LOW = 0x0, 1695 DCIOCHIP_GPIO_I2C_DRIVE_HIGH = 0x1, 1696} DCIOCHIP_GPIO_I2C_DRIVE; 1697typedef enum DCIOCHIP_GPIO_I2C_EN { 1698 DCIOCHIP_GPIO_I2C_DISABLE = 0x0, 1699 DCIOCHIP_GPIO_I2C_ENABLE = 0x1, 1700} DCIOCHIP_GPIO_I2C_EN; 1701typedef enum DCIOCHIP_MASK_4BIT { 1702 DCIOCHIP_MASK_4BIT_DISABLE = 0x0, 1703 DCIOCHIP_MASK_4BIT_ENABLE = 0xf, 1704} DCIOCHIP_MASK_4BIT; 1705typedef enum DCIOCHIP_ENABLE_4BIT { 1706 DCIOCHIP_4BIT_DISABLE = 0x0, 1707 DCIOCHIP_4BIT_ENABLE = 0xf, 1708} DCIOCHIP_ENABLE_4BIT; 1709typedef enum DCIOCHIP_MASK_5BIT { 1710 DCIOCHIP_MASIK_5BIT_DISABLE = 0x0, 1711 DCIOCHIP_MASIK_5BIT_ENABLE = 0x1f, 1712} DCIOCHIP_MASK_5BIT; 1713typedef enum DCIOCHIP_ENABLE_5BIT { 1714 DCIOCHIP_5BIT_DISABLE = 0x0, 1715 DCIOCHIP_5BIT_ENABLE = 0x1f, 1716} DCIOCHIP_ENABLE_5BIT; 1717typedef enum DCIOCHIP_MASK_2BIT { 1718 DCIOCHIP_MASK_2BIT_DISABLE = 0x0, 1719 DCIOCHIP_MASK_2BIT_ENABLE = 0x3, 1720} DCIOCHIP_MASK_2BIT; 1721typedef enum DCIOCHIP_ENABLE_2BIT { 1722 DCIOCHIP_2BIT_DISABLE = 0x0, 1723 DCIOCHIP_2BIT_ENABLE = 0x3, 1724} DCIOCHIP_ENABLE_2BIT; 1725typedef enum DCIOCHIP_REF_27_SRC_SEL { 1726 DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0x0, 1727 DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 0x1, 1728 DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 0x2, 1729 DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 0x3, 1730} DCIOCHIP_REF_27_SRC_SEL; 1731typedef enum DCIOCHIP_DVO_VREFPON { 1732 DCIOCHIP_DVO_VREFPON_DISABLE = 0x0, 1733 DCIOCHIP_DVO_VREFPON_ENABLE = 0x1, 1734} DCIOCHIP_DVO_VREFPON; 1735typedef enum DCIOCHIP_DVO_VREFSEL { 1736 DCIOCHIP_DVO_VREFSEL_ONCHIP = 0x0, 1737 DCIOCHIP_DVO_VREFSEL_EXTERNAL = 0x1, 1738} DCIOCHIP_DVO_VREFSEL; 1739typedef enum DCIOCHIP_SPDIF1_IMODE { 1740 DCIOCHIP_SPDIF1_IMODE_OE_A = 0x0, 1741 DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO = 0x1, 1742} DCIOCHIP_SPDIF1_IMODE; 1743typedef enum DCIOCHIP_AUX_FALLSLEWSEL { 1744 DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0x0, 1745 DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 0x1, 1746 DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 0x2, 1747 DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 0x3, 1748} DCIOCHIP_AUX_FALLSLEWSEL; 1749typedef enum DCIOCHIP_AUX_SPIKESEL { 1750 DCIOCHIP_AUX_SPIKESEL_50NS = 0x0, 1751 DCIOCHIP_AUX_SPIKESEL_10NS = 0x1, 1752} DCIOCHIP_AUX_SPIKESEL; 1753typedef enum DCIOCHIP_AUX_CSEL0P9 { 1754 DCIOCHIP_AUX_CSEL_DEC1P0 = 0x0, 1755 DCIOCHIP_AUX_CSEL_DEC0P9 = 0x1, 1756} DCIOCHIP_AUX_CSEL0P9; 1757typedef enum DCIOCHIP_AUX_CSEL1P1 { 1758 DCIOCHIP_AUX_CSEL_INC1P0 = 0x0, 1759 DCIOCHIP_AUX_CSEL_INC1P1 = 0x1, 1760} DCIOCHIP_AUX_CSEL1P1; 1761typedef enum DCIOCHIP_AUX_RSEL0P9 { 1762 DCIOCHIP_AUX_RSEL_DEC1P0 = 0x0, 1763 DCIOCHIP_AUX_RSEL_DEC0P9 = 0x1, 1764} DCIOCHIP_AUX_RSEL0P9; 1765typedef enum DCIOCHIP_AUX_RSEL1P1 { 1766 DCIOCHIP_AUX_RSEL_INC1P0 = 0x0, 1767 DCIOCHIP_AUX_RSEL_INC1P1 = 0x1, 1768} DCIOCHIP_AUX_RSEL1P1; 1769typedef enum DCP_GRPH_ENABLE { 1770 DCP_GRPH_ENABLE_FALSE = 0x0, 1771 DCP_GRPH_ENABLE_TRUE = 0x1, 1772} DCP_GRPH_ENABLE; 1773typedef enum DCP_GRPH_KEYER_ALPHA_SEL { 1774 DCP_GRPH_KEYER_ALPHA_SEL_FALSE = 0x0, 1775 DCP_GRPH_KEYER_ALPHA_SEL_TRUE = 0x1, 1776} DCP_GRPH_KEYER_ALPHA_SEL; 1777typedef enum DCP_GRPH_DEPTH { 1778 DCP_GRPH_DEPTH_8BPP = 0x0, 1779 DCP_GRPH_DEPTH_16BPP = 0x1, 1780 DCP_GRPH_DEPTH_32BPP = 0x2, 1781 DCP_GRPH_DEPTH_64BPP = 0x3, 1782} DCP_GRPH_DEPTH; 1783typedef enum DCP_GRPH_NUM_BANKS { 1784 DCP_GRPH_NUM_BANKS_2BANK = 0x0, 1785 DCP_GRPH_NUM_BANKS_4BANK = 0x1, 1786 DCP_GRPH_NUM_BANKS_8BANK = 0x2, 1787 DCP_GRPH_NUM_BANKS_16BANK = 0x3, 1788} DCP_GRPH_NUM_BANKS; 1789typedef enum DCP_GRPH_BANK_WIDTH { 1790 DCP_GRPH_BANK_WIDTH_1 = 0x0, 1791 DCP_GRPH_BANK_WIDTH_2 = 0x1, 1792 DCP_GRPH_BANK_WIDTH_4 = 0x2, 1793 DCP_GRPH_BANK_WIDTH_8 = 0x3, 1794} DCP_GRPH_BANK_WIDTH; 1795typedef enum DCP_GRPH_FORMAT { 1796 DCP_GRPH_FORMAT_8BPP = 0x0, 1797 DCP_GRPH_FORMAT_16BPP = 0x1, 1798 DCP_GRPH_FORMAT_32BPP = 0x2, 1799 DCP_GRPH_FORMAT_64BPP = 0x3, 1800} DCP_GRPH_FORMAT; 1801typedef enum DCP_GRPH_BANK_HEIGHT { 1802 DCP_GRPH_BANK_HEIGHT_1 = 0x0, 1803 DCP_GRPH_BANK_HEIGHT_2 = 0x1, 1804 DCP_GRPH_BANK_HEIGHT_4 = 0x2, 1805 DCP_GRPH_BANK_HEIGHT_8 = 0x3, 1806} DCP_GRPH_BANK_HEIGHT; 1807typedef enum DCP_GRPH_TILE_SPLIT { 1808 DCP_GRPH_TILE_SPLIT_64B = 0x0, 1809 DCP_GRPH_TILE_SPLIT_128B = 0x1, 1810 DCP_GRPH_TILE_SPLIT_256B = 0x2, 1811 DCP_GRPH_TILE_SPLIT_512B = 0x3, 1812 DCP_GRPH_TILE_SPLIT_1B = 0x4, 1813 DCP_GRPH_TILE_SPLIT_2B = 0x5, 1814 DCP_GRPH_TILE_SPLIT_4B = 0x6, 1815} DCP_GRPH_TILE_SPLIT; 1816typedef enum DCP_GRPH_ADDRESS_TRANSLATION_ENABLE { 1817 DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE = 0x0, 1818 DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE = 0x1, 1819} DCP_GRPH_ADDRESS_TRANSLATION_ENABLE; 1820typedef enum DCP_GRPH_PRIVILEGED_ACCESS_ENABLE { 1821 DCP_GRPH_PRIVILEGED_ACCESS_ENABLE_FALSE = 0x0, 1822 DCP_GRPH_PRIVILEGED_ACCESS_ENABLE_TRUE = 0x1, 1823} DCP_GRPH_PRIVILEGED_ACCESS_ENABLE; 1824typedef enum DCP_GRPH_MACRO_TILE_ASPECT { 1825 DCP_GRPH_MACRO_TILE_ASPECT_1 = 0x0, 1826 DCP_GRPH_MACRO_TILE_ASPECT_2 = 0x1, 1827 DCP_GRPH_MACRO_TILE_ASPECT_4 = 0x2, 1828 DCP_GRPH_MACRO_TILE_ASPECT_8 = 0x3, 1829} DCP_GRPH_MACRO_TILE_ASPECT; 1830typedef enum DCP_GRPH_ARRAY_MODE { 1831 DCP_GRPH_ARRAY_MODE_0 = 0x0, 1832 DCP_GRPH_ARRAY_MODE_1 = 0x1, 1833 DCP_GRPH_ARRAY_MODE_2 = 0x2, 1834 DCP_GRPH_ARRAY_MODE_3 = 0x3, 1835 DCP_GRPH_ARRAY_MODE_4 = 0x4, 1836 DCP_GRPH_ARRAY_MODE_7 = 0x7, 1837 DCP_GRPH_ARRAY_MODE_12 = 0xc, 1838 DCP_GRPH_ARRAY_MODE_13 = 0xd, 1839} DCP_GRPH_ARRAY_MODE; 1840typedef enum DCP_GRPH_MICRO_TILE_MODE { 1841 DCP_GRPH_MICRO_TILE_MODE_0 = 0x0, 1842 DCP_GRPH_MICRO_TILE_MODE_1 = 0x1, 1843 DCP_GRPH_MICRO_TILE_MODE_2 = 0x2, 1844 DCP_GRPH_MICRO_TILE_MODE_3 = 0x3, 1845} DCP_GRPH_MICRO_TILE_MODE; 1846typedef enum DCP_GRPH_COLOR_EXPANSION_MODE { 1847 DCP_GRPH_COLOR_EXPANSION_MODE_DEXP = 0x0, 1848 DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP = 0x1, 1849} DCP_GRPH_COLOR_EXPANSION_MODE; 1850typedef enum DCP_GRPH_LUT_10BIT_BYPASS_EN { 1851 DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE = 0x0, 1852 DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE = 0x1, 1853} DCP_GRPH_LUT_10BIT_BYPASS_EN; 1854typedef enum DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN { 1855 DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE = 0x0, 1856 DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE = 0x1, 1857} DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN; 1858typedef enum DCP_GRPH_ENDIAN_SWAP { 1859 DCP_GRPH_ENDIAN_SWAP_NONE = 0x0, 1860 DCP_GRPH_ENDIAN_SWAP_8IN16 = 0x1, 1861 DCP_GRPH_ENDIAN_SWAP_8IN32 = 0x2, 1862 DCP_GRPH_ENDIAN_SWAP_8IN64 = 0x3, 1863} DCP_GRPH_ENDIAN_SWAP; 1864typedef enum DCP_GRPH_RED_CROSSBAR { 1865 DCP_GRPH_RED_CROSSBAR_FROM_R = 0x0, 1866 DCP_GRPH_RED_CROSSBAR_FROM_G = 0x1, 1867 DCP_GRPH_RED_CROSSBAR_FROM_B = 0x2, 1868 DCP_GRPH_RED_CROSSBAR_FROM_A = 0x3, 1869} DCP_GRPH_RED_CROSSBAR; 1870typedef enum DCP_GRPH_GREEN_CROSSBAR { 1871 DCP_GRPH_GREEN_CROSSBAR_FROM_G = 0x0, 1872 DCP_GRPH_GREEN_CROSSBAR_FROM_B = 0x1, 1873 DCP_GRPH_GREEN_CROSSBAR_FROM_A = 0x2, 1874 DCP_GRPH_GREEN_CROSSBAR_FROM_R = 0x3, 1875} DCP_GRPH_GREEN_CROSSBAR; 1876typedef enum DCP_GRPH_BLUE_CROSSBAR { 1877 DCP_GRPH_BLUE_CROSSBAR_FROM_B = 0x0, 1878 DCP_GRPH_BLUE_CROSSBAR_FROM_A = 0x1, 1879 DCP_GRPH_BLUE_CROSSBAR_FROM_R = 0x2, 1880 DCP_GRPH_BLUE_CROSSBAR_FROM_G = 0x3, 1881} DCP_GRPH_BLUE_CROSSBAR; 1882typedef enum DCP_GRPH_ALPHA_CROSSBAR { 1883 DCP_GRPH_ALPHA_CROSSBAR_FROM_A = 0x0, 1884 DCP_GRPH_ALPHA_CROSSBAR_FROM_R = 0x1, 1885 DCP_GRPH_ALPHA_CROSSBAR_FROM_G = 0x2, 1886 DCP_GRPH_ALPHA_CROSSBAR_FROM_B = 0x3, 1887} DCP_GRPH_ALPHA_CROSSBAR; 1888typedef enum DCP_GRPH_PRIMARY_DFQ_ENABLE { 1889 DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE = 0x0, 1890 DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE = 0x1, 1891} DCP_GRPH_PRIMARY_DFQ_ENABLE; 1892typedef enum DCP_GRPH_SECONDARY_DFQ_ENABLE { 1893 DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE = 0x0, 1894 DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE = 0x1, 1895} DCP_GRPH_SECONDARY_DFQ_ENABLE; 1896typedef enum DCP_GRPH_INPUT_GAMMA_MODE { 1897 DCP_GRPH_INPUT_GAMMA_MODE_LUT = 0x0, 1898 DCP_GRPH_INPUT_GAMMA_MODE_BYPASS = 0x1, 1899} DCP_GRPH_INPUT_GAMMA_MODE; 1900typedef enum DCP_GRPH_MODE_UPDATE_PENDING { 1901 DCP_GRPH_MODE_UPDATE_PENDING_FALSE = 0x0, 1902 DCP_GRPH_MODE_UPDATE_PENDING_TRUE = 0x1, 1903} DCP_GRPH_MODE_UPDATE_PENDING; 1904typedef enum DCP_GRPH_MODE_UPDATE_TAKEN { 1905 DCP_GRPH_MODE_UPDATE_TAKEN_FALSE = 0x0, 1906 DCP_GRPH_MODE_UPDATE_TAKEN_TRUE = 0x1, 1907} DCP_GRPH_MODE_UPDATE_TAKEN; 1908typedef enum DCP_GRPH_SURFACE_UPDATE_PENDING { 1909 DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE = 0x0, 1910 DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE = 0x1, 1911} DCP_GRPH_SURFACE_UPDATE_PENDING; 1912typedef enum DCP_GRPH_SURFACE_UPDATE_TAKEN { 1913 DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE = 0x0, 1914 DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE = 0x1, 1915} DCP_GRPH_SURFACE_UPDATE_TAKEN; 1916typedef enum DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE { 1917 DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE = 0x0, 1918 DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE = 0x1, 1919} DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE; 1920typedef enum DCP_GRPH_UPDATE_LOCK { 1921 DCP_GRPH_UPDATE_LOCK_FALSE = 0x0, 1922 DCP_GRPH_UPDATE_LOCK_TRUE = 0x1, 1923} DCP_GRPH_UPDATE_LOCK; 1924typedef enum DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK { 1925 DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE = 0x0, 1926 DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE = 0x1, 1927} DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK; 1928typedef enum DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE { 1929 DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0, 1930 DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1, 1931} DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE; 1932typedef enum DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE { 1933 DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0, 1934 DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1, 1935} DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE; 1936typedef enum DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN { 1937 DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE = 0x0, 1938 DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE = 0x1, 1939} DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN; 1940typedef enum DCP_GRPH_XDMA_SUPER_AA_EN { 1941 DCP_GRPH_XDMA_SUPER_AA_EN_FALSE = 0x0, 1942 DCP_GRPH_XDMA_SUPER_AA_EN_TRUE = 0x1, 1943} DCP_GRPH_XDMA_SUPER_AA_EN; 1944typedef enum DCP_GRPH_DFQ_RESET { 1945 DCP_GRPH_DFQ_RESET_FALSE = 0x0, 1946 DCP_GRPH_DFQ_RESET_TRUE = 0x1, 1947} DCP_GRPH_DFQ_RESET; 1948typedef enum DCP_GRPH_DFQ_SIZE { 1949 DCP_GRPH_DFQ_SIZE_DEEP1 = 0x0, 1950 DCP_GRPH_DFQ_SIZE_DEEP2 = 0x1, 1951 DCP_GRPH_DFQ_SIZE_DEEP3 = 0x2, 1952 DCP_GRPH_DFQ_SIZE_DEEP4 = 0x3, 1953 DCP_GRPH_DFQ_SIZE_DEEP5 = 0x4, 1954 DCP_GRPH_DFQ_SIZE_DEEP6 = 0x5, 1955 DCP_GRPH_DFQ_SIZE_DEEP7 = 0x6, 1956 DCP_GRPH_DFQ_SIZE_DEEP8 = 0x7, 1957} DCP_GRPH_DFQ_SIZE; 1958typedef enum DCP_GRPH_DFQ_MIN_FREE_ENTRIES { 1959 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1 = 0x0, 1960 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2 = 0x1, 1961 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3 = 0x2, 1962 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4 = 0x3, 1963 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5 = 0x4, 1964 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6 = 0x5, 1965 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7 = 0x6, 1966 DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8 = 0x7, 1967} DCP_GRPH_DFQ_MIN_FREE_ENTRIES; 1968typedef enum DCP_GRPH_DFQ_RESET_ACK { 1969 DCP_GRPH_DFQ_RESET_ACK_FALSE = 0x0, 1970 DCP_GRPH_DFQ_RESET_ACK_TRUE = 0x1, 1971} DCP_GRPH_DFQ_RESET_ACK; 1972typedef enum DCP_GRPH_PFLIP_INT_CLEAR { 1973 DCP_GRPH_PFLIP_INT_CLEAR_FALSE = 0x0, 1974 DCP_GRPH_PFLIP_INT_CLEAR_TRUE = 0x1, 1975} DCP_GRPH_PFLIP_INT_CLEAR; 1976typedef enum DCP_GRPH_PFLIP_INT_MASK { 1977 DCP_GRPH_PFLIP_INT_MASK_FALSE = 0x0, 1978 DCP_GRPH_PFLIP_INT_MASK_TRUE = 0x1, 1979} DCP_GRPH_PFLIP_INT_MASK; 1980typedef enum DCP_GRPH_PFLIP_INT_TYPE { 1981 DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL = 0x0, 1982 DCP_GRPH_PFLIP_INT_TYPE_PULSE = 0x1, 1983} DCP_GRPH_PFLIP_INT_TYPE; 1984typedef enum DCP_GRPH_PRESCALE_SELECT { 1985 DCP_GRPH_PRESCALE_SELECT_FIXED = 0x0, 1986 DCP_GRPH_PRESCALE_SELECT_FLOATING = 0x1, 1987} DCP_GRPH_PRESCALE_SELECT; 1988typedef enum DCP_GRPH_PRESCALE_R_SIGN { 1989 DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED = 0x0, 1990 DCP_GRPH_PRESCALE_R_SIGN_SIGNED = 0x1, 1991} DCP_GRPH_PRESCALE_R_SIGN; 1992typedef enum DCP_GRPH_PRESCALE_G_SIGN { 1993 DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED = 0x0, 1994 DCP_GRPH_PRESCALE_G_SIGN_SIGNED = 0x1, 1995} DCP_GRPH_PRESCALE_G_SIGN; 1996typedef enum DCP_GRPH_PRESCALE_B_SIGN { 1997 DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED = 0x0, 1998 DCP_GRPH_PRESCALE_B_SIGN_SIGNED = 0x1, 1999} DCP_GRPH_PRESCALE_B_SIGN; 2000typedef enum DCP_GRPH_PRESCALE_BYPASS { 2001 DCP_GRPH_PRESCALE_BYPASS_FALSE = 0x0, 2002 DCP_GRPH_PRESCALE_BYPASS_TRUE = 0x1, 2003} DCP_GRPH_PRESCALE_BYPASS; 2004typedef enum DCP_INPUT_CSC_GRPH_MODE { 2005 DCP_INPUT_CSC_GRPH_MODE_BYPASS = 0x0, 2006 DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF = 0x1, 2007 DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF = 0x2, 2008 DCP_INPUT_CSC_GRPH_MODE_RESERVED = 0x3, 2009} DCP_INPUT_CSC_GRPH_MODE; 2010typedef enum DCP_OUTPUT_CSC_GRPH_MODE { 2011 DCP_OUTPUT_CSC_GRPH_MODE_BYPASS = 0x0, 2012 DCP_OUTPUT_CSC_GRPH_MODE_RGB = 0x1, 2013 DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601 = 0x2, 2014 DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709 = 0x3, 2015 DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF = 0x4, 2016 DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF = 0x5, 2017 DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0 = 0x6, 2018 DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1 = 0x7, 2019} DCP_OUTPUT_CSC_GRPH_MODE; 2020typedef enum DCP_DENORM_MODE { 2021 DCP_DENORM_MODE_UNITY = 0x0, 2022 DCP_DENORM_MODE_6BIT = 0x1, 2023 DCP_DENORM_MODE_8BIT = 0x2, 2024 DCP_DENORM_MODE_10BIT = 0x3, 2025 DCP_DENORM_MODE_11BIT = 0x4, 2026 DCP_DENORM_MODE_12BIT = 0x5, 2027 DCP_DENORM_MODE_RESERVED0 = 0x6, 2028 DCP_DENORM_MODE_RESERVED1 = 0x7, 2029} DCP_DENORM_MODE; 2030typedef enum DCP_DENORM_14BIT_OUT { 2031 DCP_DENORM_14BIT_OUT_FALSE = 0x0, 2032 DCP_DENORM_14BIT_OUT_TRUE = 0x1, 2033} DCP_DENORM_14BIT_OUT; 2034typedef enum DCP_OUT_ROUND_TRUNC_MODE { 2035 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12 = 0x0, 2036 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11 = 0x1, 2037 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10 = 0x2, 2038 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9 = 0x3, 2039 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8 = 0x4, 2040 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED = 0x5, 2041 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14 = 0x6, 2042 DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13 = 0x7, 2043 DCP_OUT_ROUND_TRUNC_MODE_ROUND_12 = 0x8, 2044 DCP_OUT_ROUND_TRUNC_MODE_ROUND_11 = 0x9, 2045 DCP_OUT_ROUND_TRUNC_MODE_ROUND_10 = 0xa, 2046 DCP_OUT_ROUND_TRUNC_MODE_ROUND_9 = 0xb, 2047 DCP_OUT_ROUND_TRUNC_MODE_ROUND_8 = 0xc, 2048 DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED = 0xd, 2049 DCP_OUT_ROUND_TRUNC_MODE_ROUND_14 = 0xe, 2050 DCP_OUT_ROUND_TRUNC_MODE_ROUND_13 = 0xf, 2051} DCP_OUT_ROUND_TRUNC_MODE; 2052typedef enum DCP_KEY_MODE { 2053 DCP_KEY_MODE_ALPHA0 = 0x0, 2054 DCP_KEY_MODE_ALPHA1 = 0x1, 2055 DCP_KEY_MODE_IN_RANGE_ALPHA1 = 0x2, 2056 DCP_KEY_MODE_IN_RANGE_ALPHA0 = 0x3, 2057} DCP_KEY_MODE; 2058typedef enum DCP_GRPH_DEGAMMA_MODE { 2059 DCP_GRPH_DEGAMMA_MODE_BYPASS = 0x0, 2060 DCP_GRPH_DEGAMMA_MODE_ROMA = 0x1, 2061 DCP_GRPH_DEGAMMA_MODE_ROMB = 0x2, 2062 DCP_GRPH_DEGAMMA_MODE_RESERVED = 0x3, 2063} DCP_GRPH_DEGAMMA_MODE; 2064typedef enum DCP_CURSOR2_DEGAMMA_MODE { 2065 DCP_CURSOR2_DEGAMMA_MODE_BYPASS = 0x0, 2066 DCP_CURSOR2_DEGAMMA_MODE_ROMA = 0x1, 2067 DCP_CURSOR2_DEGAMMA_MODE_ROMB = 0x2, 2068 DCP_CURSOR2_DEGAMMA_MODE_RESERVED = 0x3, 2069} DCP_CURSOR2_DEGAMMA_MODE; 2070typedef enum DCP_CURSOR_DEGAMMA_MODE { 2071 DCP_CURSOR_DEGAMMA_MODE_BYPASS = 0x0, 2072 DCP_CURSOR_DEGAMMA_MODE_ROMA = 0x1, 2073 DCP_CURSOR_DEGAMMA_MODE_ROMB = 0x2, 2074 DCP_CURSOR_DEGAMMA_MODE_RESERVED = 0x3, 2075} DCP_CURSOR_DEGAMMA_MODE; 2076typedef enum DCP_GRPH_GAMUT_REMAP_MODE { 2077 DCP_GRPH_GAMUT_REMAP_MODE_BYPASS = 0x0, 2078 DCP_GRPH_GAMUT_REMAP_MODE_ROMA = 0x1, 2079 DCP_GRPH_GAMUT_REMAP_MODE_ROMB = 0x2, 2080 DCP_GRPH_GAMUT_REMAP_MODE_RESERVED = 0x3, 2081} DCP_GRPH_GAMUT_REMAP_MODE; 2082typedef enum DCP_SPATIAL_DITHER_EN { 2083 DCP_SPATIAL_DITHER_EN_FALSE = 0x0, 2084 DCP_SPATIAL_DITHER_EN_TRUE = 0x1, 2085} DCP_SPATIAL_DITHER_EN; 2086typedef enum DCP_SPATIAL_DITHER_MODE { 2087 DCP_SPATIAL_DITHER_MODE_BYPASS = 0x0, 2088 DCP_SPATIAL_DITHER_MODE_ROMA = 0x1, 2089 DCP_SPATIAL_DITHER_MODE_ROMB = 0x2, 2090 DCP_SPATIAL_DITHER_MODE_RESERVED = 0x3, 2091} DCP_SPATIAL_DITHER_MODE; 2092typedef enum DCP_SPATIAL_DITHER_DEPTH { 2093 DCP_SPATIAL_DITHER_DEPTH_30BPP = 0x0, 2094 DCP_SPATIAL_DITHER_DEPTH_24BPP = 0x1, 2095 DCP_SPATIAL_DITHER_DEPTH_36BPP = 0x2, 2096 DCP_SPATIAL_DITHER_DEPTH_UNDEFINED = 0x3, 2097} DCP_SPATIAL_DITHER_DEPTH; 2098typedef enum DCP_FRAME_RANDOM_ENABLE { 2099 DCP_FRAME_RANDOM_ENABLE_FALSE = 0x0, 2100 DCP_FRAME_RANDOM_ENABLE_TRUE = 0x1, 2101} DCP_FRAME_RANDOM_ENABLE; 2102typedef enum DCP_RGB_RANDOM_ENABLE { 2103 DCP_RGB_RANDOM_ENABLE_FALSE = 0x0, 2104 DCP_RGB_RANDOM_ENABLE_TRUE = 0x1, 2105} DCP_RGB_RANDOM_ENABLE; 2106typedef enum DCP_HIGHPASS_RANDOM_ENABLE { 2107 DCP_HIGHPASS_RANDOM_ENABLE_FALSE = 0x0, 2108 DCP_HIGHPASS_RANDOM_ENABLE_TRUE = 0x1, 2109} DCP_HIGHPASS_RANDOM_ENABLE; 2110typedef enum DCP_CURSOR_EN { 2111 DCP_CURSOR_EN_FALSE = 0x0, 2112 DCP_CURSOR_EN_TRUE = 0x1, 2113} DCP_CURSOR_EN; 2114typedef enum DCP_CUR_INV_TRANS_CLAMP { 2115 DCP_CUR_INV_TRANS_CLAMP_FALSE = 0x0, 2116 DCP_CUR_INV_TRANS_CLAMP_TRUE = 0x1, 2117} DCP_CUR_INV_TRANS_CLAMP; 2118typedef enum DCP_CURSOR_MODE { 2119 DCP_CURSOR_MODE_MONO_2BPP = 0x0, 2120 DCP_CURSOR_MODE_24BPP_1BIT = 0x1, 2121 DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI = 0x2, 2122 DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI = 0x3, 2123} DCP_CURSOR_MODE; 2124typedef enum DCP_CURSOR_2X_MAGNIFY { 2125 DCP_CURSOR_2X_MAGNIFY_FALSE = 0x0, 2126 DCP_CURSOR_2X_MAGNIFY_TRUE = 0x1, 2127} DCP_CURSOR_2X_MAGNIFY; 2128typedef enum DCP_CURSOR_FORCE_MC_ON { 2129 DCP_CURSOR_FORCE_MC_ON_FALSE = 0x0, 2130 DCP_CURSOR_FORCE_MC_ON_TRUE = 0x1, 2131} DCP_CURSOR_FORCE_MC_ON; 2132typedef enum DCP_CURSOR_URGENT_CONTROL { 2133 DCP_CURSOR_URGENT_CONTROL_MODE_0 = 0x0, 2134 DCP_CURSOR_URGENT_CONTROL_MODE_1 = 0x1, 2135 DCP_CURSOR_URGENT_CONTROL_MODE_2 = 0x2, 2136 DCP_CURSOR_URGENT_CONTROL_MODE_3 = 0x3, 2137 DCP_CURSOR_URGENT_CONTROL_MODE_4 = 0x4, 2138} DCP_CURSOR_URGENT_CONTROL; 2139typedef enum DCP_CURSOR_UPDATE_PENDING { 2140 DCP_CURSOR_UPDATE_PENDING_FALSE = 0x0, 2141 DCP_CURSOR_UPDATE_PENDING_TRUE = 0x1, 2142} DCP_CURSOR_UPDATE_PENDING; 2143typedef enum DCP_CURSOR_UPDATE_TAKEN { 2144 DCP_CURSOR_UPDATE_TAKEN_FALSE = 0x0, 2145 DCP_CURSOR_UPDATE_TAKEN_TRUE = 0x1, 2146} DCP_CURSOR_UPDATE_TAKEN; 2147typedef enum DCP_CURSOR_UPDATE_LOCK { 2148 DCP_CURSOR_UPDATE_LOCK_FALSE = 0x0, 2149 DCP_CURSOR_UPDATE_LOCK_TRUE = 0x1, 2150} DCP_CURSOR_UPDATE_LOCK; 2151typedef enum DCP_CURSOR_DISABLE_MULTIPLE_UPDATE { 2152 DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0, 2153 DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1, 2154} DCP_CURSOR_DISABLE_MULTIPLE_UPDATE; 2155typedef enum DCP_CURSOR_UPDATE_STEREO_MODE { 2156 DCP_CURSOR_UPDATE_STEREO_MODE_BOTH = 0x0, 2157 DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY = 0x1, 2158 DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED = 0x2, 2159 DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY = 0x3, 2160} DCP_CURSOR_UPDATE_STEREO_MODE; 2161typedef enum DCP_CURSOR2_EN { 2162 DCP_CURSOR2_EN_FALSE = 0x0, 2163 DCP_CURSOR2_EN_TRUE = 0x1, 2164} DCP_CURSOR2_EN; 2165typedef enum DCP_CUR2_INV_TRANS_CLAMP { 2166 DCP_CUR2_INV_TRANS_CLAMP_FALSE = 0x0, 2167 DCP_CUR2_INV_TRANS_CLAMP_TRUE = 0x1, 2168} DCP_CUR2_INV_TRANS_CLAMP; 2169typedef enum DCP_CURSOR2_MODE { 2170 DCP_CURSOR2_MODE_MONO_2BPP = 0x0, 2171 DCP_CURSOR2_MODE_24BPP_1BIT = 0x1, 2172 DCP_CURSOR2_MODE_24BPP_8BIT_PREMULTI = 0x2, 2173 DCP_CURSOR2_MODE_24BPP_8BIT_UNPREMULTI = 0x3, 2174} DCP_CURSOR2_MODE; 2175typedef enum DCP_CURSOR2_2X_MAGNIFY { 2176 DCP_CURSOR2_2X_MAGNIFY_FALSE = 0x0, 2177 DCP_CURSOR2_2X_MAGNIFY_TRUE = 0x1, 2178} DCP_CURSOR2_2X_MAGNIFY; 2179typedef enum DCP_CURSOR2_FORCE_MC_ON { 2180 DCP_CURSOR2_FORCE_MC_ON_FALSE = 0x0, 2181 DCP_CURSOR2_FORCE_MC_ON_TRUE = 0x1, 2182} DCP_CURSOR2_FORCE_MC_ON; 2183typedef enum DCP_CURSOR2_URGENT_CONTROL { 2184 DCP_CURSOR2_URGENT_CONTROL_MODE_0 = 0x0, 2185 DCP_CURSOR2_URGENT_CONTROL_MODE_1 = 0x1, 2186 DCP_CURSOR2_URGENT_CONTROL_MODE_2 = 0x2, 2187 DCP_CURSOR2_URGENT_CONTROL_MODE_3 = 0x3, 2188 DCP_CURSOR2_URGENT_CONTROL_MODE_4 = 0x4, 2189} DCP_CURSOR2_URGENT_CONTROL; 2190typedef enum DCP_CURSOR2_UPDATE_PENDING { 2191 DCP_CURSOR2_UPDATE_PENDING_FALSE = 0x0, 2192 DCP_CURSOR2_UPDATE_PENDING_TRUE = 0x1, 2193} DCP_CURSOR2_UPDATE_PENDING; 2194typedef enum DCP_CURSOR2_UPDATE_TAKEN { 2195 DCP_CURSOR2_UPDATE_TAKEN_FALSE = 0x0, 2196 DCP_CURSOR2_UPDATE_TAKEN_TRUE = 0x1, 2197} DCP_CURSOR2_UPDATE_TAKEN; 2198typedef enum DCP_CURSOR2_UPDATE_LOCK { 2199 DCP_CURSOR2_UPDATE_LOCK_FALSE = 0x0, 2200 DCP_CURSOR2_UPDATE_LOCK_TRUE = 0x1, 2201} DCP_CURSOR2_UPDATE_LOCK; 2202typedef enum DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE { 2203 DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0, 2204 DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1, 2205} DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE; 2206typedef enum DCP_CURSOR2_UPDATE_STEREO_MODE { 2207 DCP_CURSOR2_UPDATE_STEREO_MODE_BOTH = 0x0, 2208 DCP_CURSOR2_UPDATE_STEREO_MODE_SECONDARY_ONLY = 0x1, 2209 DCP_CURSOR2_UPDATE_STEREO_MODE_UNDEFINED = 0x2, 2210 DCP_CURSOR2_UPDATE_STEREO_MODE_PRIMARY_ONLY = 0x3, 2211} DCP_CURSOR2_UPDATE_STEREO_MODE; 2212typedef enum DCP_CUR_REQUEST_FILTER_DIS { 2213 DCP_CUR_REQUEST_FILTER_DIS_FALSE = 0x0, 2214 DCP_CUR_REQUEST_FILTER_DIS_TRUE = 0x1, 2215} DCP_CUR_REQUEST_FILTER_DIS; 2216typedef enum DCP_CURSOR_STEREO_EN { 2217 DCP_CURSOR_STEREO_EN_FALSE = 0x0, 2218 DCP_CURSOR_STEREO_EN_TRUE = 0x1, 2219} DCP_CURSOR_STEREO_EN; 2220typedef enum DCP_CURSOR_STEREO_OFFSET_YNX { 2221 DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION = 0x0, 2222 DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION = 0x1, 2223} DCP_CURSOR_STEREO_OFFSET_YNX; 2224typedef enum DCP_CURSOR2_STEREO_EN { 2225 DCP_CURSOR2_STEREO_EN_FALSE = 0x0, 2226 DCP_CURSOR2_STEREO_EN_TRUE = 0x1, 2227} DCP_CURSOR2_STEREO_EN; 2228typedef enum DCP_CURSOR2_STEREO_OFFSET_YNX { 2229 DCP_CURSOR2_STEREO_OFFSET_YNX_X_POSITION = 0x0, 2230 DCP_CURSOR2_STEREO_OFFSET_YNX_Y_POSITION = 0x1, 2231} DCP_CURSOR2_STEREO_OFFSET_YNX; 2232typedef enum DCP_DC_LUT_RW_MODE { 2233 DCP_DC_LUT_RW_MODE_256_ENTRY = 0x0, 2234 DCP_DC_LUT_RW_MODE_PWL = 0x1, 2235} DCP_DC_LUT_RW_MODE; 2236typedef enum DCP_DC_LUT_VGA_ACCESS_ENABLE { 2237 DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE = 0x0, 2238 DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE = 0x1, 2239} DCP_DC_LUT_VGA_ACCESS_ENABLE; 2240typedef enum DCP_DC_LUT_AUTOFILL { 2241 DCP_DC_LUT_AUTOFILL_FALSE = 0x0, 2242 DCP_DC_LUT_AUTOFILL_TRUE = 0x1, 2243} DCP_DC_LUT_AUTOFILL; 2244typedef enum DCP_DC_LUT_AUTOFILL_DONE { 2245 DCP_DC_LUT_AUTOFILL_DONE_FALSE = 0x0, 2246 DCP_DC_LUT_AUTOFILL_DONE_TRUE = 0x1, 2247} DCP_DC_LUT_AUTOFILL_DONE; 2248typedef enum DCP_DC_LUT_INC_B { 2249 DCP_DC_LUT_INC_B_NA = 0x0, 2250 DCP_DC_LUT_INC_B_2 = 0x1, 2251 DCP_DC_LUT_INC_B_4 = 0x2, 2252 DCP_DC_LUT_INC_B_8 = 0x3, 2253 DCP_DC_LUT_INC_B_16 = 0x4, 2254 DCP_DC_LUT_INC_B_32 = 0x5, 2255 DCP_DC_LUT_INC_B_64 = 0x6, 2256 DCP_DC_LUT_INC_B_128 = 0x7, 2257 DCP_DC_LUT_INC_B_256 = 0x8, 2258 DCP_DC_LUT_INC_B_512 = 0x9, 2259} DCP_DC_LUT_INC_B; 2260typedef enum DCP_DC_LUT_DATA_B_SIGNED_EN { 2261 DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE = 0x0, 2262 DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE = 0x1, 2263} DCP_DC_LUT_DATA_B_SIGNED_EN; 2264typedef enum DCP_DC_LUT_DATA_B_FLOAT_POINT_EN { 2265 DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE = 0x0, 2266 DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE = 0x1, 2267} DCP_DC_LUT_DATA_B_FLOAT_POINT_EN; 2268typedef enum DCP_DC_LUT_DATA_B_FORMAT { 2269 DCP_DC_LUT_DATA_B_FORMAT_U0P10 = 0x0, 2270 DCP_DC_LUT_DATA_B_FORMAT_S1P10 = 0x1, 2271 DCP_DC_LUT_DATA_B_FORMAT_U1P11 = 0x2, 2272 DCP_DC_LUT_DATA_B_FORMAT_U0P12 = 0x3, 2273} DCP_DC_LUT_DATA_B_FORMAT; 2274typedef enum DCP_DC_LUT_INC_G { 2275 DCP_DC_LUT_INC_G_NA = 0x0, 2276 DCP_DC_LUT_INC_G_2 = 0x1, 2277 DCP_DC_LUT_INC_G_4 = 0x2, 2278 DCP_DC_LUT_INC_G_8 = 0x3, 2279 DCP_DC_LUT_INC_G_16 = 0x4, 2280 DCP_DC_LUT_INC_G_32 = 0x5, 2281 DCP_DC_LUT_INC_G_64 = 0x6, 2282 DCP_DC_LUT_INC_G_128 = 0x7, 2283 DCP_DC_LUT_INC_G_256 = 0x8, 2284 DCP_DC_LUT_INC_G_512 = 0x9, 2285} DCP_DC_LUT_INC_G; 2286typedef enum DCP_DC_LUT_DATA_G_SIGNED_EN { 2287 DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE = 0x0, 2288 DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE = 0x1, 2289} DCP_DC_LUT_DATA_G_SIGNED_EN; 2290typedef enum DCP_DC_LUT_DATA_G_FLOAT_POINT_EN { 2291 DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE = 0x0, 2292 DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE = 0x1, 2293} DCP_DC_LUT_DATA_G_FLOAT_POINT_EN; 2294typedef enum DCP_DC_LUT_DATA_G_FORMAT { 2295 DCP_DC_LUT_DATA_G_FORMAT_U0P10 = 0x0, 2296 DCP_DC_LUT_DATA_G_FORMAT_S1P10 = 0x1, 2297 DCP_DC_LUT_DATA_G_FORMAT_U1P11 = 0x2, 2298 DCP_DC_LUT_DATA_G_FORMAT_U0P12 = 0x3, 2299} DCP_DC_LUT_DATA_G_FORMAT; 2300typedef enum DCP_DC_LUT_INC_R { 2301 DCP_DC_LUT_INC_R_NA = 0x0, 2302 DCP_DC_LUT_INC_R_2 = 0x1, 2303 DCP_DC_LUT_INC_R_4 = 0x2, 2304 DCP_DC_LUT_INC_R_8 = 0x3, 2305 DCP_DC_LUT_INC_R_16 = 0x4, 2306 DCP_DC_LUT_INC_R_32 = 0x5, 2307 DCP_DC_LUT_INC_R_64 = 0x6, 2308 DCP_DC_LUT_INC_R_128 = 0x7, 2309 DCP_DC_LUT_INC_R_256 = 0x8, 2310 DCP_DC_LUT_INC_R_512 = 0x9, 2311} DCP_DC_LUT_INC_R; 2312typedef enum DCP_DC_LUT_DATA_R_SIGNED_EN { 2313 DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE = 0x0, 2314 DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE = 0x1, 2315} DCP_DC_LUT_DATA_R_SIGNED_EN; 2316typedef enum DCP_DC_LUT_DATA_R_FLOAT_POINT_EN { 2317 DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE = 0x0, 2318 DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE = 0x1, 2319} DCP_DC_LUT_DATA_R_FLOAT_POINT_EN; 2320typedef enum DCP_DC_LUT_DATA_R_FORMAT { 2321 DCP_DC_LUT_DATA_R_FORMAT_U0P10 = 0x0, 2322 DCP_DC_LUT_DATA_R_FORMAT_S1P10 = 0x1, 2323 DCP_DC_LUT_DATA_R_FORMAT_U1P11 = 0x2, 2324 DCP_DC_LUT_DATA_R_FORMAT_U0P12 = 0x3, 2325} DCP_DC_LUT_DATA_R_FORMAT; 2326typedef enum DCP_CRC_ENABLE { 2327 DCP_CRC_ENABLE_FALSE = 0x0, 2328 DCP_CRC_ENABLE_TRUE = 0x1, 2329} DCP_CRC_ENABLE; 2330typedef enum DCP_CRC_SOURCE_SEL { 2331 DCP_CRC_SOURCE_SEL_OUTPUT_PIX = 0x0, 2332 DCP_CRC_SOURCE_SEL_INPUT_L32 = 0x1, 2333 DCP_CRC_SOURCE_SEL_INPUT_H32 = 0x2, 2334 DCP_CRC_SOURCE_SEL_OUTPUT_CNTL = 0x4, 2335} DCP_CRC_SOURCE_SEL; 2336typedef enum DCP_CRC_LINE_SEL { 2337 DCP_CRC_LINE_SEL_RESERVED = 0x0, 2338 DCP_CRC_LINE_SEL_EVEN = 0x1, 2339 DCP_CRC_LINE_SEL_ODD = 0x2, 2340 DCP_CRC_LINE_SEL_BOTH = 0x3, 2341} DCP_CRC_LINE_SEL; 2342typedef enum DCP_GRPH_FLIP_RATE { 2343 DCP_GRPH_FLIP_RATE_1FRAME = 0x0, 2344 DCP_GRPH_FLIP_RATE_2FRAME = 0x1, 2345 DCP_GRPH_FLIP_RATE_3FRAME = 0x2, 2346 DCP_GRPH_FLIP_RATE_4FRAME = 0x3, 2347 DCP_GRPH_FLIP_RATE_5FRAME = 0x4, 2348 DCP_GRPH_FLIP_RATE_6FRAME = 0x5, 2349 DCP_GRPH_FLIP_RATE_7FRAME = 0x6, 2350 DCP_GRPH_FLIP_RATE_8FRAME = 0x7, 2351} DCP_GRPH_FLIP_RATE; 2352typedef enum DCP_GRPH_FLIP_RATE_ENABLE { 2353 DCP_GRPH_FLIP_RATE_ENABLE_FALSE = 0x0, 2354 DCP_GRPH_FLIP_RATE_ENABLE_TRUE = 0x1, 2355} DCP_GRPH_FLIP_RATE_ENABLE; 2356typedef enum DCP_GSL0_EN { 2357 DCP_GSL0_EN_FALSE = 0x0, 2358 DCP_GSL0_EN_TRUE = 0x1, 2359} DCP_GSL0_EN; 2360typedef enum DCP_GSL1_EN { 2361 DCP_GSL1_EN_FALSE = 0x0, 2362 DCP_GSL1_EN_TRUE = 0x1, 2363} DCP_GSL1_EN; 2364typedef enum DCP_GSL2_EN { 2365 DCP_GSL2_EN_FALSE = 0x0, 2366 DCP_GSL2_EN_TRUE = 0x1, 2367} DCP_GSL2_EN; 2368typedef enum DCP_GSL_MASTER_EN { 2369 DCP_GSL_MASTER_EN_FALSE = 0x0, 2370 DCP_GSL_MASTER_EN_TRUE = 0x1, 2371} DCP_GSL_MASTER_EN; 2372typedef enum DCP_GSL_XDMA_GROUP { 2373 DCP_GSL_XDMA_GROUP_VSYNC = 0x0, 2374 DCP_GSL_XDMA_GROUP_HSYNC0 = 0x1, 2375 DCP_GSL_XDMA_GROUP_HSYNC1 = 0x2, 2376 DCP_GSL_XDMA_GROUP_HSYNC2 = 0x3, 2377} DCP_GSL_XDMA_GROUP; 2378typedef enum DCP_GSL_XDMA_GROUP_UNDERFLOW_EN { 2379 DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE = 0x0, 2380 DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE = 0x1, 2381} DCP_GSL_XDMA_GROUP_UNDERFLOW_EN; 2382typedef enum DCP_GSL_SYNC_SOURCE { 2383 DCP_GSL_SYNC_SOURCE_FLIP = 0x0, 2384 DCP_GSL_SYNC_SOURCE_PHASE0 = 0x1, 2385 DCP_GSL_SYNC_SOURCE_RESET = 0x2, 2386 DCP_GSL_SYNC_SOURCE_PHASE1 = 0x3, 2387} DCP_GSL_SYNC_SOURCE; 2388typedef enum DCP_GSL_DELAY_SURFACE_UPDATE_PENDING { 2389 DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE = 0x0, 2390 DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE = 0x1, 2391} DCP_GSL_DELAY_SURFACE_UPDATE_PENDING; 2392typedef enum DCP_TEST_DEBUG_WRITE_EN { 2393 DCP_TEST_DEBUG_WRITE_EN_FALSE = 0x0, 2394 DCP_TEST_DEBUG_WRITE_EN_TRUE = 0x1, 2395} DCP_TEST_DEBUG_WRITE_EN; 2396typedef enum DCP_GRPH_STEREOSYNC_FLIP_EN { 2397 DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE = 0x0, 2398 DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE = 0x1, 2399} DCP_GRPH_STEREOSYNC_FLIP_EN; 2400typedef enum DCP_GRPH_STEREOSYNC_FLIP_MODE { 2401 DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP = 0x0, 2402 DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0 = 0x1, 2403 DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET = 0x2, 2404 DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1 = 0x3, 2405} DCP_GRPH_STEREOSYNC_FLIP_MODE; 2406typedef enum DCP_GRPH_STEREOSYNC_SELECT_DISABLE { 2407 DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE = 0x0, 2408 DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE = 0x1, 2409} DCP_GRPH_STEREOSYNC_SELECT_DISABLE; 2410typedef enum DCP_GRPH_ROTATION_ANGLE { 2411 DCP_GRPH_ROTATION_ANGLE_0 = 0x0, 2412 DCP_GRPH_ROTATION_ANGLE_90 = 0x1, 2413 DCP_GRPH_ROTATION_ANGLE_180 = 0x2, 2414 DCP_GRPH_ROTATION_ANGLE_270 = 0x3, 2415} DCP_GRPH_ROTATION_ANGLE; 2416typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN { 2417 DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE = 0x0, 2418 DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE = 0x1, 2419} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN; 2420typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE { 2421 DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM = 0x0, 2422 DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE= 0x1, 2423} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE; 2424typedef enum DCP_GRPH_REGAMMA_MODE { 2425 DCP_GRPH_REGAMMA_MODE_BYPASS = 0x0, 2426 DCP_GRPH_REGAMMA_MODE_SRGB = 0x1, 2427 DCP_GRPH_REGAMMA_MODE_XVYCC = 0x2, 2428 DCP_GRPH_REGAMMA_MODE_PROGA = 0x3, 2429 DCP_GRPH_REGAMMA_MODE_PROGB = 0x4, 2430} DCP_GRPH_REGAMMA_MODE; 2431typedef enum DCP_ALPHA_ROUND_TRUNC_MODE { 2432 DCP_ALPHA_ROUND_TRUNC_MODE_ROUND = 0x0, 2433 DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC = 0x1, 2434} DCP_ALPHA_ROUND_TRUNC_MODE; 2435typedef enum DCP_CURSOR_ALPHA_BLND_ENA { 2436 DCP_CURSOR_ALPHA_BLND_ENA_FALSE = 0x0, 2437 DCP_CURSOR_ALPHA_BLND_ENA_TRUE = 0x1, 2438} DCP_CURSOR_ALPHA_BLND_ENA; 2439typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK { 2440 DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE = 0x0, 2441 DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE = 0x1, 2442} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK; 2443typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK { 2444 DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE = 0x0, 2445 DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE = 0x1, 2446} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK; 2447typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK { 2448 DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE = 0x0, 2449 DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE = 0x1, 2450} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK; 2451typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK { 2452 DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE = 0x0, 2453 DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE = 0x1, 2454} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK; 2455typedef enum DCP_GRPH_SURFACE_COUNTER_EN { 2456 DCP_GRPH_SURFACE_COUNTER_EN_DISABLE = 0x0, 2457 DCP_GRPH_SURFACE_COUNTER_EN_ENABLE = 0x1, 2458} DCP_GRPH_SURFACE_COUNTER_EN; 2459typedef enum DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT { 2460 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0 = 0x0, 2461 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1 = 0x1, 2462 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2 = 0x2, 2463 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3 = 0x3, 2464 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4 = 0x4, 2465 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5 = 0x5, 2466 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6 = 0x6, 2467 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7 = 0x7, 2468 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8 = 0x8, 2469 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9 = 0x9, 2470 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10 = 0xa, 2471 DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11 = 0xb, 2472} DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT; 2473typedef enum DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED { 2474 DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO = 0x0, 2475 DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES = 0x1, 2476} DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED; 2477typedef enum HDMI_KEEPOUT_MODE { 2478 HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0x0, 2479 HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 0x1, 2480} HDMI_KEEPOUT_MODE; 2481typedef enum HDMI_CLOCK_CHANNEL_RATE { 2482 HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0x0, 2483 HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 0x1, 2484} HDMI_CLOCK_CHANNEL_RATE; 2485typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED { 2486 HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0x0, 2487 HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 0x1, 2488} HDMI_NO_EXTRA_NULL_PACKET_FILLED; 2489typedef enum HDMI_PACKET_GEN_VERSION { 2490 HDMI_PACKET_GEN_VERSION_OLD = 0x0, 2491 HDMI_PACKET_GEN_VERSION_NEW = 0x1, 2492} HDMI_PACKET_GEN_VERSION; 2493typedef enum HDMI_ERROR_ACK { 2494 HDMI_ERROR_ACK_INT = 0x0, 2495 HDMI_ERROR_NOT_ACK = 0x1, 2496} HDMI_ERROR_ACK; 2497typedef enum HDMI_ERROR_MASK { 2498 HDMI_ERROR_MASK_INT = 0x0, 2499 HDMI_ERROR_NOT_MASK = 0x1, 2500} HDMI_ERROR_MASK; 2501typedef enum HDMI_DEEP_COLOR_DEPTH { 2502 HDMI_DEEP_COLOR_DEPTH_24BPP = 0x0, 2503 HDMI_DEEP_COLOR_DEPTH_30BPP = 0x1, 2504 HDMI_DEEP_COLOR_DEPTH_36BPP = 0x2, 2505 HDMI_DEEP_COLOR_DEPTH_RESERVED = 0x3, 2506} HDMI_DEEP_COLOR_DEPTH; 2507typedef enum HDMI_AUDIO_DELAY_EN { 2508 HDMI_AUDIO_DELAY_DISABLE = 0x0, 2509 HDMI_AUDIO_DELAY_58CLK = 0x1, 2510 HDMI_AUDIO_DELAY_56CLK = 0x2, 2511 HDMI_AUDIO_DELAY_RESERVED = 0x3, 2512} HDMI_AUDIO_DELAY_EN; 2513typedef enum HDMI_AUDIO_SEND_MAX_PACKETS { 2514 HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0x0, 2515 HDMI_SEND_MAX_AUDIO_PACKETS = 0x1, 2516} HDMI_AUDIO_SEND_MAX_PACKETS; 2517typedef enum HDMI_ACR_SEND { 2518 HDMI_ACR_NOT_SEND = 0x0, 2519 HDMI_ACR_PKT_SEND = 0x1, 2520} HDMI_ACR_SEND; 2521typedef enum HDMI_ACR_CONT { 2522 HDMI_ACR_CONT_DISABLE = 0x0, 2523 HDMI_ACR_CONT_ENABLE = 0x1, 2524} HDMI_ACR_CONT; 2525typedef enum HDMI_ACR_SELECT { 2526 HDMI_ACR_SELECT_HW = 0x0, 2527 HDMI_ACR_SELECT_32K = 0x1, 2528 HDMI_ACR_SELECT_44K = 0x2, 2529 HDMI_ACR_SELECT_48K = 0x3, 2530} HDMI_ACR_SELECT; 2531typedef enum HDMI_ACR_SOURCE { 2532 HDMI_ACR_SOURCE_HW = 0x0, 2533 HDMI_ACR_SOURCE_SW = 0x1, 2534} HDMI_ACR_SOURCE; 2535typedef enum HDMI_ACR_N_MULTIPLE { 2536 HDMI_ACR_0_MULTIPLE_RESERVED = 0x0, 2537 HDMI_ACR_1_MULTIPLE = 0x1, 2538 HDMI_ACR_2_MULTIPLE = 0x2, 2539 HDMI_ACR_3_MULTIPLE_RESERVED = 0x3, 2540 HDMI_ACR_4_MULTIPLE = 0x4, 2541 HDMI_ACR_5_MULTIPLE_RESERVED = 0x5, 2542 HDMI_ACR_6_MULTIPLE_RESERVED = 0x6, 2543 HDMI_ACR_7_MULTIPLE_RESERVED = 0x7, 2544} HDMI_ACR_N_MULTIPLE; 2545typedef enum HDMI_ACR_AUDIO_PRIORITY { 2546 HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0x0, 2547 HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 0x1, 2548} HDMI_ACR_AUDIO_PRIORITY; 2549typedef enum HDMI_NULL_SEND { 2550 HDMI_NULL_NOT_SEND = 0x0, 2551 HDMI_NULL_PKT_SEND = 0x1, 2552} HDMI_NULL_SEND; 2553typedef enum HDMI_GC_SEND { 2554 HDMI_GC_NOT_SEND = 0x0, 2555 HDMI_GC_PKT_SEND = 0x1, 2556} HDMI_GC_SEND; 2557typedef enum HDMI_GC_CONT { 2558 HDMI_GC_CONT_DISABLE = 0x0, 2559 HDMI_GC_CONT_ENABLE = 0x1, 2560} HDMI_GC_CONT; 2561typedef enum HDMI_ISRC_SEND { 2562 HDMI_ISRC_NOT_SEND = 0x0, 2563 HDMI_ISRC_PKT_SEND = 0x1, 2564} HDMI_ISRC_SEND; 2565typedef enum HDMI_ISRC_CONT { 2566 HDMI_ISRC_CONT_DISABLE = 0x0, 2567 HDMI_ISRC_CONT_ENABLE = 0x1, 2568} HDMI_ISRC_CONT; 2569typedef enum HDMI_AVI_INFO_SEND { 2570 HDMI_AVI_INFO_NOT_SEND = 0x0, 2571 HDMI_AVI_INFO_PKT_SEND = 0x1, 2572} HDMI_AVI_INFO_SEND; 2573typedef enum HDMI_AVI_INFO_CONT { 2574 HDMI_AVI_INFO_CONT_DISABLE = 0x0, 2575 HDMI_AVI_INFO_CONT_ENABLE = 0x1, 2576} HDMI_AVI_INFO_CONT; 2577typedef enum HDMI_AUDIO_INFO_SEND { 2578 HDMI_AUDIO_INFO_NOT_SEND = 0x0, 2579 HDMI_AUDIO_INFO_PKT_SEND = 0x1, 2580} HDMI_AUDIO_INFO_SEND; 2581typedef enum HDMI_AUDIO_INFO_CONT { 2582 HDMI_AUDIO_INFO_CONT_DISABLE = 0x0, 2583 HDMI_AUDIO_INFO_CONT_ENABLE = 0x1, 2584} HDMI_AUDIO_INFO_CONT; 2585typedef enum HDMI_MPEG_INFO_SEND { 2586 HDMI_MPEG_INFO_NOT_SEND = 0x0, 2587 HDMI_MPEG_INFO_PKT_SEND = 0x1, 2588} HDMI_MPEG_INFO_SEND; 2589typedef enum HDMI_MPEG_INFO_CONT { 2590 HDMI_MPEG_INFO_CONT_DISABLE = 0x0, 2591 HDMI_MPEG_INFO_CONT_ENABLE = 0x1, 2592} HDMI_MPEG_INFO_CONT; 2593typedef enum HDMI_GENERIC0_SEND { 2594 HDMI_GENERIC0_NOT_SEND = 0x0, 2595 HDMI_GENERIC0_PKT_SEND = 0x1, 2596} HDMI_GENERIC0_SEND; 2597typedef enum HDMI_GENERIC0_CONT { 2598 HDMI_GENERIC0_CONT_DISABLE = 0x0, 2599 HDMI_GENERIC0_CONT_ENABLE = 0x1, 2600} HDMI_GENERIC0_CONT; 2601typedef enum HDMI_GENERIC1_SEND { 2602 HDMI_GENERIC1_NOT_SEND = 0x0, 2603 HDMI_GENERIC1_PKT_SEND = 0x1, 2604} HDMI_GENERIC1_SEND; 2605typedef enum HDMI_GENERIC1_CONT { 2606 HDMI_GENERIC1_CONT_DISABLE = 0x0, 2607 HDMI_GENERIC1_CONT_ENABLE = 0x1, 2608} HDMI_GENERIC1_CONT; 2609typedef enum HDMI_GC_AVMUTE_CONT { 2610 HDMI_GC_AVMUTE_CONT_DISABLE = 0x0, 2611 HDMI_GC_AVMUTE_CONT_ENABLE = 0x1, 2612} HDMI_GC_AVMUTE_CONT; 2613typedef enum HDMI_PACKING_PHASE_OVERRIDE { 2614 HDMI_PACKING_PHASE_SET_BY_HW = 0x0, 2615 HDMI_PACKING_PHASE_SET_BY_SW = 0x1, 2616} HDMI_PACKING_PHASE_OVERRIDE; 2617typedef enum HDMI_GENERIC2_SEND { 2618 HDMI_GENERIC2_NOT_SEND = 0x0, 2619 HDMI_GENERIC2_PKT_SEND = 0x1, 2620} HDMI_GENERIC2_SEND; 2621typedef enum HDMI_GENERIC2_CONT { 2622 HDMI_GENERIC2_CONT_DISABLE = 0x0, 2623 HDMI_GENERIC2_CONT_ENABLE = 0x1, 2624} HDMI_GENERIC2_CONT; 2625typedef enum HDMI_GENERIC3_SEND { 2626 HDMI_GENERIC3_NOT_SEND = 0x0, 2627 HDMI_GENERIC3_PKT_SEND = 0x1, 2628} HDMI_GENERIC3_SEND; 2629typedef enum HDMI_GENERIC3_CONT { 2630 HDMI_GENERIC3_CONT_DISABLE = 0x0, 2631 HDMI_GENERIC3_CONT_ENABLE = 0x1, 2632} HDMI_GENERIC3_CONT; 2633typedef enum TMDS_PIXEL_ENCODING { 2634 TMDS_PIXEL_ENCODING_444_OR_420 = 0x0, 2635 TMDS_PIXEL_ENCODING_422 = 0x1, 2636} TMDS_PIXEL_ENCODING; 2637typedef enum TMDS_COLOR_FORMAT { 2638 TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP= 0x0, 2639 TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 0x1, 2640 TMDS_COLOR_FORMAT_DUAL30BPP = 0x2, 2641 TMDS_COLOR_FORMAT_RESERVED = 0x3, 2642} TMDS_COLOR_FORMAT; 2643typedef enum TMDS_STEREOSYNC_CTL_SEL_REG { 2644 TMDS_STEREOSYNC_CTL0 = 0x0, 2645 TMDS_STEREOSYNC_CTL1 = 0x1, 2646 TMDS_STEREOSYNC_CTL2 = 0x2, 2647 TMDS_STEREOSYNC_CTL3 = 0x3, 2648} TMDS_STEREOSYNC_CTL_SEL_REG; 2649typedef enum TMDS_CTL0_DATA_SEL { 2650 TMDS_CTL0_DATA_SEL0_RESERVED = 0x0, 2651 TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 0x1, 2652 TMDS_CTL0_DATA_SEL2_VSYNC = 0x2, 2653 TMDS_CTL0_DATA_SEL3_RESERVED = 0x3, 2654 TMDS_CTL0_DATA_SEL4_HSYNC = 0x4, 2655 TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 0x5, 2656 TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 0x6, 2657 TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 0x7, 2658} TMDS_CTL0_DATA_SEL; 2659typedef enum TMDS_CTL0_DATA_INVERT { 2660 TMDS_CTL0_DATA_NORMAL = 0x0, 2661 TMDS_CTL0_DATA_INVERT_EN = 0x1, 2662} TMDS_CTL0_DATA_INVERT; 2663typedef enum TMDS_CTL0_DATA_MODULATION { 2664 TMDS_CTL0_DATA_MODULATION_DISABLE = 0x0, 2665 TMDS_CTL0_DATA_MODULATION_BIT0 = 0x1, 2666 TMDS_CTL0_DATA_MODULATION_BIT1 = 0x2, 2667 TMDS_CTL0_DATA_MODULATION_BIT2 = 0x3, 2668} TMDS_CTL0_DATA_MODULATION; 2669typedef enum TMDS_CTL0_PATTERN_OUT_EN { 2670 TMDS_CTL0_PATTERN_OUT_DISABLE = 0x0, 2671 TMDS_CTL0_PATTERN_OUT_ENABLE = 0x1, 2672} TMDS_CTL0_PATTERN_OUT_EN; 2673typedef enum TMDS_CTL1_DATA_SEL { 2674 TMDS_CTL1_DATA_SEL0_RESERVED = 0x0, 2675 TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 0x1, 2676 TMDS_CTL1_DATA_SEL2_VSYNC = 0x2, 2677 TMDS_CTL1_DATA_SEL3_RESERVED = 0x3, 2678 TMDS_CTL1_DATA_SEL4_HSYNC = 0x4, 2679 TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 0x5, 2680 TMDS_CTL1_DATA_SEL8_BLANK_TIME = 0x6, 2681 TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 0x7, 2682} TMDS_CTL1_DATA_SEL; 2683typedef enum TMDS_CTL1_DATA_INVERT { 2684 TMDS_CTL1_DATA_NORMAL = 0x0, 2685 TMDS_CTL1_DATA_INVERT_EN = 0x1, 2686} TMDS_CTL1_DATA_INVERT; 2687typedef enum TMDS_CTL1_DATA_MODULATION { 2688 TMDS_CTL1_DATA_MODULATION_DISABLE = 0x0, 2689 TMDS_CTL1_DATA_MODULATION_BIT0 = 0x1, 2690 TMDS_CTL1_DATA_MODULATION_BIT1 = 0x2, 2691 TMDS_CTL1_DATA_MODULATION_BIT2 = 0x3, 2692} TMDS_CTL1_DATA_MODULATION; 2693typedef enum TMDS_CTL1_PATTERN_OUT_EN { 2694 TMDS_CTL1_PATTERN_OUT_DISABLE = 0x0, 2695 TMDS_CTL1_PATTERN_OUT_ENABLE = 0x1, 2696} TMDS_CTL1_PATTERN_OUT_EN; 2697typedef enum TMDS_CTL2_DATA_SEL { 2698 TMDS_CTL2_DATA_SEL0_RESERVED = 0x0, 2699 TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 0x1, 2700 TMDS_CTL2_DATA_SEL2_VSYNC = 0x2, 2701 TMDS_CTL2_DATA_SEL3_RESERVED = 0x3, 2702 TMDS_CTL2_DATA_SEL4_HSYNC = 0x4, 2703 TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 0x5, 2704 TMDS_CTL2_DATA_SEL8_BLANK_TIME = 0x6, 2705 TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 0x7, 2706} TMDS_CTL2_DATA_SEL; 2707typedef enum TMDS_CTL2_DATA_INVERT { 2708 TMDS_CTL2_DATA_NORMAL = 0x0, 2709 TMDS_CTL2_DATA_INVERT_EN = 0x1, 2710} TMDS_CTL2_DATA_INVERT; 2711typedef enum TMDS_CTL2_DATA_MODULATION { 2712 TMDS_CTL2_DATA_MODULATION_DISABLE = 0x0, 2713 TMDS_CTL2_DATA_MODULATION_BIT0 = 0x1, 2714 TMDS_CTL2_DATA_MODULATION_BIT1 = 0x2, 2715 TMDS_CTL2_DATA_MODULATION_BIT2 = 0x3, 2716} TMDS_CTL2_DATA_MODULATION; 2717typedef enum TMDS_CTL2_PATTERN_OUT_EN { 2718 TMDS_CTL2_PATTERN_OUT_DISABLE = 0x0, 2719 TMDS_CTL2_PATTERN_OUT_ENABLE = 0x1, 2720} TMDS_CTL2_PATTERN_OUT_EN; 2721typedef enum TMDS_CTL3_DATA_INVERT { 2722 TMDS_CTL3_DATA_NORMAL = 0x0, 2723 TMDS_CTL3_DATA_INVERT_EN = 0x1, 2724} TMDS_CTL3_DATA_INVERT; 2725typedef enum TMDS_CTL3_DATA_MODULATION { 2726 TMDS_CTL3_DATA_MODULATION_DISABLE = 0x0, 2727 TMDS_CTL3_DATA_MODULATION_BIT0 = 0x1, 2728 TMDS_CTL3_DATA_MODULATION_BIT1 = 0x2, 2729 TMDS_CTL3_DATA_MODULATION_BIT2 = 0x3, 2730} TMDS_CTL3_DATA_MODULATION; 2731typedef enum TMDS_CTL3_PATTERN_OUT_EN { 2732 TMDS_CTL3_PATTERN_OUT_DISABLE = 0x0, 2733 TMDS_CTL3_PATTERN_OUT_ENABLE = 0x1, 2734} TMDS_CTL3_PATTERN_OUT_EN; 2735typedef enum TMDS_CTL3_DATA_SEL { 2736 TMDS_CTL3_DATA_SEL0_RESERVED = 0x0, 2737 TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 0x1, 2738 TMDS_CTL3_DATA_SEL2_VSYNC = 0x2, 2739 TMDS_CTL3_DATA_SEL3_RESERVED = 0x3, 2740 TMDS_CTL3_DATA_SEL4_HSYNC = 0x4, 2741 TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 0x5, 2742 TMDS_CTL3_DATA_SEL8_BLANK_TIME = 0x6, 2743 TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 0x7, 2744} TMDS_CTL3_DATA_SEL; 2745typedef enum DIG_FE_CNTL_SOURCE_SELECT { 2746 DIG_FE_SOURCE_FROM_FMT0 = 0x0, 2747 DIG_FE_SOURCE_FROM_FMT1 = 0x1, 2748 DIG_FE_SOURCE_FROM_FMT2 = 0x2, 2749 DIG_FE_SOURCE_FROM_FMT3 = 0x3, 2750 DIG_FE_SOURCE_FROM_FMT4 = 0x4, 2751 DIG_FE_SOURCE_FROM_FMT5 = 0x5, 2752} DIG_FE_CNTL_SOURCE_SELECT; 2753typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT { 2754 DIG_FE_STEREOSYNC_FROM_FMT0 = 0x0, 2755 DIG_FE_STEREOSYNC_FROM_FMT1 = 0x1, 2756 DIG_FE_STEREOSYNC_FROM_FMT2 = 0x2, 2757 DIG_FE_STEREOSYNC_FROM_FMT3 = 0x3, 2758 DIG_FE_STEREOSYNC_FROM_FMT4 = 0x4, 2759 DIG_FE_STEREOSYNC_FROM_FMT5 = 0x5, 2760} DIG_FE_CNTL_STEREOSYNC_SELECT; 2761typedef enum DIG_FIFO_READ_CLOCK_SRC { 2762 DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0x0, 2763 DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 0x1, 2764} DIG_FIFO_READ_CLOCK_SRC; 2765typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL { 2766 DIG_OUTPUT_CRC_ON_LINK0 = 0x0, 2767 DIG_OUTPUT_CRC_ON_LINK1 = 0x1, 2768} DIG_OUTPUT_CRC_CNTL_LINK_SEL; 2769typedef enum DIG_OUTPUT_CRC_DATA_SEL { 2770 DIG_OUTPUT_CRC_FOR_FULLFRAME = 0x0, 2771 DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 0x1, 2772 DIG_OUTPUT_CRC_FOR_VBI = 0x2, 2773 DIG_OUTPUT_CRC_FOR_AUDIO = 0x3, 2774} DIG_OUTPUT_CRC_DATA_SEL; 2775typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN { 2776 DIG_IN_NORMAL_OPERATION = 0x0, 2777 DIG_IN_DEBUG_MODE = 0x1, 2778} DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN; 2779typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL { 2780 DIG_10BIT_TEST_PATTERN = 0x0, 2781 DIG_ALTERNATING_TEST_PATTERN = 0x1, 2782} DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL; 2783typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN { 2784 DIG_TEST_PATTERN_NORMAL = 0x0, 2785 DIG_TEST_PATTERN_RANDOM = 0x1, 2786} DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN; 2787typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET { 2788 DIG_RANDOM_PATTERN_ENABLED = 0x0, 2789 DIG_RANDOM_PATTERN_RESETED = 0x1, 2790} DIG_TEST_PATTERN_RANDOM_PATTERN_RESET; 2791typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN { 2792 DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0x0, 2793 DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 0x1, 2794} DIG_TEST_PATTERN_EXTERNAL_RESET_EN; 2795typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT { 2796 DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0x0, 2797 DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 0x1, 2798} DIG_RANDOM_PATTERN_SEED_RAN_PAT; 2799typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL { 2800 DIG_FIFO_USE_OVERWRITE_LEVEL = 0x0, 2801 DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 0x1, 2802} DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL; 2803typedef enum DIG_FIFO_ERROR_ACK { 2804 DIG_FIFO_ERROR_ACK_INT = 0x0, 2805 DIG_FIFO_ERROR_NOT_ACK = 0x1, 2806} DIG_FIFO_ERROR_ACK; 2807typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE { 2808 DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0x0, 2809 DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 0x1, 2810} DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE; 2811typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX { 2812 DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0x0, 2813 DIG_FIFO_FORCE_RECOMP_MINMAX = 0x1, 2814} DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX; 2815typedef enum DIG_DISPCLK_SWITCH_CNTL_SWITCH_POINT { 2816 DIG_DISPCLK_SWITCH_AT_EARLY_VBLANK = 0x0, 2817 DIG_DISPCLK_SWITCH_AT_FIRST_HSYNC = 0x1, 2818} DIG_DISPCLK_SWITCH_CNTL_SWITCH_POINT; 2819typedef enum DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK { 2820 DIG_DISPCLK_SWITCH_ALLOWED_ACK_INT = 0x0, 2821 DIG_DISPCLK_SWITCH_ALLOWED_INT_NOT_ACK = 0x1, 2822} DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK; 2823typedef enum DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK { 2824 DIG_DISPCLK_SWITCH_ALLOWED_MASK_INT = 0x0, 2825 DIG_DISPCLK_SWITCH_ALLOWED_INT_UNMASK = 0x1, 2826} DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK; 2827typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK { 2828 AFMT_INTERRUPT_DISABLE = 0x0, 2829 AFMT_INTERRUPT_ENABLE = 0x1, 2830} AFMT_INTERRUPT_STATUS_CHG_MASK; 2831typedef enum HDMI_GC_AVMUTE { 2832 HDMI_GC_AVMUTE_SET = 0x0, 2833 HDMI_GC_AVMUTE_UNSET = 0x1, 2834} HDMI_GC_AVMUTE; 2835typedef enum HDMI_DEFAULT_PAHSE { 2836 HDMI_DEFAULT_PHASE_IS_0 = 0x0, 2837 HDMI_DEFAULT_PHASE_IS_1 = 0x1, 2838} HDMI_DEFAULT_PAHSE; 2839typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD { 2840 AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS= 0x0, 2841 AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 0x1, 2842} AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD; 2843typedef enum AUDIO_LAYOUT_SELECT { 2844 AUDIO_LAYOUT_0 = 0x0, 2845 AUDIO_LAYOUT_1 = 0x1, 2846} AUDIO_LAYOUT_SELECT; 2847typedef enum AFMT_AUDIO_CRC_CONTROL_CONT { 2848 AFMT_AUDIO_CRC_ONESHOT = 0x0, 2849 AFMT_AUDIO_CRC_AUTO_RESTART = 0x1, 2850} AFMT_AUDIO_CRC_CONTROL_CONT; 2851typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE { 2852 AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0x0, 2853 AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 0x1, 2854} AFMT_AUDIO_CRC_CONTROL_SOURCE; 2855typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL { 2856 AFMT_AUDIO_CRC_CH0_SIG = 0x0, 2857 AFMT_AUDIO_CRC_CH1_SIG = 0x1, 2858 AFMT_AUDIO_CRC_CH2_SIG = 0x2, 2859 AFMT_AUDIO_CRC_CH3_SIG = 0x3, 2860 AFMT_AUDIO_CRC_CH4_SIG = 0x4, 2861 AFMT_AUDIO_CRC_CH5_SIG = 0x5, 2862 AFMT_AUDIO_CRC_CH6_SIG = 0x6, 2863 AFMT_AUDIO_CRC_CH7_SIG = 0x7, 2864 AFMT_AUDIO_CRC_RESERVED = 0x8, 2865 AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 0x9, 2866} AFMT_AUDIO_CRC_CONTROL_CH_SEL; 2867typedef enum AFMT_RAMP_CONTROL0_SIGN { 2868 AFMT_RAMP_SIGNED = 0x0, 2869 AFMT_RAMP_UNSIGNED = 0x1, 2870} AFMT_RAMP_CONTROL0_SIGN; 2871typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND { 2872 AFMT_AUDIO_PACKET_SENT_DISABLED = 0x0, 2873 AFMT_AUDIO_PACKET_SENT_ENABLED = 0x1, 2874} AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND; 2875typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS { 2876 AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED= 0x0, 2877 AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 0x1, 2878} AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS; 2879typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE { 2880 AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0x0, 2881 AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 0x1, 2882} AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE; 2883typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT { 2884 AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0x0, 2885 AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 0x1, 2886 AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 0x2, 2887 AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 0x3, 2888 AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 0x4, 2889 AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 0x5, 2890 AFMT_AUDIO_SRC_RESERVED = 0x6, 2891} AFMT_AUDIO_SRC_CONTROL_SELECT; 2892typedef enum DIG_BE_CNTL_MODE { 2893 DIG_BE_DP_SST_MODE = 0x0, 2894 DIG_BE_RESERVED1 = 0x1, 2895 DIG_BE_TMDS_DVI_MODE = 0x2, 2896 DIG_BE_TMDS_HDMI_MODE = 0x3, 2897 DIG_BE_SDVO_RESERVED = 0x4, 2898 DIG_BE_DP_MST_MODE = 0x5, 2899 DIG_BE_RESERVED2 = 0x6, 2900 DIG_BE_RESERVED3 = 0x7, 2901} DIG_BE_CNTL_MODE; 2902typedef enum DIG_BE_CNTL_HPD_SELECT { 2903 DIG_BE_CNTL_HPD1 = 0x0, 2904 DIG_BE_CNTL_HPD2 = 0x1, 2905 DIG_BE_CNTL_HPD3 = 0x2, 2906 DIG_BE_CNTL_HPD4 = 0x3, 2907 DIG_BE_CNTL_HPD5 = 0x4, 2908 DIG_BE_CNTL_HPD6 = 0x5, 2909} DIG_BE_CNTL_HPD_SELECT; 2910typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT { 2911 LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0x0, 2912 LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 0x1, 2913} LVTMA_RANDOM_PATTERN_SEED_RAN_PAT; 2914typedef enum TMDS_SYNC_PHASE { 2915 TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0x0, 2916 TMDS_SYNC_PHASE_ON_FRAME_START = 0x1, 2917} TMDS_SYNC_PHASE; 2918typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL { 2919 TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0x0, 2920 TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 0x1, 2921} TMDS_DATA_SYNCHRONIZATION_DSINTSEL; 2922typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK { 2923 TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0x0, 2924 TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 0x1, 2925} TMDS_TRANSMITTER_ENABLE_HPD_MASK; 2926typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK { 2927 TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0x0, 2928 TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 0x1, 2929} TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK; 2930typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK { 2931 TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0x0, 2932 TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 0x1, 2933} TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK; 2934typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK { 2935 TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0x0, 2936 TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON= 0x1, 2937 TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 0x2, 2938 TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 0x3, 2939} TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK; 2940typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA { 2941 TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0x0, 2942 TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 0x1, 2943} TMDS_TRANSMITTER_CONTROL_IDSCKSELA; 2944typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB { 2945 TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0x0, 2946 TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 0x1, 2947} TMDS_TRANSMITTER_CONTROL_IDSCKSELB; 2948typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN { 2949 TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0x0, 2950 TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 0x1, 2951} TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN; 2952typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK { 2953 TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0x0, 2954 TMDS_TRANSMITTER_PLL_RST_ON_HPD = 0x1, 2955} TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK; 2956typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS { 2957 TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0x0, 2958 TMDS_TRANSMITTER_TMCLK_FROM_PADS = 0x1, 2959} TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS; 2960typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS { 2961 TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0x0, 2962 TMDS_TRANSMITTER_TDCLK_FROM_PADS = 0x1, 2963} TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS; 2964typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN { 2965 TMDS_TRANSMITTER_PLLSEL_BY_HW = 0x0, 2966 TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 0x1, 2967} TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN; 2968typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA { 2969 TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0x0, 2970 TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 0x1, 2971} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA; 2972typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB { 2973 TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0x0, 2974 TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 0x1, 2975} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB; 2976typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA { 2977 TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0x0, 2978 TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 0x1, 2979 TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 0x2, 2980 TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 0x3, 2981} TMDS_REG_TEST_OUTPUTA_CNTLA; 2982typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB { 2983 TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0x0, 2984 TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 0x1, 2985 TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 0x2, 2986 TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 0x3, 2987} TMDS_REG_TEST_OUTPUTB_CNTLB; 2988typedef enum DP_LINK_TRAINING_COMPLETE { 2989 DP_LINK_TRAINING_NOT_COMPLETE = 0x0, 2990 DP_LINK_TRAINING_ALREADY_COMPLETE = 0x1, 2991} DP_LINK_TRAINING_COMPLETE; 2992typedef enum DP_EMBEDDED_PANEL_MODE { 2993 DP_EXTERNAL_PANEL = 0x0, 2994 DP_EMBEDDED_PANEL = 0x1, 2995} DP_EMBEDDED_PANEL_MODE; 2996typedef enum DP_PIXEL_ENCODING { 2997 DP_PIXEL_ENCODING_RGB444 = 0x0, 2998 DP_PIXEL_ENCODING_YCBCR422 = 0x1, 2999 DP_PIXEL_ENCODING_YCBCR444 = 0x2, 3000 DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x3, 3001 DP_PIXEL_ENCODING_Y_ONLY = 0x4, 3002 DP_PIXEL_ENCODING_YCBCR420 = 0x5, 3003 DP_PIXEL_ENCODING_RESERVED = 0x6, 3004} DP_PIXEL_ENCODING; 3005typedef enum DP_DYN_RANGE { 3006 DP_DYN_VESA_RANGE = 0x0, 3007 DP_DYN_CEA_RANGE = 0x1, 3008} DP_DYN_RANGE; 3009typedef enum DP_YCBCR_RANGE { 3010 DP_YCBCR_RANGE_BT601_5 = 0x0, 3011 DP_YCBCR_RANGE_BT709_5 = 0x1, 3012} DP_YCBCR_RANGE; 3013typedef enum DP_COMPONENT_DEPTH { 3014 DP_COMPONENT_DEPTH_6BPC = 0x0, 3015 DP_COMPONENT_DEPTH_8BPC = 0x1, 3016 DP_COMPONENT_DEPTH_10BPC = 0x2, 3017 DP_COMPONENT_DEPTH_12BPC = 0x3, 3018 DP_COMPONENT_DEPTH_16BPC = 0x4, 3019 DP_COMPONENT_DEPTH_RESERVED = 0x5, 3020} DP_COMPONENT_DEPTH; 3021typedef enum DP_MSA_MISC0_OVERRIDE_ENABLE { 3022 MSA_MISC0_OVERRIDE_DISABLE = 0x0, 3023 MSA_MISC0_OVERRIDE_ENABLE = 0x1, 3024} DP_MSA_MISC0_OVERRIDE_ENABLE; 3025typedef enum DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE { 3026 MSA_MISC1_BIT7_OVERRIDE_DISABLE = 0x0, 3027 MSA_MISC1_BIT7_OVERRIDE_ENABLE = 0x1, 3028} DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE; 3029typedef enum DP_UDI_LANES { 3030 DP_UDI_1_LANE = 0x0, 3031 DP_UDI_2_LANES = 0x1, 3032 DP_UDI_LANES_RESERVED = 0x2, 3033 DP_UDI_4_LANES = 0x3, 3034} DP_UDI_LANES; 3035typedef enum DP_VID_STREAM_DIS_DEFER { 3036 DP_VID_STREAM_DIS_NO_DEFER = 0x0, 3037 DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 0x1, 3038 DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 0x2, 3039} DP_VID_STREAM_DIS_DEFER; 3040typedef enum DP_STEER_OVERFLOW_ACK { 3041 DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0x0, 3042 DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 0x1, 3043} DP_STEER_OVERFLOW_ACK; 3044typedef enum DP_STEER_OVERFLOW_MASK { 3045 DP_STEER_OVERFLOW_MASKED = 0x0, 3046 DP_STEER_OVERFLOW_UNMASK = 0x1, 3047} DP_STEER_OVERFLOW_MASK; 3048typedef enum DP_TU_OVERFLOW_ACK { 3049 DP_TU_OVERFLOW_ACK_NO_EFFECT = 0x0, 3050 DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 0x1, 3051} DP_TU_OVERFLOW_ACK; 3052typedef enum DP_VID_TIMING_MODE { 3053 DP_VID_TIMING_MODE_ASYNC = 0x0, 3054 DP_VID_TIMING_MODE_SYNC = 0x1, 3055} DP_VID_TIMING_MODE; 3056typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE { 3057 DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0x0, 3058 DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 0x1, 3059} DP_VID_M_N_DOUBLE_BUFFER_MODE; 3060typedef enum DP_VID_M_N_GEN_EN { 3061 DP_VID_M_N_PROGRAMMED_VIA_REG = 0x0, 3062 DP_VID_M_N_CALC_AUTO = 0x1, 3063} DP_VID_M_N_GEN_EN; 3064typedef enum DP_VID_M_DOUBLE_VALUE_EN { 3065 DP_VID_M_INPUT_PIXEL_RATE = 0x0, 3066 DP_VID_M_DOUBLE_INPUT_PIXEL_RATE = 0x1, 3067} DP_VID_M_DOUBLE_VALUE_EN; 3068typedef enum DP_VID_ENHANCED_FRAME_MODE { 3069 VID_NORMAL_FRAME_MODE = 0x0, 3070 VID_ENHANCED_MODE = 0x1, 3071} DP_VID_ENHANCED_FRAME_MODE; 3072typedef enum DP_VID_MSA_TOP_FIELD_MODE { 3073 DP_TOP_FIELD_ONLY = 0x0, 3074 DP_TOP_PLUS_BOTTOM_FIELD = 0x1, 3075} DP_VID_MSA_TOP_FIELD_MODE; 3076typedef enum DP_VID_VBID_FIELD_POL { 3077 DP_VID_VBID_FIELD_POL_NORMAL = 0x0, 3078 DP_VID_VBID_FIELD_POL_INV = 0x1, 3079} DP_VID_VBID_FIELD_POL; 3080typedef enum DP_VID_STREAM_DISABLE_ACK { 3081 ID_STREAM_DISABLE_NO_ACK = 0x0, 3082 ID_STREAM_DISABLE_ACKED = 0x1, 3083} DP_VID_STREAM_DISABLE_ACK; 3084typedef enum DP_VID_STREAM_DISABLE_MASK { 3085 VID_STREAM_DISABLE_MASKED = 0x0, 3086 VID_STREAM_DISABLE_UNMASK = 0x1, 3087} DP_VID_STREAM_DISABLE_MASK; 3088typedef enum DPHY_ATEST_SEL_LANE0 { 3089 DPHY_ATEST_LANE0_PRBS_PATTERN = 0x0, 3090 DPHY_ATEST_LANE0_REG_PATTERN = 0x1, 3091} DPHY_ATEST_SEL_LANE0; 3092typedef enum DPHY_ATEST_SEL_LANE1 { 3093 DPHY_ATEST_LANE1_PRBS_PATTERN = 0x0, 3094 DPHY_ATEST_LANE1_REG_PATTERN = 0x1, 3095} DPHY_ATEST_SEL_LANE1; 3096typedef enum DPHY_ATEST_SEL_LANE2 { 3097 DPHY_ATEST_LANE2_PRBS_PATTERN = 0x0, 3098 DPHY_ATEST_LANE2_REG_PATTERN = 0x1, 3099} DPHY_ATEST_SEL_LANE2; 3100typedef enum DPHY_ATEST_SEL_LANE3 { 3101 DPHY_ATEST_LANE3_PRBS_PATTERN = 0x0, 3102 DPHY_ATEST_LANE3_REG_PATTERN = 0x1, 3103} DPHY_ATEST_SEL_LANE3; 3104typedef enum DPHY_BYPASS { 3105 DPHY_8B10B_OUTPUT = 0x0, 3106 DPHY_DBG_OUTPUT = 0x1, 3107} DPHY_BYPASS; 3108typedef enum DPHY_SKEW_BYPASS { 3109 DPHY_WITH_SKEW = 0x0, 3110 DPHY_NO_SKEW = 0x1, 3111} DPHY_SKEW_BYPASS; 3112typedef enum DPHY_TRAINING_PATTERN_SEL { 3113 DPHY_TRAINING_PATTERN_1 = 0x0, 3114 DPHY_TRAINING_PATTERN_2 = 0x1, 3115 DPHY_TRAINING_PATTERN_3 = 0x2, 3116 DPHY_TRAINING_PATTERN_4 = 0x3, 3117} DPHY_TRAINING_PATTERN_SEL; 3118typedef enum DPHY_8B10B_RESET { 3119 DPHY_8B10B_NOT_RESET = 0x0, 3120 DPHY_8B10B_RESETET = 0x1, 3121} DPHY_8B10B_RESET; 3122typedef enum DP_DPHY_8B10B_EXT_DISP { 3123 DP_DPHY_8B10B_EXT_DISP_ZERO = 0x0, 3124 DP_DPHY_8B10B_EXT_DISP_ONE = 0x1, 3125} DP_DPHY_8B10B_EXT_DISP; 3126typedef enum DPHY_8B10B_CUR_DISP { 3127 DPHY_8B10B_CUR_DISP_ZERO = 0x0, 3128 DPHY_8B10B_CUR_DISP_ONE = 0x1, 3129} DPHY_8B10B_CUR_DISP; 3130typedef enum DPHY_PRBS_EN { 3131 DPHY_PRBS_DISABLE = 0x0, 3132 DPHY_PRBS_ENABLE = 0x1, 3133} DPHY_PRBS_EN; 3134typedef enum DPHY_PRBS_SEL { 3135 DPHY_PRBS7_SELECTED = 0x0, 3136 DPHY_PRBS23_SELECTED = 0x1, 3137 DPHY_PRBS11_SELECTED = 0x2, 3138} DPHY_PRBS_SEL; 3139typedef enum DPHY_LOAD_BS_COUNT_START { 3140 DPHY_LOAD_BS_COUNT_STARTED = 0x0, 3141 DPHY_LOAD_BS_COUNT_NOT_STARTED = 0x1, 3142} DPHY_LOAD_BS_COUNT_START; 3143typedef enum DPHY_CRC_EN { 3144 DPHY_CRC_DISABLED = 0x0, 3145 DPHY_CRC_ENABLED = 0x1, 3146} DPHY_CRC_EN; 3147typedef enum DPHY_CRC_CONT_EN { 3148 DPHY_CRC_ONE_SHOT = 0x0, 3149 DPHY_CRC_CONTINUOUS = 0x1, 3150} DPHY_CRC_CONT_EN; 3151typedef enum DPHY_CRC_FIELD { 3152 DPHY_CRC_START_FROM_TOP_FIELD = 0x0, 3153 DPHY_CRC_START_FROM_BOTTOM_FIELD = 0x1, 3154} DPHY_CRC_FIELD; 3155typedef enum DPHY_CRC_SEL { 3156 DPHY_CRC_LANE0_SELECTED = 0x0, 3157 DPHY_CRC_LANE1_SELECTED = 0x1, 3158 DPHY_CRC_LANE2_SELECTED = 0x2, 3159 DPHY_CRC_LANE3_SELECTED = 0x3, 3160} DPHY_CRC_SEL; 3161typedef enum DPHY_RX_FAST_TRAINING_CAPABLE { 3162 DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0x0, 3163 DPHY_FAST_TRAINING_CAPABLE = 0x1, 3164} DPHY_RX_FAST_TRAINING_CAPABLE; 3165typedef enum DP_SEC_COLLISION_ACK { 3166 DP_SEC_COLLISION_ACK_NO_EFFECT = 0x0, 3167 DP_SEC_COLLISION_ACK_CLR_FLAG = 0x1, 3168} DP_SEC_COLLISION_ACK; 3169typedef enum DP_SEC_AUDIO_MUTE { 3170 DP_SEC_AUDIO_MUTE_HW_CTRL = 0x0, 3171 DP_SEC_AUDIO_MUTE_SW_CTRL = 0x1, 3172} DP_SEC_AUDIO_MUTE; 3173typedef enum DP_SEC_TIMESTAMP_MODE { 3174 DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0x0, 3175 DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 0x1, 3176} DP_SEC_TIMESTAMP_MODE; 3177typedef enum DP_SEC_ASP_PRIORITY { 3178 DP_SEC_ASP_LOW_PRIORITY = 0x0, 3179 DP_SEC_ASP_HIGH_PRIORITY = 0x1, 3180} DP_SEC_ASP_PRIORITY; 3181typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE { 3182 DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0x0, 3183 DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 0x1, 3184} DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE; 3185typedef enum DP_MSE_SAT_UPDATE_ACT { 3186 DP_MSE_SAT_UPDATE_NO_ACTION = 0x0, 3187 DP_MSE_SAT_UPDATE_WITH_TRIGGER = 0x1, 3188 DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 0x2, 3189} DP_MSE_SAT_UPDATE_ACT; 3190typedef enum DP_MSE_LINK_LINE { 3191 DP_MSE_LINK_LINE_32_MTP_LONG = 0x0, 3192 DP_MSE_LINK_LINE_64_MTP_LONG = 0x1, 3193 DP_MSE_LINK_LINE_128_MTP_LONG = 0x2, 3194 DP_MSE_LINK_LINE_256_MTP_LONG = 0x3, 3195} DP_MSE_LINK_LINE; 3196typedef enum DP_MSE_BLANK_CODE { 3197 DP_MSE_BLANK_CODE_SF_FILLED = 0x0, 3198 DP_MSE_BLANK_CODE_ZERO_FILLED = 0x1, 3199} DP_MSE_BLANK_CODE; 3200typedef enum DP_MSE_TIMESTAMP_MODE { 3201 DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0x0, 3202 DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 0x1, 3203} DP_MSE_TIMESTAMP_MODE; 3204typedef enum DP_MSE_ZERO_ENCODER { 3205 DP_MSE_NOT_ZERO_FE_ENCODER = 0x0, 3206 DP_MSE_ZERO_FE_ENCODER = 0x1, 3207} DP_MSE_ZERO_ENCODER; 3208typedef enum DP_MSE_OUTPUT_DPDBG_DATA { 3209 DP_MSE_OUTPUT_DPDBG_DATA_DIS = 0x0, 3210 DP_MSE_OUTPUT_DPDBG_DATA_EN = 0x1, 3211} DP_MSE_OUTPUT_DPDBG_DATA; 3212typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE { 3213 DP_DPHY_HBR2_PASS_THROUGH = 0x0, 3214 DP_DPHY_HBR2_PATTERN_1 = 0x1, 3215 DP_DPHY_HBR2_PATTERN_2_NEG = 0x2, 3216 DP_DPHY_HBR2_PATTERN_3 = 0x3, 3217 DP_DPHY_HBR2_PATTERN_2_POS = 0x6, 3218} DP_DPHY_HBR2_PATTERN_CONTROL_MODE; 3219typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK { 3220 DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0x0, 3221 DPHY_CRC_MST_PHASE_ERROR_ACKED = 0x1, 3222} DPHY_CRC_MST_PHASE_ERROR_ACK; 3223typedef enum DPHY_SW_FAST_TRAINING_START { 3224 DPHY_SW_FAST_TRAINING_NOT_STARTED = 0x0, 3225 DPHY_SW_FAST_TRAINING_STARTED = 0x1, 3226} DPHY_SW_FAST_TRAINING_START; 3227typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN { 3228 DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED= 0x0, 3229 DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 0x1, 3230} DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN; 3231typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK { 3232 DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0x0, 3233 DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 0x1, 3234} DP_DPHY_FAST_TRAINING_COMPLETE_MASK; 3235typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK { 3236 DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0x0, 3237 DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 0x1, 3238} DP_DPHY_FAST_TRAINING_COMPLETE_ACK; 3239typedef enum DP_MSA_V_TIMING_OVERRIDE_EN { 3240 MSA_V_TIMING_OVERRIDE_DISABLED = 0x0, 3241 MSA_V_TIMING_OVERRIDE_ENABLED = 0x1, 3242} DP_MSA_V_TIMING_OVERRIDE_EN; 3243typedef enum DP_SEC_GSP0_PRIORITY { 3244 SEC_GSP0_PRIORITY_LOW = 0x0, 3245 SEC_GSP0_PRIORITY_HIGH = 0x1, 3246} DP_SEC_GSP0_PRIORITY; 3247typedef enum DP_SEC_GSP0_SEND { 3248 NOT_SENT = 0x0, 3249 FORCE_SENT = 0x1, 3250} DP_SEC_GSP0_SEND; 3251typedef enum DP_AUX_CONTROL_HPD_SEL { 3252 DP_AUX_CONTROL_HPD1_SELECTED = 0x0, 3253 DP_AUX_CONTROL_HPD2_SELECTED = 0x1, 3254 DP_AUX_CONTROL_HPD3_SELECTED = 0x2, 3255 DP_AUX_CONTROL_HPD4_SELECTED = 0x3, 3256 DP_AUX_CONTROL_HPD5_SELECTED = 0x4, 3257 DP_AUX_CONTROL_HPD6_SELECTED = 0x5, 3258} DP_AUX_CONTROL_HPD_SEL; 3259typedef enum DP_AUX_CONTROL_TEST_MODE { 3260 DP_AUX_CONTROL_TEST_MODE_DISABLE = 0x0, 3261 DP_AUX_CONTROL_TEST_MODE_ENABLE = 0x1, 3262} DP_AUX_CONTROL_TEST_MODE; 3263typedef enum DP_AUX_SW_CONTROL_SW_GO { 3264 DP_AUX_SW_CONTROL_SW__NOT_GO = 0x0, 3265 DP_AUX_SW_CONTROL_SW__GO = 0x1, 3266} DP_AUX_SW_CONTROL_SW_GO; 3267typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG { 3268 DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0x0, 3269 DP_AUX_SW_CONTROL_LS_READ__TRIG = 0x1, 3270} DP_AUX_SW_CONTROL_LS_READ_TRIG; 3271typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY { 3272 DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0x0, 3273 DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 0x1, 3274 DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 0x2, 3275 DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 0x3, 3276} DP_AUX_ARB_CONTROL_ARB_PRIORITY; 3277typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ { 3278 DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0x0, 3279 DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 0x1, 3280} DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ; 3281typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG { 3282 DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0x0, 3283 DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 0x1, 3284} DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG; 3285typedef enum DP_AUX_INT_ACK { 3286 DP_AUX_INT__NOT_ACK = 0x0, 3287 DP_AUX_INT__ACK = 0x1, 3288} DP_AUX_INT_ACK; 3289typedef enum DP_AUX_LS_UPDATE_ACK { 3290 DP_AUX_INT_LS_UPDATE_NOT_ACK = 0x0, 3291 DP_AUX_INT_LS_UPDATE_ACK = 0x1, 3292} DP_AUX_LS_UPDATE_ACK; 3293typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL { 3294 DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK= 0x0, 3295 DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF= 0x1, 3296} DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL; 3297typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE { 3298 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0x0, 3299 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 0x1, 3300 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 0x2, 3301 DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 0x3, 3302} DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE; 3303typedef enum DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN { 3304 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US = 0x0, 3305 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US = 0x1, 3306 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US = 0x2, 3307 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US = 0x3, 3308 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US = 0x4, 3309 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US = 0x5, 3310 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US = 0x6, 3311 DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US = 0x7, 3312} DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN; 3313typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY { 3314 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0x0, 3315 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US= 0x1, 3316 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US= 0x2, 3317 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US= 0x3, 3318 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US= 0x4, 3319 DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US= 0x5, 3320} DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY; 3321typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW { 3322 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0x0, 3323 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 0x1, 3324 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 0x2, 3325 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD= 0x3, 3326 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD= 0x4, 3327 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD= 0x5, 3328 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD= 0x6, 3329 DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD= 0x7, 3330} DP_AUX_DPHY_RX_CONTROL_START_WINDOW; 3331typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW { 3332 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD= 0x0, 3333 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD= 0x1, 3334 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD= 0x2, 3335 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD= 0x3, 3336 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD= 0x4, 3337 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD= 0x5, 3338 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD= 0x6, 3339 DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD= 0x7, 3340} DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW; 3341typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN { 3342 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES= 0x0, 3343 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES= 0x1, 3344 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES= 0x2, 3345 DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED= 0x3, 3346} DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN; 3347typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT { 3348 DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT= 0x0, 3349 DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT= 0x1, 3350} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT; 3351typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START { 3352 DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START= 0x0, 3353 DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START= 0x1, 3354} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START; 3355typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP { 3356 DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP= 0x0, 3357 DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP= 0x1, 3358} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP; 3359typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN { 3360 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS= 0x0, 3361 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS= 0x1, 3362 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS= 0x2, 3363 DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS= 0x3, 3364} DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN; 3365typedef enum DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN { 3366 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US = 0x0, 3367 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US = 0x1, 3368 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US = 0x2, 3369 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US = 0x3, 3370 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US = 0x4, 3371 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US = 0x5, 3372 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US = 0x6, 3373 DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US = 0x7, 3374} DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN; 3375typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD { 3376 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0x0, 3377 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 0x1, 3378 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 0x2, 3379 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 0x3, 3380 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 0x4, 3381 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 0x5, 3382 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 0x6, 3383 DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 0x7, 3384} DP_AUX_DPHY_RX_DETECTION_THRESHOLD; 3385typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ { 3386 DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX= 0x0, 3387 DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX= 0x1, 3388} DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ; 3389typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW { 3390 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US= 0x0, 3391 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US= 0x1, 3392 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US= 0x2, 3393 DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US= 0x3, 3394} DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW; 3395typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT { 3396 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS= 0x0, 3397 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS= 0x1, 3398 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS= 0x2, 3399 DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED= 0x3, 3400} DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT; 3401typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN { 3402 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0= 0x0, 3403 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64= 0x1, 3404 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128= 0x2, 3405 DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256= 0x3, 3406} DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN; 3407typedef enum DP_AUX_ERR_OCCURRED_ACK { 3408 DP_AUX_ERR_OCCURRED__NOT_ACK = 0x0, 3409 DP_AUX_ERR_OCCURRED__ACK = 0x1, 3410} DP_AUX_ERR_OCCURRED_ACK; 3411typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK { 3412 DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0x0, 3413 DP_AUX_POTENTIAL_ERR_REACHED__ACK = 0x1, 3414} DP_AUX_POTENTIAL_ERR_REACHED_ACK; 3415typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK { 3416 ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0x0, 3417 ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 0x1, 3418} DP_AUX_DEFINITE_ERR_REACHED_ACK; 3419typedef enum DP_AUX_RESET { 3420 DP_AUX_RESET_DEASSERTED = 0x0, 3421 DP_AUX_RESET_ASSERTED = 0x1, 3422} DP_AUX_RESET; 3423typedef enum DP_AUX_RESET_DONE { 3424 DP_AUX_RESET_SEQUENCE_NOT_DONE = 0x0, 3425 DP_AUX_RESET_SEQUENCE_DONE = 0x1, 3426} DP_AUX_RESET_DONE; 3427typedef enum FBC_IDLE_MASK_MASK_BITS { 3428 FBC_IDLE_MASK_DISP_REG_UPDATE = 0x0, 3429 FBC_IDLE_MASK_RESERVED1 = 0x1, 3430 FBC_IDLE_MASK_FBC_GRPH_COMP_EN = 0x2, 3431 FBC_IDLE_MASK_FBC_MIN_COMPRESSION = 0x3, 3432 FBC_IDLE_MASK_FBC_ALPHA_COMP_EN = 0x4, 3433 FBC_IDLE_MASK_FBC_ZERO_ALPHA_CHUNK_SKIP_EN = 0x5, 3434 FBC_IDLE_MASK_FBC_FORCE_COPY_TO_COMP_BUF = 0x6, 3435 FBC_IDLE_MASK_RESERVED7 = 0x7, 3436 FBC_IDLE_MASK_RESERVED8 = 0x8, 3437 FBC_IDLE_MASK_RESERVED9 = 0x9, 3438 FBC_IDLE_MASK_RESERVED10 = 0xa, 3439 FBC_IDLE_MASK_RESERVED11 = 0xb, 3440 FBC_IDLE_MASK_RESERVED12 = 0xc, 3441 FBC_IDLE_MASK_RESERVED13 = 0xd, 3442 FBC_IDLE_MASK_RESERVED14 = 0xe, 3443 FBC_IDLE_MASK_RESERVED15 = 0xf, 3444 FBC_IDLE_MASK_RESERVED16 = 0x10, 3445 FBC_IDLE_MASK_RESERVED17 = 0x11, 3446 FBC_IDLE_MASK_RESERVED18 = 0x12, 3447 FBC_IDLE_MASK_RESERVED19 = 0x13, 3448 FBC_IDLE_MASK_RESERVED20 = 0x14, 3449 FBC_IDLE_MASK_RESERVED21 = 0x15, 3450 FBC_IDLE_MASK_RESERVED22 = 0x16, 3451 FBC_IDLE_MASK_RESERVED23 = 0x17, 3452 FBC_IDLE_MASK_MC_HIT_REGION_0 = 0x18, 3453 FBC_IDLE_MASK_MC_HIT_REGION_1 = 0x19, 3454 FBC_IDLE_MASK_MC_HIT_REGION_2 = 0x1a, 3455 FBC_IDLE_MASK_MC_HIT_REGION_3 = 0x1b, 3456 FBC_IDLE_MASK_MC_WRITE = 0x1c, 3457 FBC_IDLE_MASK_CG_STATIC_SCREEN = 0x1d, 3458 FBC_IDLE_MASK_RESERVED30 = 0x1e, 3459 FBC_IDLE_MASK_RESERVED31 = 0x1f, 3460} FBC_IDLE_MASK_MASK_BITS; 3461typedef enum FMT_CONTROL_PIXEL_ENCODING { 3462 FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0x0, 3463 FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 0x1, 3464 FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 0x2, 3465 FMT_CONTROL_PIXEL_ENCODING_RESERVED = 0x3, 3466} FMT_CONTROL_PIXEL_ENCODING; 3467typedef enum FMT_CONTROL_SUBSAMPLING_MODE { 3468 FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0x0, 3469 FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 0x1, 3470 FMT_CONTROL_SUBSAMPLING_MODE_3_TAP = 0x2, 3471 FMT_CONTROL_SUBSAMPLING_MODE_RESERVED = 0x3, 3472} FMT_CONTROL_SUBSAMPLING_MODE; 3473typedef enum FMT_CONTROL_SUBSAMPLING_ORDER { 3474 FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0x0, 3475 FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 0x1, 3476} FMT_CONTROL_SUBSAMPLING_ORDER; 3477typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS { 3478 FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0x0, 3479 FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 0x1, 3480} FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS; 3481typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE { 3482 FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0x0, 3483 FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 0x1, 3484} FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE; 3485typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH { 3486 FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0x0, 3487 FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 0x1, 3488 FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 0x2, 3489} FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH; 3490typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH { 3491 FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0x0, 3492 FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 0x1, 3493 FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x2, 3494} FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH; 3495typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH { 3496 FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP= 0x0, 3497 FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP= 0x1, 3498 FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP= 0x2, 3499} FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH; 3500typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL { 3501 FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0x0, 3502 FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 0x1, 3503} FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL; 3504typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL { 3505 FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0x0, 3506 FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 0x1, 3507 FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 0x2, 3508 FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 0x3, 3509} FMT_BIT_DEPTH_CONTROL_25FRC_SEL; 3510typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL { 3511 FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0x0, 3512 FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 0x1, 3513 FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 0x2, 3514 FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 0x3, 3515} FMT_BIT_DEPTH_CONTROL_50FRC_SEL; 3516typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL { 3517 FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0x0, 3518 FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 0x1, 3519 FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 0x2, 3520 FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 0x3, 3521} FMT_BIT_DEPTH_CONTROL_75FRC_SEL; 3522typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT { 3523 FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN= 0x0, 3524 FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN= 0x1, 3525} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT; 3526typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 { 3527 FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR= 0x0, 3528 FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB= 0x1, 3529} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0; 3530typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT { 3531 FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0x0, 3532 FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 0x1, 3533 FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 0x2, 3534 FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 0x3, 3535 FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 0x4, 3536 FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 0x5, 3537 FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 0x6, 3538 FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 0x7, 3539} FMT_CLAMP_CNTL_COLOR_FORMAT; 3540typedef enum FMT_CRC_CNTL_CONT_EN { 3541 FMT_CRC_CNTL_CONT_EN_ONE_SHOT = 0x0, 3542 FMT_CRC_CNTL_CONT_EN_CONT = 0x1, 3543} FMT_CRC_CNTL_CONT_EN; 3544typedef enum FMT_CRC_CNTL_INCLUDE_OVERSCAN { 3545 FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE = 0x0, 3546 FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE = 0x1, 3547} FMT_CRC_CNTL_INCLUDE_OVERSCAN; 3548typedef enum FMT_CRC_CNTL_ONLY_BLANKB { 3549 FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD = 0x0, 3550 FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK = 0x1, 3551} FMT_CRC_CNTL_ONLY_BLANKB; 3552typedef enum FMT_CRC_CNTL_PSR_MODE_ENABLE { 3553 FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL = 0x0, 3554 FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC = 0x1, 3555} FMT_CRC_CNTL_PSR_MODE_ENABLE; 3556typedef enum FMT_CRC_CNTL_INTERLACE_MODE { 3557 FMT_CRC_CNTL_INTERLACE_MODE_TOP = 0x0, 3558 FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM = 0x1, 3559 FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM = 0x2, 3560 FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH = 0x3, 3561} FMT_CRC_CNTL_INTERLACE_MODE; 3562typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE { 3563 FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL = 0x0, 3564 FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN = 0x1, 3565} FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE; 3566typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT { 3567 FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN = 0x0, 3568 FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD = 0x1, 3569} FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT; 3570typedef enum FMT_DEBUG_CNTL_COLOR_SELECT { 3571 FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0x0, 3572 FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 0x1, 3573 FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 0x2, 3574 FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 0x3, 3575} FMT_DEBUG_CNTL_COLOR_SELECT; 3576typedef enum FMT_SPATIAL_DITHER_MODE { 3577 FMT_SPATIAL_DITHER_MODE_0 = 0x0, 3578 FMT_SPATIAL_DITHER_MODE_1 = 0x1, 3579 FMT_SPATIAL_DITHER_MODE_2 = 0x2, 3580 FMT_SPATIAL_DITHER_MODE_3 = 0x3, 3581} FMT_SPATIAL_DITHER_MODE; 3582typedef enum FMT_STEREOSYNC_OVR_POL { 3583 FMT_STEREOSYNC_OVR_POL_INVERTED = 0x0, 3584 FMT_STEREOSYNC_OVR_POL_NOT_INVERTED = 0x1, 3585} FMT_STEREOSYNC_OVR_POL; 3586typedef enum FMT_DYNAMIC_EXP_MODE { 3587 FMT_DYNAMIC_EXP_MODE_10to12 = 0x0, 3588 FMT_DYNAMIC_EXP_MODE_8to12 = 0x1, 3589} FMT_DYNAMIC_EXP_MODE; 3590typedef enum LB_DATA_FORMAT_PIXEL_DEPTH { 3591 LB_DATA_FORMAT_PIXEL_DEPTH_30BPP = 0x0, 3592 LB_DATA_FORMAT_PIXEL_DEPTH_24BPP = 0x1, 3593 LB_DATA_FORMAT_PIXEL_DEPTH_18BPP = 0x2, 3594 LB_DATA_FORMAT_PIXEL_DEPTH_36BPP = 0x3, 3595} LB_DATA_FORMAT_PIXEL_DEPTH; 3596typedef enum LB_DATA_FORMAT_PIXEL_EXPAN_MODE { 3597 LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION= 0x0, 3598 LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION= 0x1, 3599} LB_DATA_FORMAT_PIXEL_EXPAN_MODE; 3600typedef enum LB_DATA_FORMAT_PIXEL_REDUCE_MODE { 3601 LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION = 0x0, 3602 LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING = 0x1, 3603} LB_DATA_FORMAT_PIXEL_REDUCE_MODE; 3604typedef enum LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH { 3605 LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP = 0x0, 3606 LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP = 0x1, 3607} LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH; 3608typedef enum LB_DATA_FORMAT_INTERLEAVE_EN { 3609 LB_DATA_FORMAT_INTERLEAVE_DISABLE = 0x0, 3610 LB_DATA_FORMAT_INTERLEAVE_ENABLE = 0x1, 3611} LB_DATA_FORMAT_INTERLEAVE_EN; 3612typedef enum LB_DATA_FORMAT_PREFILL_EN { 3613 LB_DATA_FORMAT_PREFILL_DISABLE = 0x0, 3614 LB_DATA_FORMAT_PREFILL_ENABLE = 0x1, 3615} LB_DATA_FORMAT_PREFILL_EN; 3616typedef enum LB_DATA_FORMAT_REQUEST_MODE { 3617 LB_DATA_FORMAT_REQUEST_MODE_NORMAL = 0x0, 3618 LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE = 0x1, 3619} LB_DATA_FORMAT_REQUEST_MODE; 3620typedef enum LB_DATA_FORMAT_ALPHA_EN { 3621 LB_DATA_FORMAT_ALPHA_DISABLE = 0x0, 3622 LB_DATA_FORMAT_ALPHA_ENABLE = 0x1, 3623} LB_DATA_FORMAT_ALPHA_EN; 3624typedef enum LB_VLINE_START_END_VLINE_INV { 3625 LB_VLINE_START_END_VLINE_NORMAL = 0x0, 3626 LB_VLINE_START_END_VLINE_INVERSE = 0x1, 3627} LB_VLINE_START_END_VLINE_INV; 3628typedef enum LB_VLINE2_START_END_VLINE2_INV { 3629 LB_VLINE2_START_END_VLINE2_NORMAL = 0x0, 3630 LB_VLINE2_START_END_VLINE2_INVERSE = 0x1, 3631} LB_VLINE2_START_END_VLINE2_INV; 3632typedef enum LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK { 3633 LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE = 0x0, 3634 LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE = 0x1, 3635} LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK; 3636typedef enum LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK { 3637 LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE = 0x0, 3638 LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE = 0x1, 3639} LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK; 3640typedef enum LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK { 3641 LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE = 0x0, 3642 LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE = 0x1, 3643} LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK; 3644typedef enum LB_VLINE_STATUS_VLINE_ACK { 3645 LB_VLINE_STATUS_VLINE_NORMAL = 0x0, 3646 LB_VLINE_STATUS_VLINE_CLEAR = 0x1, 3647} LB_VLINE_STATUS_VLINE_ACK; 3648typedef enum LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE { 3649 LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED = 0x0, 3650 LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED = 0x1, 3651} LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE; 3652typedef enum LB_VLINE2_STATUS_VLINE2_ACK { 3653 LB_VLINE2_STATUS_VLINE2_NORMAL = 0x0, 3654 LB_VLINE2_STATUS_VLINE2_CLEAR = 0x1, 3655} LB_VLINE2_STATUS_VLINE2_ACK; 3656typedef enum LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE { 3657 LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED= 0x0, 3658 LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED= 0x1, 3659} LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE; 3660typedef enum LB_VBLANK_STATUS_VBLANK_ACK { 3661 LB_VBLANK_STATUS_VBLANK_NORMAL = 0x0, 3662 LB_VBLANK_STATUS_VBLANK_CLEAR = 0x1, 3663} LB_VBLANK_STATUS_VBLANK_ACK; 3664typedef enum LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE { 3665 LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED= 0x0, 3666 LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED= 0x1, 3667} LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE; 3668typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL { 3669 LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE = 0x0, 3670 LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK= 0x1, 3671 LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET= 0x2, 3672 LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET= 0x3, 3673} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL; 3674typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 { 3675 LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK = 0x0, 3676 LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC = 0x1, 3677} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2; 3678typedef enum LB_SYNC_RESET_SEL_LB_SYNC_DURATION { 3679 LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS = 0x0, 3680 LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS = 0x1, 3681 LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS = 0x2, 3682 LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS = 0x3, 3683} LB_SYNC_RESET_SEL_LB_SYNC_DURATION; 3684typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN { 3685 LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE = 0x0, 3686 LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE = 0x1, 3687} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN; 3688typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN { 3689 LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE= 0x0, 3690 LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE= 0x1, 3691} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN; 3692typedef enum LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK { 3693 LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL = 0x0, 3694 LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET = 0x1, 3695} LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK; 3696typedef enum LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK { 3697 LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL = 0x0, 3698 LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET = 0x1, 3699} LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK; 3700typedef enum LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE { 3701 LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP = 0x2, 3702 LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP= 0x3, 3703} LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE; 3704typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET { 3705 LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL= 0x0, 3706 LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE= 0x1, 3707} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET; 3708typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK { 3709 LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0= 0x0, 3710 LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1= 0x1, 3711} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK; 3712typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE { 3713 LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT= 0x0, 3714 LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG= 0x1, 3715 LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE= 0x2, 3716} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE; 3717typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE { 3718 LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE= 0x0, 3719 LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN = 0x1, 3720} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE; 3721typedef enum LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE { 3722 ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER= 0x1, 3723 ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE= 0x2, 3724} LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE; 3725typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL { 3726 LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0= 0x0, 3727 LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1= 0x1, 3728} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL; 3729typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE { 3730 LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE= 0x0, 3731 LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE= 0x1, 3732} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE; 3733typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO { 3734 LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO= 0x0, 3735 LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO= 0x1, 3736} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO; 3737typedef enum LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN { 3738 LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0= 0x0, 3739 LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1= 0x1, 3740} LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN; 3741typedef enum LBV_PIXEL_DEPTH { 3742 PIXEL_DEPTH_30BPP = 0x0, 3743 PIXEL_DEPTH_24BPP = 0x1, 3744 PIXEL_DEPTH_18BPP = 0x2, 3745 PIXEL_DEPTH_38BPP = 0x3, 3746} LBV_PIXEL_DEPTH; 3747typedef enum LBV_PIXEL_EXPAN_MODE { 3748 PIXEL_EXPAN_MODE_ZERO_EXP = 0x0, 3749 PIXEL_EXPAN_MODE_DYN_EXP = 0x1, 3750} LBV_PIXEL_EXPAN_MODE; 3751typedef enum LBV_INTERLEAVE_EN { 3752 INTERLEAVE_DIS = 0x0, 3753 INTERLEAVE_EN = 0x1, 3754} LBV_INTERLEAVE_EN; 3755typedef enum LBV_PIXEL_REDUCE_MODE { 3756 PIXEL_REDUCE_MODE_TRUNCATION = 0x0, 3757 PIXEL_REDUCE_MODE_ROUNDING = 0x1, 3758} LBV_PIXEL_REDUCE_MODE; 3759typedef enum LBV_DYNAMIC_PIXEL_DEPTH { 3760 DYNAMIC_PIXEL_DEPTH_36BPP = 0x0, 3761 DYNAMIC_PIXEL_DEPTH_30BPP = 0x1, 3762} LBV_DYNAMIC_PIXEL_DEPTH; 3763typedef enum LBV_DITHER_EN { 3764 DITHER_DIS = 0x0, 3765 DITHER_EN = 0x1, 3766} LBV_DITHER_EN; 3767typedef enum LBV_DOWNSCALE_PREFETCH_EN { 3768 DOWNSCALE_PREFETCH_DIS = 0x0, 3769 DOWNSCALE_PREFETCH_EN = 0x1, 3770} LBV_DOWNSCALE_PREFETCH_EN; 3771typedef enum LBV_MEMORY_CONFIG { 3772 MEMORY_CONFIG_0 = 0x0, 3773 MEMORY_CONFIG_1 = 0x1, 3774 MEMORY_CONFIG_2 = 0x2, 3775 MEMORY_CONFIG_3 = 0x3, 3776} LBV_MEMORY_CONFIG; 3777typedef enum LBV_SYNC_RESET_SEL2 { 3778 SYNC_RESET_SEL2_VBLANK = 0x0, 3779 SYNC_RESET_SEL2_VSYNC = 0x1, 3780} LBV_SYNC_RESET_SEL2; 3781typedef enum LBV_SYNC_DURATION { 3782 SYNC_DURATION_16 = 0x0, 3783 SYNC_DURATION_32 = 0x1, 3784 SYNC_DURATION_64 = 0x2, 3785 SYNC_DURATION_128 = 0x3, 3786} LBV_SYNC_DURATION; 3787typedef enum SCL_C_RAM_TAP_PAIR_IDX { 3788 SCL_C_RAM_TAP_PAIR_ID0 = 0x0, 3789 SCL_C_RAM_TAP_PAIR_ID1 = 0x1, 3790 SCL_C_RAM_TAP_PAIR_ID2 = 0x2, 3791 SCL_C_RAM_TAP_PAIR_ID3 = 0x3, 3792 SCL_C_RAM_TAP_PAIR_ID4 = 0x4, 3793} SCL_C_RAM_TAP_PAIR_IDX; 3794typedef enum SCL_C_RAM_PHASE { 3795 SCL_C_RAM_PHASE_0 = 0x0, 3796 SCL_C_RAM_PHASE_1 = 0x1, 3797 SCL_C_RAM_PHASE_2 = 0x2, 3798 SCL_C_RAM_PHASE_3 = 0x3, 3799 SCL_C_RAM_PHASE_4 = 0x4, 3800 SCL_C_RAM_PHASE_5 = 0x5, 3801 SCL_C_RAM_PHASE_6 = 0x6, 3802 SCL_C_RAM_PHASE_7 = 0x7, 3803 SCL_C_RAM_PHASE_8 = 0x8, 3804} SCL_C_RAM_PHASE; 3805typedef enum SCL_C_RAM_FILTER_TYPE { 3806 SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT = 0x0, 3807 SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT = 0x1, 3808 SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT = 0x2, 3809 SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT = 0x3, 3810} SCL_C_RAM_FILTER_TYPE; 3811typedef enum SCL_MODE_SEL { 3812 SCL_MODE_RGB_BYPASS = 0x0, 3813 SCL_MODE_RGB_SCALING = 0x1, 3814 SCL_MODE_YCBCR_SCALING = 0x2, 3815 SCL_MODE_YCBCR_BYPASS = 0x3, 3816} SCL_MODE_SEL; 3817typedef enum SCL_PSCL_EN { 3818 SCL_PSCL_DISABLE = 0x0, 3819 SCL_PSCL_ENANBLE = 0x1, 3820} SCL_PSCL_EN; 3821typedef enum SCL_V_NUM_OF_TAPS { 3822 SCL_V_NUM_OF_TAPS_1 = 0x0, 3823 SCL_V_NUM_OF_TAPS_2 = 0x1, 3824 SCL_V_NUM_OF_TAPS_3 = 0x2, 3825 SCL_V_NUM_OF_TAPS_4 = 0x3, 3826 SCL_V_NUM_OF_TAPS_5 = 0x4, 3827 SCL_V_NUM_OF_TAPS_6 = 0x5, 3828} SCL_V_NUM_OF_TAPS; 3829typedef enum SCL_H_NUM_OF_TAPS { 3830 SCL_H_NUM_OF_TAPS_1 = 0x0, 3831 SCL_H_NUM_OF_TAPS_2 = 0x1, 3832 SCL_H_NUM_OF_TAPS_4 = 0x3, 3833 SCL_H_NUM_OF_TAPS_6 = 0x5, 3834 SCL_H_NUM_OF_TAPS_8 = 0x7, 3835 SCL_H_NUM_OF_TAPS_10 = 0x9, 3836} SCL_H_NUM_OF_TAPS; 3837typedef enum SCL_BOUNDARY_MODE { 3838 SCL_BOUNDARY_MODE_BLACK = 0x0, 3839 SCL_BOUNDARY_MODE_EDGE = 0x1, 3840} SCL_BOUNDARY_MODE; 3841typedef enum SCL_EARLY_EOL_MOD { 3842 SCL_EARLY_EOL_MODE_CRTC = 0x0, 3843 SCL_EARLY_EOL_MODE_INTERNAL = 0x1, 3844} SCL_EARLY_EOL_MOD; 3845typedef enum SCL_BYPASS_MODE { 3846 SCL_BYPASS_MODE_MC_MR = 0x0, 3847 SCL_BYPASS_MODE_AC_NR = 0x1, 3848 SCL_BYPASS_MODE_AC_AR = 0x2, 3849 SCL_BYPASS_MODE_RESERVED = 0x3, 3850} SCL_BYPASS_MODE; 3851typedef enum SCL_V_MANUAL_REPLICATE_FACTOR { 3852 SCL_V_MANUAL_REPLICATE_FACTOR_1 = 0x0, 3853 SCL_V_MANUAL_REPLICATE_FACTOR_2 = 0x1, 3854 SCL_V_MANUAL_REPLICATE_FACTOR_3 = 0x2, 3855 SCL_V_MANUAL_REPLICATE_FACTOR_4 = 0x3, 3856 SCL_V_MANUAL_REPLICATE_FACTOR_5 = 0x4, 3857 SCL_V_MANUAL_REPLICATE_FACTOR_6 = 0x5, 3858 SCL_V_MANUAL_REPLICATE_FACTOR_7 = 0x6, 3859 SCL_V_MANUAL_REPLICATE_FACTOR_8 = 0x7, 3860 SCL_V_MANUAL_REPLICATE_FACTOR_9 = 0x8, 3861 SCL_V_MANUAL_REPLICATE_FACTOR_10 = 0x9, 3862 SCL_V_MANUAL_REPLICATE_FACTOR_11 = 0xa, 3863 SCL_V_MANUAL_REPLICATE_FACTOR_12 = 0xb, 3864 SCL_V_MANUAL_REPLICATE_FACTOR_13 = 0xc, 3865 SCL_V_MANUAL_REPLICATE_FACTOR_14 = 0xd, 3866 SCL_V_MANUAL_REPLICATE_FACTOR_15 = 0xe, 3867 SCL_V_MANUAL_REPLICATE_FACTOR_16 = 0xf, 3868} SCL_V_MANUAL_REPLICATE_FACTOR; 3869typedef enum SCL_H_MANUAL_REPLICATE_FACTOR { 3870 SCL_H_MANUAL_REPLICATE_FACTOR_1 = 0x0, 3871 SCL_H_MANUAL_REPLICATE_FACTOR_2 = 0x1, 3872 SCL_H_MANUAL_REPLICATE_FACTOR_3 = 0x2, 3873 SCL_H_MANUAL_REPLICATE_FACTOR_4 = 0x3, 3874 SCL_H_MANUAL_REPLICATE_FACTOR_5 = 0x4, 3875 SCL_H_MANUAL_REPLICATE_FACTOR_6 = 0x5, 3876 SCL_H_MANUAL_REPLICATE_FACTOR_7 = 0x6, 3877 SCL_H_MANUAL_REPLICATE_FACTOR_8 = 0x7, 3878 SCL_H_MANUAL_REPLICATE_FACTOR_9 = 0x8, 3879 SCL_H_MANUAL_REPLICATE_FACTOR_10 = 0x9, 3880 SCL_H_MANUAL_REPLICATE_FACTOR_11 = 0xa, 3881 SCL_H_MANUAL_REPLICATE_FACTOR_12 = 0xb, 3882 SCL_H_MANUAL_REPLICATE_FACTOR_13 = 0xc, 3883 SCL_H_MANUAL_REPLICATE_FACTOR_14 = 0xd, 3884 SCL_H_MANUAL_REPLICATE_FACTOR_15 = 0xe, 3885 SCL_H_MANUAL_REPLICATE_FACTOR_16 = 0xf, 3886} SCL_H_MANUAL_REPLICATE_FACTOR; 3887typedef enum SCL_V_CALC_AUTO_RATIO_EN { 3888 SCL_V_CALC_AUTO_RATIO_DISABLE = 0x0, 3889 SCL_V_CALC_AUTO_RATIO_ENABLE = 0x1, 3890} SCL_V_CALC_AUTO_RATIO_EN; 3891typedef enum SCL_H_CALC_AUTO_RATIO_EN { 3892 SCL_H_CALC_AUTO_RATIO_DISABLE = 0x0, 3893 SCL_H_CALC_AUTO_RATIO_ENABLE = 0x1, 3894} SCL_H_CALC_AUTO_RATIO_EN; 3895typedef enum SCL_H_FILTER_PICK_NEAREST { 3896 SCL_H_FILTER_PICK_NEAREST_DISABLE = 0x0, 3897 SCL_H_FILTER_PICK_NEAREST_ENABLE = 0x1, 3898} SCL_H_FILTER_PICK_NEAREST; 3899typedef enum SCL_H_2TAP_HARDCODE_COEF_EN { 3900 SCL_H_2TAP_HARDCODE_COEF_DISABLE = 0x0, 3901 SCL_H_2TAP_HARDCODE_COEF_ENABLE = 0x1, 3902} SCL_H_2TAP_HARDCODE_COEF_EN; 3903typedef enum SCL_V_FILTER_PICK_NEAREST { 3904 SCL_V_FILTER_PICK_NEAREST_DISABLE = 0x0, 3905 SCL_V_FILTER_PICK_NEAREST_ENABLE = 0x1, 3906} SCL_V_FILTER_PICK_NEAREST; 3907typedef enum SCL_V_2TAP_HARDCODE_COEF_EN { 3908 SCL_V_2TAP_HARDCODE_COEF_DISABLE = 0x0, 3909 SCL_V_2TAP_HARDCODE_COEF_ENABLE = 0x1, 3910} SCL_V_2TAP_HARDCODE_COEF_EN; 3911typedef enum SCL_UPDATE_TAKEN { 3912 SCL_UPDATE_TAKEN_NO = 0x0, 3913 SCL_UPDATE_TAKEN_YES = 0x1, 3914} SCL_UPDATE_TAKEN; 3915typedef enum SCL_UPDATE_LOCK { 3916 SCL_UPDATE_UNLOCKED = 0x0, 3917 SCL_UPDATE_LOCKED = 0x1, 3918} SCL_UPDATE_LOCK; 3919typedef enum SCL_COEF_UPDATE_COMPLETE { 3920 SCL_COEF_UPDATE_NOT_COMPLETED = 0x0, 3921 SCL_COEF_UPDATE_COMPLETED = 0x1, 3922} SCL_COEF_UPDATE_COMPLETE; 3923typedef enum SCL_HF_SHARP_SCALE_FACTOR { 3924 SCL_HF_SHARP_SCALE_FACTOR_0 = 0x0, 3925 SCL_HF_SHARP_SCALE_FACTOR_1 = 0x1, 3926 SCL_HF_SHARP_SCALE_FACTOR_2 = 0x2, 3927 SCL_HF_SHARP_SCALE_FACTOR_3 = 0x3, 3928 SCL_HF_SHARP_SCALE_FACTOR_4 = 0x4, 3929 SCL_HF_SHARP_SCALE_FACTOR_5 = 0x5, 3930 SCL_HF_SHARP_SCALE_FACTOR_6 = 0x6, 3931 SCL_HF_SHARP_SCALE_FACTOR_7 = 0x7, 3932} SCL_HF_SHARP_SCALE_FACTOR; 3933typedef enum SCL_HF_SHARP_EN { 3934 SCL_HF_SHARP_DISABLE = 0x0, 3935 SCL_HF_SHARP_ENABLE = 0x1, 3936} SCL_HF_SHARP_EN; 3937typedef enum SCL_VF_SHARP_SCALE_FACTOR { 3938 SCL_VF_SHARP_SCALE_FACTOR_0 = 0x0, 3939 SCL_VF_SHARP_SCALE_FACTOR_1 = 0x1, 3940 SCL_VF_SHARP_SCALE_FACTOR_2 = 0x2, 3941 SCL_VF_SHARP_SCALE_FACTOR_3 = 0x3, 3942 SCL_VF_SHARP_SCALE_FACTOR_4 = 0x4, 3943 SCL_VF_SHARP_SCALE_FACTOR_5 = 0x5, 3944 SCL_VF_SHARP_SCALE_FACTOR_6 = 0x6, 3945 SCL_VF_SHARP_SCALE_FACTOR_7 = 0x7, 3946} SCL_VF_SHARP_SCALE_FACTOR; 3947typedef enum SCL_VF_SHARP_EN { 3948 SCL_VF_SHARP_DISABLE = 0x0, 3949 SCL_VF_SHARP_ENABLE = 0x1, 3950} SCL_VF_SHARP_EN; 3951typedef enum SCL_ALU_DISABLE { 3952 SCL_ALU_ENABLED = 0x0, 3953 SCL_ALU_DISABLED = 0x1, 3954} SCL_ALU_DISABLE; 3955typedef enum SCL_HOST_CONFLICT_MASK { 3956 SCL_HOST_CONFLICT_DISABLE_INTERRUPT = 0x0, 3957 SCL_HOST_CONFLICT_ENABLE_INTERRUPT = 0x1, 3958} SCL_HOST_CONFLICT_MASK; 3959typedef enum SCL_SCL_MODE_CHANGE_MASK { 3960 SCL_MODE_CHANGE_DISABLE_INTERRUPT = 0x0, 3961 SCL_MODE_CHANGE_ENABLE_INTERRUPT = 0x1, 3962} SCL_SCL_MODE_CHANGE_MASK; 3963typedef enum SCLV_MODE_SEL { 3964 SCLV_MODE_RGB_BYPASS = 0x0, 3965 SCLV_MODE_RGB_SCALING = 0x1, 3966 SCLV_MODE_YCBCR_SCALING = 0x2, 3967 SCLV_MODE_YCBCR_BYPASS = 0x3, 3968} SCLV_MODE_SEL; 3969typedef enum SCLV_INTERLACE_SOURCE { 3970 INTERLACE_SOURCE_PROGRESSIVE = 0x0, 3971 INTERLACE_SOURCE_INTERLEAVE = 0x1, 3972 INTERLACE_SOURCE_STACK = 0x2, 3973} SCLV_INTERLACE_SOURCE; 3974typedef enum SCLV_UPDATE_LOCK { 3975 UPDATE_UNLOCKED = 0x0, 3976 UPDATE_LOCKED = 0x1, 3977} SCLV_UPDATE_LOCK; 3978typedef enum SCLV_COEF_UPDATE_COMPLETE { 3979 COEF_UPDATE_NOT_COMPLETE = 0x0, 3980 COEF_UPDATE_COMPLETE = 0x1, 3981} SCLV_COEF_UPDATE_COMPLETE; 3982typedef enum COL_MAN_UPDATE_LOCK { 3983 COL_MAN_UPDATE_UNLOCKED = 0x0, 3984 COL_MAN_UPDATE_LOCKED = 0x1, 3985} COL_MAN_UPDATE_LOCK; 3986typedef enum COL_MAN_DISABLE_MULTIPLE_UPDATE { 3987 COL_MAN_MULTIPLE_UPDATE = 0x0, 3988 COL_MAN_MULTIPLE_UPDAT_EDISABLE = 0x1, 3989} COL_MAN_DISABLE_MULTIPLE_UPDATE; 3990typedef enum COL_MAN_INPUTCSC_MODE { 3991 INPUTCSC_MODE_BYPASS = 0x0, 3992 INPUTCSC_MODE_A = 0x1, 3993 INPUTCSC_MODE_B = 0x2, 3994 INPUTCSC_MODE_UNITY = 0x3, 3995} COL_MAN_INPUTCSC_MODE; 3996typedef enum COL_MAN_INPUTCSC_TYPE { 3997 INPUTCSC_TYPE_12_0 = 0x0, 3998 INPUTCSC_TYPE_10_2 = 0x1, 3999 INPUTCSC_TYPE_8_4 = 0x2, 4000} COL_MAN_INPUTCSC_TYPE; 4001typedef enum COL_MAN_INPUTCSC_CONVERT { 4002 INPUTCSC_ROUND = 0x0, 4003 INPUTCSC_TRUNCATE = 0x1, 4004} COL_MAN_INPUTCSC_CONVERT; 4005typedef enum COL_MAN_PRESCALE_MODE { 4006 PRESCALE_MODE_BYPASS = 0x0, 4007 PRESCALE_MODE_PROGRAM = 0x1, 4008 PRESCALE_MODE_UNITY = 0x2, 4009} COL_MAN_PRESCALE_MODE; 4010typedef enum COL_MAN_INPUT_GAMMA_MODE { 4011 INGAMMA_MODE_BYPASS = 0x0, 4012 INGAMMA_MODE_FIX = 0x1, 4013 INGAMMA_MODE_FLOAT = 0x2, 4014} COL_MAN_INPUT_GAMMA_MODE; 4015typedef enum COL_MAN_OUTPUT_CSC_MODE { 4016 COL_MAN_OUTPUT_CSC_BYPASS = 0x0, 4017 COL_MAN_OUTPUT_CSC_RGB = 0x1, 4018 COL_MAN_OUTPUT_CSC_YCrCb601 = 0x2, 4019 COL_MAN_OUTPUT_CSC_YCrCb709 = 0x3, 4020 COL_MAN_OUTPUT_CSC_A = 0x4, 4021 COL_MAN_OUTPUT_CSC_B = 0x5, 4022 COL_MAN_OUTPUT_CSC_UNITY = 0x6, 4023} COL_MAN_OUTPUT_CSC_MODE; 4024typedef enum COL_MAN_DENORM_CLAMP_CONTROL { 4025 DENORM_CLAMP_MODE_UNITY = 0x0, 4026 DENORM_CLAMP_MODE_8 = 0x1, 4027 DENORM_CLAMP_MODE_10 = 0x2, 4028 DENORM_CLAMP_MODE_12 = 0x3, 4029} COL_MAN_DENORM_CLAMP_CONTROL; 4030typedef enum COL_MAN_GAMMA_CORR_CONTROL { 4031 GAMMA_CORR_MODE_BYPASS = 0x0, 4032 GAMMA_CORR_MODE_A = 0x1, 4033 GAMMA_CORR_MODE_B = 0x2, 4034} COL_MAN_GAMMA_CORR_CONTROL; 4035typedef enum COL_MAN_GLOBAL_PASSTHROUGH_ENABLE { 4036 CM_GLOBAL_PASSTHROUGH_DISBALE = 0x0, 4037 CM_GLOBAL_PASSTHROUGH_ENABLE = 0x1, 4038} COL_MAN_GLOBAL_PASSTHROUGH_ENABLE; 4039typedef enum UNP_GRPH_EN { 4040 UNP_GRPH_DISABLED = 0x0, 4041 UNP_GRPH_ENABLED = 0x1, 4042} UNP_GRPH_EN; 4043typedef enum UNP_GRPH_DEPTH { 4044 UNP_GRPH_8BPP = 0x0, 4045 UNP_GRPH_16BPP = 0x1, 4046 UNP_GRPH_32BPP = 0x2, 4047} UNP_GRPH_DEPTH; 4048typedef enum UNP_GRPH_NUM_BANKS { 4049 UNP_GRPH_ADDR_SURF_2_BANK = 0x0, 4050 UNP_GRPH_ADDR_SURF_4_BANK = 0x1, 4051 UNP_GRPH_ADDR_SURF_8_BANK = 0x2, 4052 UNP_GRPH_ADDR_SURF_16_BANK = 0x3, 4053} UNP_GRPH_NUM_BANKS; 4054typedef enum UNP_GRPH_BANK_WIDTH { 4055 UNP_GRPH_ADDR_SURF_BANK_WIDTH_1 = 0x0, 4056 UNP_GRPH_ADDR_SURF_BANK_WIDTH_2 = 0x1, 4057 UNP_GRPH_ADDR_SURF_BANK_WIDTH_4 = 0x2, 4058 UNP_GRPH_ADDR_SURF_BANK_WIDTH_8 = 0x3, 4059} UNP_GRPH_BANK_WIDTH; 4060typedef enum UNP_GRPH_BANK_HEIGHT { 4061 UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1 = 0x0, 4062 UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2 = 0x1, 4063 UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4 = 0x2, 4064 UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8 = 0x3, 4065} UNP_GRPH_BANK_HEIGHT; 4066typedef enum UNP_GRPH_TILE_SPLIT { 4067 UNP_ADDR_SURF_TILE_SPLIT_64B = 0x0, 4068 UNP_ADDR_SURF_TILE_SPLIT_128B = 0x1, 4069 UNP_ADDR_SURF_TILE_SPLIT_256B = 0x2, 4070 UNP_ADDR_SURF_TILE_SPLIT_512B = 0x3, 4071 UNP_ADDR_SURF_TILE_SPLIT_1KB = 0x4, 4072 UNP_ADDR_SURF_TILE_SPLIT_2KB = 0x5, 4073 UNP_ADDR_SURF_TILE_SPLIT_4KB = 0x6, 4074} UNP_GRPH_TILE_SPLIT; 4075typedef enum UNP_GRPH_ADDRESS_TRANSLATION_ENABLE { 4076 UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0 = 0x0, 4077 UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1 = 0x1, 4078} UNP_GRPH_ADDRESS_TRANSLATION_ENABLE; 4079typedef enum UNP_GRPH_PRIVILEGED_ACCESS_ENABLE { 4080 UNP_GRPH_PRIVILEGED_ACCESS_DIS = 0x0, 4081 UNP_GRPH_PRIVILEGED_ACCESS_EN = 0x1, 4082} UNP_GRPH_PRIVILEGED_ACCESS_ENABLE; 4083typedef enum UNP_GRPH_MACRO_TILE_ASPECT { 4084 UNP_ADDR_SURF_MACRO_ASPECT_1 = 0x0, 4085 UNP_ADDR_SURF_MACRO_ASPECT_2 = 0x1, 4086 UNP_ADDR_SURF_MACRO_ASPECT_4 = 0x2, 4087 UNP_ADDR_SURF_MACRO_ASPECT_8 = 0x3, 4088} UNP_GRPH_MACRO_TILE_ASPECT; 4089typedef enum UNP_GRPH_COLOR_EXPANSION_MODE { 4090 UNP_GRPH_DYNAMIC_EXPANSION = 0x0, 4091 UNP_GRPH_ZERO_EXPANSION = 0x1, 4092} UNP_GRPH_COLOR_EXPANSION_MODE; 4093typedef enum UNP_VIDEO_FORMAT { 4094 UNP_VIDEO_FORMAT0 = 0x0, 4095 UNP_VIDEO_FORMAT1 = 0x1, 4096 UNP_VIDEO_FORMAT_YUV420_YCbCr = 0x2, 4097 UNP_VIDEO_FORMAT_YUV420_YCrCb = 0x3, 4098 UNP_VIDEO_FORMAT_YUV422_YCb = 0x4, 4099 UNP_VIDEO_FORMAT_YUV422_YCr = 0x5, 4100 UNP_VIDEO_FORMAT_YUV422_CbY = 0x6, 4101 UNP_VIDEO_FORMAT_YUV422_CrY = 0x7, 4102} UNP_VIDEO_FORMAT; 4103typedef enum UNP_GRPH_ENDIAN_SWAP { 4104 UNP_GRPH_ENDIAN_SWAP_NONE = 0x0, 4105 UNP_GRPH_ENDIAN_SWAP_8IN16 = 0x1, 4106 UNP_GRPH_ENDIAN_SWAP_8IN32 = 0x2, 4107 UNP_GRPH_ENDIAN_SWAP_8IN43 = 0x3, 4108} UNP_GRPH_ENDIAN_SWAP; 4109typedef enum UNP_GRPH_RED_CROSSBAR { 4110 UNP_GRPH_RED_CROSSBAR_R_Cr = 0x0, 4111 UNP_GRPH_RED_CROSSBAR_G_Y = 0x1, 4112 UNP_GRPH_RED_CROSSBAR_B_Cb = 0x2, 4113 UNP_GRPH_RED_CROSSBAR_A = 0x3, 4114} UNP_GRPH_RED_CROSSBAR; 4115typedef enum UNP_GRPH_GREEN_CROSSBAR { 4116 UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y = 0x0, 4117 UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C = 0x1, 4118 UNP_UNP_GRPH_GREEN_CROSSBAR_A = 0x2, 4119 UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr = 0x3, 4120} UNP_GRPH_GREEN_CROSSBAR; 4121typedef enum UNP_GRPH_BLUE_CROSSBAR { 4122 UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C = 0x0, 4123 UNP_GRPH_BLUE_CROSSBAR_A = 0x1, 4124 UNP_GRPH_BLUE_CROSSBAR_R_Cr = 0x2, 4125 UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y = 0x3, 4126} UNP_GRPH_BLUE_CROSSBAR; 4127typedef enum UNP_GRPH_MODE_UPDATE_LOCKG { 4128 UNP_GRPH_UPDATE_LOCK_0 = 0x0, 4129 UNP_GRPH_UPDATE_LOCK_1 = 0x1, 4130} UNP_GRPH_MODE_UPDATE_LOCKG; 4131typedef enum UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK { 4132 UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0 = 0x0, 4133 UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1 = 0x1, 4134} UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK; 4135typedef enum UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE { 4136 UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0 = 0x0, 4137 UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1 = 0x1, 4138} UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE; 4139typedef enum UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE { 4140 UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0 = 0x0, 4141 UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1 = 0x1, 4142} UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE; 4143typedef enum UNP_GRPH_STEREOSYNC_FLIP_EN { 4144 UNP_GRPH_STEREOSYNC_FLIP_DISABLE = 0x0, 4145 UNP_GRPH_STEREOSYNC_FLIP_ENABLE = 0x1, 4146} UNP_GRPH_STEREOSYNC_FLIP_EN; 4147typedef enum UNP_GRPH_STEREOSYNC_FLIP_MODE { 4148 UNP_GRPH_STEREOSYNC_FLIP_MODE_0 = 0x0, 4149 UNP_GRPH_STEREOSYNC_FLIP_MODE_1 = 0x1, 4150 UNP_GRPH_STEREOSYNC_FLIP_MODE_2 = 0x2, 4151 UNP_GRPH_STEREOSYNC_FLIP_MODE_3 = 0x3, 4152} UNP_GRPH_STEREOSYNC_FLIP_MODE; 4153typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_EN { 4154 UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE = 0x0, 4155 UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE = 0x1, 4156} UNP_GRPH_STACK_INTERLACE_FLIP_EN; 4157typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_MODE { 4158 UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0 = 0x0, 4159 UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1 = 0x1, 4160 UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2 = 0x2, 4161 UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3 = 0x3, 4162} UNP_GRPH_STACK_INTERLACE_FLIP_MODE; 4163typedef enum UNP_GRPH_STEREOSYNC_SELECT_DISABLE { 4164 UNP_GRPH_STEREOSYNC_SELECT_EN = 0x0, 4165 UNP_GRPH_STEREOSYNC_SELECT_DIS = 0x1, 4166} UNP_GRPH_STEREOSYNC_SELECT_DISABLE; 4167typedef enum UNP_CRC_SOURCE_SEL { 4168 UNP_CRC_SOURCE_SEL_NP_TO_LBV = 0x0, 4169 UNP_CRC_SOURCE_SEL_LOWER32 = 0x1, 4170 UNP_CRC_SOURCE_SEL_RESERVED = 0x2, 4171 UNP_CRC_SOURCE_SEL_LOWER16 = 0x3, 4172 UNP_CRC_SOURCE_SEL_UNP_TO_LBV = 0x4, 4173} UNP_CRC_SOURCE_SEL; 4174typedef enum UNP_CRC_LINE_SEL { 4175 UNP_CRC_LINE_SEL_RESERVED = 0x0, 4176 UNP_CRC_LINE_SEL_EVEN_ONLY = 0x1, 4177 UNP_CRC_LINE_SEL_ODD_ONLY = 0x2, 4178 UNP_CRC_LINE_SEL_ODD_EVEN = 0x3, 4179} UNP_CRC_LINE_SEL; 4180typedef enum UNP_ROTATION_ANGLE { 4181 UNP_ROTATION_ANGLE_0 = 0x0, 4182 UNP_ROTATION_ANGLE_90 = 0x1, 4183 UNP_ROTATION_ANGLE_180 = 0x2, 4184 UNP_ROTATION_ANGLE_270 = 0x3, 4185 UNP_ROTATION_ANGLE_0m = 0x4, 4186 UNP_ROTATION_ANGLE_90m = 0x5, 4187 UNP_ROTATION_ANGLE_180m = 0x6, 4188 UNP_ROTATION_ANGLE_270m = 0x7, 4189} UNP_ROTATION_ANGLE; 4190typedef enum UNP_PIXEL_DROP { 4191 UNP_PIXEL_NO_DROP = 0x0, 4192 UNP_PIXEL_DROPPING = 0x1, 4193} UNP_PIXEL_DROP; 4194typedef enum UNP_BUFFER_MODE { 4195 UNP_BUFFER_MODE_LUMA = 0x0, 4196 UNP_BUFFER_MODE_LUMA_CHROMA = 0x1, 4197} UNP_BUFFER_MODE; 4198typedef enum WATERMARK_MASK_CONTROL { 4199 WM_MASK_CONTROL_SET_A = 0x0, 4200 WM_MASK_CONTROL_SET_B = 0x1, 4201 WM_MASK_CONTROL_SET_C = 0x2, 4202 WM_MASK_CONTROL_SET_D = 0x3, 4203 WM_MASK_CONTROL_RESERVED1 = 0x4, 4204 WM_MASK_CONTROL_RESERVED2 = 0x5, 4205 WM_MASK_CONTROL_RESERVED3 = 0x6, 4206 WM_MASK_CONTROL_ACTIVE_SET = 0x7, 4207} WATERMARK_MASK_CONTROL; 4208typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET { 4209 AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET= 0x0, 4210 AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET= 0x1, 4211} AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET; 4212typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY { 4213 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL= 0x0, 4214 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6= 0x1, 4215 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5= 0x2, 4216 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4= 0x3, 4217 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3= 0x4, 4218 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2= 0x5, 4219 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1= 0x6, 4220 CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0= 0x7, 4221} CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY; 4222typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY { 4223 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL= 0x0, 4224 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6= 0x1, 4225 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5= 0x2, 4226 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4= 0x3, 4227 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3= 0x4, 4228 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2= 0x5, 4229 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1= 0x6, 4230 CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0= 0x7, 4231} CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY; 4232typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL { 4233 GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0x0, 4234 GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 0x1, 4235} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL; 4236typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED { 4237 GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0x0, 4238 GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 0x1, 4239} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED; 4240typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS { 4241 GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0x0, 4242 GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 0x1, 4243} GENERIC_AZ_CONTROLLER_REGISTER_STATUS; 4244typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED { 4245 GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED= 0x0, 4246 GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED= 0x1, 4247} GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED; 4248typedef enum AZ_GLOBAL_CAPABILITIES { 4249 AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED= 0x0, 4250 AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED= 0x1, 4251} AZ_GLOBAL_CAPABILITIES; 4252typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE { 4253 ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0x0, 4254 ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 0x1, 4255} GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE; 4256typedef enum GLOBAL_CONTROL_FLUSH_CONTROL { 4257 FLUSH_CONTROL_FLUSH_NOT_STARTED = 0x0, 4258 FLUSH_CONTROL_FLUSH_STARTED = 0x1, 4259} GLOBAL_CONTROL_FLUSH_CONTROL; 4260typedef enum GLOBAL_CONTROL_CONTROLLER_RESET { 4261 CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0x0, 4262 CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 0x1, 4263} GLOBAL_CONTROL_CONTROLLER_RESET; 4264typedef enum AZ_STATE_CHANGE_STATUS { 4265 AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0x0, 4266 AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 0x1, 4267} AZ_STATE_CHANGE_STATUS; 4268typedef enum GLOBAL_STATUS_FLUSH_STATUS { 4269 GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0x0, 4270 GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 0x1, 4271} GLOBAL_STATUS_FLUSH_STATUS; 4272typedef enum STREAM_0_SYNCHRONIZATION { 4273 STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0, 4274 STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 0x1, 4275} STREAM_0_SYNCHRONIZATION; 4276typedef enum STREAM_1_SYNCHRONIZATION { 4277 STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0, 4278 STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 0x1, 4279} STREAM_1_SYNCHRONIZATION; 4280typedef enum STREAM_2_SYNCHRONIZATION { 4281 STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0, 4282 STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 0x1, 4283} STREAM_2_SYNCHRONIZATION; 4284typedef enum STREAM_3_SYNCHRONIZATION { 4285 STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0, 4286 STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 0x1, 4287} STREAM_3_SYNCHRONIZATION; 4288typedef enum STREAM_4_SYNCHRONIZATION { 4289 STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0, 4290 STREAM_4_SYNCHRONIZATION_STEAM_STOPPED = 0x1, 4291} STREAM_4_SYNCHRONIZATION; 4292typedef enum STREAM_5_SYNCHRONIZATION { 4293 STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0, 4294 STREAM_5_SYNCHRONIZATION_STEAM_STOPPED = 0x1, 4295} STREAM_5_SYNCHRONIZATION; 4296typedef enum STREAM_6_SYNCHRONIZATION { 4297 STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, 4298 STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, 4299} STREAM_6_SYNCHRONIZATION; 4300typedef enum STREAM_7_SYNCHRONIZATION { 4301 STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, 4302 STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, 4303} STREAM_7_SYNCHRONIZATION; 4304typedef enum STREAM_8_SYNCHRONIZATION { 4305 STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, 4306 STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, 4307} STREAM_8_SYNCHRONIZATION; 4308typedef enum STREAM_9_SYNCHRONIZATION { 4309 STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, 4310 STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, 4311} STREAM_9_SYNCHRONIZATION; 4312typedef enum STREAM_10_SYNCHRONIZATION { 4313 STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, 4314 STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, 4315} STREAM_10_SYNCHRONIZATION; 4316typedef enum STREAM_11_SYNCHRONIZATION { 4317 STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, 4318 STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, 4319} STREAM_11_SYNCHRONIZATION; 4320typedef enum STREAM_12_SYNCHRONIZATION { 4321 STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, 4322 STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, 4323} STREAM_12_SYNCHRONIZATION; 4324typedef enum STREAM_13_SYNCHRONIZATION { 4325 STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, 4326 STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, 4327} STREAM_13_SYNCHRONIZATION; 4328typedef enum STREAM_14_SYNCHRONIZATION { 4329 STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, 4330 STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, 4331} STREAM_14_SYNCHRONIZATION; 4332typedef enum STREAM_15_SYNCHRONIZATION { 4333 STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, 4334 STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, 4335} STREAM_15_SYNCHRONIZATION; 4336typedef enum CORB_READ_POINTER_RESET { 4337 CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0x0, 4338 CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 0x1, 4339} CORB_READ_POINTER_RESET; 4340typedef enum AZ_CORB_SIZE { 4341 AZ_CORB_SIZE_2ENTRIES_RESERVED = 0x0, 4342 AZ_CORB_SIZE_16ENTRIES_RESERVED = 0x1, 4343 AZ_CORB_SIZE_256ENTRIES = 0x2, 4344 AZ_CORB_SIZE_RESERVED = 0x3, 4345} AZ_CORB_SIZE; 4346typedef enum AZ_RIRB_WRITE_POINTER_RESET { 4347 AZ_RIRB_WRITE_POINTER_NOT_RESET = 0x0, 4348 AZ_RIRB_WRITE_POINTER_DO_RESET = 0x1, 4349} AZ_RIRB_WRITE_POINTER_RESET; 4350typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL { 4351 RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED= 0x0, 4352 RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED= 0x1, 4353} RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL; 4354typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL { 4355 RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED= 0x0, 4356 RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED= 0x1, 4357} RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL; 4358typedef enum AZ_RIRB_SIZE { 4359 AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0x0, 4360 AZ_RIRB_SIZE_16ENTRIES_RESERVED = 0x1, 4361 AZ_RIRB_SIZE_256ENTRIES = 0x2, 4362 AZ_RIRB_SIZE_UNDEFINED = 0x3, 4363} AZ_RIRB_SIZE; 4364typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID { 4365 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID= 0x0, 4366 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID= 0x1, 4367} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID; 4368typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY { 4369 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY= 0x0, 4370 IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY= 0x1, 4371} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY; 4372typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE { 4373 DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE= 0x0, 4374 DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE= 0x1, 4375} DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE; 4376typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR { 4377 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET= 0x0, 4378 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET= 0x1, 4379} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR; 4380typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR { 4381 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET= 0x0, 4382 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET= 0x1, 4383} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR; 4384typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS { 4385 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET= 0x0, 4386 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET= 0x1, 4387} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS; 4388typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY { 4389 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY= 0x0, 4390 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY= 0x1, 4391} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY; 4392typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE { 4393 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED= 0x0, 4394 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED= 0x1, 4395} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE; 4396typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE { 4397 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED= 0x0, 4398 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED= 0x1, 4399} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE; 4400typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE { 4401 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED= 0x0, 4402 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED= 0x1, 4403} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE; 4404typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN { 4405 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN= 0x0, 4406 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN= 0x1, 4407} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN; 4408typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET { 4409 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET= 0x0, 4410 OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET= 0x1, 4411} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET; 4412typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE { 4413 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0, 4414 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1, 4415} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE; 4416typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE { 4417 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0, 4418 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1, 4419 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2, 4420 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3, 4421 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4, 4422} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE; 4423typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR { 4424 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0, 4425 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1, 4426 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2, 4427 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3, 4428 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4, 4429 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5, 4430 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6, 4431 OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7, 4432} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR; 4433typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE { 4434 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0, 4435 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16= 0x1, 4436 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20= 0x2, 4437 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24= 0x3, 4438 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4, 4439 OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5, 4440} OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE; 4441typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS { 4442 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1= 0x0, 4443 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2= 0x1, 4444 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3= 0x2, 4445 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4= 0x3, 4446 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5= 0x4, 4447 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6= 0x5, 4448 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7= 0x6, 4449 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8= 0x7, 4450 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED= 0x8, 4451 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED= 0x9, 4452 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED= 0xa, 4453 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED= 0xb, 4454 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED= 0xc, 4455 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED= 0xd, 4456 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED= 0xe, 4457 OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED= 0xf, 4458} OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS; 4459typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE { 4460 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM= 0x0, 4461 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM= 0x1, 4462} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE; 4463typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE { 4464 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0, 4465 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1, 4466} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE; 4467typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE { 4468 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0, 4469 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1, 4470 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2, 4471 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3, 4472 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4, 4473} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE; 4474typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR { 4475 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0, 4476 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1, 4477 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2, 4478 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3, 4479 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4, 4480 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5, 4481 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6, 4482 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7, 4483} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR; 4484typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE { 4485 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0, 4486 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16= 0x1, 4487 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20= 0x2, 4488 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24= 0x3, 4489 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4, 4490 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5, 4491} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE; 4492typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS { 4493 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1= 0x0, 4494 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2= 0x1, 4495 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3= 0x2, 4496 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4= 0x3, 4497 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5= 0x4, 4498 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6= 0x5, 4499 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7= 0x6, 4500 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8= 0x7, 4501 AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED= 0x8, 4502} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS; 4503typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L { 4504 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET= 0x0, 4505 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET= 0x1, 4506} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L; 4507typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO { 4508 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET= 0x0, 4509 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET= 0x1, 4510} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO; 4511typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO { 4512 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET= 0x0, 4513 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET= 0x1, 4514} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO; 4515typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY { 4516 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET= 0x0, 4517 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET= 0x1, 4518} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY; 4519typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE { 4520 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET= 0x0, 4521 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET= 0x1, 4522} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE; 4523typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG { 4524 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON= 0x0, 4525 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON= 0x1, 4526} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG; 4527typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V { 4528 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO= 0x0, 4529 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE= 0x1, 4530} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V; 4531typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN { 4532 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED= 0x0, 4533 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED= 0x1, 4534} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN; 4535typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE { 4536 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE= 0x0, 4537 AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE= 0x1, 4538} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE; 4539typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE { 4540 AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF= 0x0, 4541 AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN= 0x1, 4542} AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE; 4543typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE { 4544 AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED= 0x0, 4545 AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED= 0x1, 4546} AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE; 4547typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT { 4548 AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED= 0x0, 4549 AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 0x1, 4550} AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT; 4551typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE { 4552 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED= 0x0, 4553 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED= 0x1, 4554} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE; 4555typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE { 4556 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED= 0x0, 4557 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED= 0x1, 4558} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE; 4559typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE { 4560 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED= 0x0, 4561 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED= 0x1, 4562} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE; 4563typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE { 4564 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED= 0x0, 4565 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED= 0x1, 4566} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE; 4567typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE { 4568 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED= 0x0, 4569 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED= 0x1, 4570} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE; 4571typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE { 4572 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED= 0x0, 4573 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED= 0x1, 4574} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE; 4575typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE { 4576 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED= 0x0, 4577 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED= 0x1, 4578} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE; 4579typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE { 4580 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED= 0x0, 4581 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED= 0x1, 4582} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE; 4583typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE { 4584 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE= 0x0, 4585 AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE= 0x1, 4586} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE; 4587typedef enum AZ_LATENCY_COUNTER_CONTROL { 4588 AZ_LATENCY_COUNTER_NO_RESET = 0x0, 4589 AZ_LATENCY_COUNTER_RESET_DONE = 0x1, 4590} AZ_LATENCY_COUNTER_CONTROL; 4591typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { 4592 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0, 4593 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1, 4594 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2, 4595 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3, 4596 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4, 4597 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5, 4598 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6, 4599 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7, 4600 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED= 0x8, 4601 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9, 4602} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; 4603typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { 4604 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0, 4605 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1, 4606} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; 4607typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { 4608 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0, 4609 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1, 4610} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; 4611typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { 4612 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0, 4613 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1, 4614} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; 4615typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { 4616 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0, 4617 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1, 4618} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; 4619typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { 4620 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0, 4621 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1, 4622} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; 4623typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { 4624 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES= 0x0, 4625 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES= 0x1, 4626} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; 4627typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { 4628 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0, 4629 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1, 4630} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; 4631typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE { 4632 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE= 0x0, 4633 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE= 0x1, 4634} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE; 4635typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { 4636 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0, 4637 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1, 4638} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; 4639typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { 4640 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0, 4641 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1, 4642} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; 4643typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { 4644 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0, 4645 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1, 4646} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; 4647typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES { 4648 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC= 0x0, 4649 AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO= 0x1, 4650} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES; 4651typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { 4652 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0, 4653 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1, 4654 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2, 4655 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3, 4656 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4, 4657 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5, 4658 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6, 4659 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7, 4660 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED= 0x8, 4661 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9, 4662} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; 4663typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { 4664 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0, 4665 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1, 4666} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; 4667typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { 4668 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0, 4669 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1, 4670} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; 4671typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { 4672 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0, 4673 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1, 4674} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; 4675typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { 4676 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0, 4677 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1, 4678} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; 4679typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { 4680 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0, 4681 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1, 4682} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; 4683typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { 4684 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES= 0x0, 4685 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES= 0x1, 4686} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; 4687typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { 4688 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0, 4689 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1, 4690} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; 4691typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { 4692 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0, 4693 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1, 4694} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; 4695typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { 4696 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0, 4697 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1, 4698} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; 4699typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { 4700 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT= 0x0, 4701 AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1, 4702} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; 4703typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE { 4704 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN= 0x0, 4705 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN= 0x1, 4706} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE; 4707typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS { 4708 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED= 0x0, 4709 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED= 0x1, 4710} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS; 4711typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE { 4712 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN= 0x0, 4713 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN= 0x1, 4714} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE; 4715typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE { 4716 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN= 0x0, 4717 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN= 0x1, 4718} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE; 4719typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE { 4720 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY= 0x0, 4721 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY= 0x1, 4722} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE; 4723typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY { 4724 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY= 0x0, 4725 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY= 0x1, 4726} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY; 4727typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED { 4728 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x0, 4729 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x1, 4730} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED; 4731typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE { 4732 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY= 0x0, 4733 AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY= 0x1, 4734} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE; 4735typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE { 4736 AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE= 0x0, 4737 AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE= 0x1, 4738} AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE; 4739typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE { 4740 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY= 0x0, 4741 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY= 0x1, 4742} AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE; 4743typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { 4744 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0, 4745 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1, 4746 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2, 4747 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3, 4748 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4, 4749 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5, 4750 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6, 4751 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7, 4752 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED= 0x8, 4753 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9, 4754} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; 4755typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { 4756 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0, 4757 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1, 4758} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; 4759typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { 4760 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0, 4761 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1, 4762} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; 4763typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { 4764 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG= 0x0, 4765 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL= 0x1, 4766} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; 4767typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { 4768 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0, 4769 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1, 4770} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; 4771typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { 4772 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0, 4773 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1, 4774} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; 4775typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { 4776 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES= 0x0, 4777 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES= 0x1, 4778} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; 4779typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { 4780 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING= 0x0, 4781 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1, 4782} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; 4783typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE { 4784 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE= 0x0, 4785 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE= 0x1, 4786} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE; 4787typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { 4788 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0, 4789 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER= 0x1, 4790} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; 4791typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { 4792 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0, 4793 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1, 4794} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; 4795typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { 4796 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0, 4797 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1, 4798} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; 4799typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES { 4800 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC= 0x0, 4801 AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO= 0x1, 4802} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES; 4803typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { 4804 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0, 4805 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1, 4806 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2, 4807 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3, 4808 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4, 4809 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5, 4810 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6, 4811 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7, 4812 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED= 0x8, 4813 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9, 4814} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; 4815typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { 4816 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP= 0x0, 4817 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP= 0x1, 4818} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; 4819typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { 4820 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0, 4821 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1, 4822} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; 4823typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { 4824 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0, 4825 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1, 4826} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; 4827typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { 4828 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0, 4829 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1, 4830} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; 4831typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { 4832 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0, 4833 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1, 4834} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; 4835typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { 4836 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES= 0x0, 4837 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES= 0x1, 4838} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; 4839typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { 4840 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0, 4841 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1, 4842} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; 4843typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { 4844 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0, 4845 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1, 4846} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; 4847typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { 4848 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0, 4849 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1, 4850} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; 4851typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { 4852 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0, 4853 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1, 4854} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; 4855typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP { 4856 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED= 0x0, 4857 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED= 0x1, 4858} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP; 4859typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE { 4860 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN= 0x0, 4861 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN= 0x1, 4862} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE; 4863typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI { 4864 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED= 0x0, 4865 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED= 0x1, 4866} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI; 4867typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS { 4868 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED= 0x0, 4869 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED= 0x1, 4870} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS; 4871typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE { 4872 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN= 0x0, 4873 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN= 0x1, 4874} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE; 4875typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE { 4876 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN= 0x0, 4877 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN= 0x1, 4878} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE; 4879typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE { 4880 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY= 0x0, 4881 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY= 0x1, 4882} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE; 4883typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY { 4884 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY= 0x0, 4885 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY= 0x1, 4886} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY; 4887typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED { 4888 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x0, 4889 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x1, 4890} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED; 4891typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE { 4892 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY= 0x0, 4893 AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY= 0x1, 4894} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE; 4895typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE { 4896 AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY= 0x0, 4897 AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY= 0x1, 4898} AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE; 4899typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE { 4900 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM= 0x0, 4901 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM= 0x1, 4902} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE; 4903typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE { 4904 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0, 4905 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1, 4906} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE; 4907typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE { 4908 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0, 4909 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1, 4910 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2, 4911 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3, 4912 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4, 4913} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE; 4914typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR { 4915 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0, 4916 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1, 4917 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2, 4918 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3, 4919 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4, 4920 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5, 4921 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6, 4922 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7, 4923} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR; 4924typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE { 4925 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0, 4926 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16= 0x1, 4927 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20= 0x2, 4928 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24= 0x3, 4929 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4, 4930 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5, 4931} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE; 4932typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS { 4933 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1= 0x0, 4934 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2= 0x1, 4935 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3= 0x2, 4936 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4= 0x3, 4937 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5= 0x4, 4938 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6= 0x5, 4939 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7= 0x6, 4940 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8= 0x7, 4941 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED= 0x8, 4942} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS; 4943typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN { 4944 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED= 0x0, 4945 AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED= 0x1, 4946} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN; 4947typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE { 4948 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF= 0x0, 4949 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN= 0x1, 4950} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE; 4951typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE { 4952 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED= 0x0, 4953 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED= 0x1, 4954} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE; 4955typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE { 4956 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED= 0x0, 4957 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED= 0x1, 4958} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE; 4959typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE { 4960 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED= 0x0, 4961 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED= 0x1, 4962} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE; 4963typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE { 4964 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED= 0x0, 4965 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED= 0x1, 4966} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE; 4967typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE { 4968 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED= 0x0, 4969 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED= 0x1, 4970} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE; 4971typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE { 4972 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED= 0x0, 4973 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED= 0x1, 4974} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE; 4975typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE { 4976 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED= 0x0, 4977 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED= 0x1, 4978} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE; 4979typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE { 4980 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED= 0x0, 4981 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED= 0x1, 4982} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE; 4983typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE { 4984 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED= 0x0, 4985 AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED= 0x1, 4986} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE; 4987typedef enum BLND_CONTROL_BLND_MODE { 4988 BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x0, 4989 BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 0x1, 4990 BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x2, 4991 BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x3, 4992} BLND_CONTROL_BLND_MODE; 4993typedef enum BLND_CONTROL_BLND_STEREO_TYPE { 4994 BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO= 0x0, 4995 BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO= 0x1, 4996 BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO= 0x2, 4997 BLND_CONTROL_BLND_STEREO_TYPE_UNUSED = 0x3, 4998} BLND_CONTROL_BLND_STEREO_TYPE; 4999typedef enum BLND_CONTROL_BLND_STEREO_POLARITY { 5000 BLND_CONTROL_BLND_STEREO_POLARITY_LOW = 0x0, 5001 BLND_CONTROL_BLND_STEREO_POLARITY_HIGH = 0x1, 5002} BLND_CONTROL_BLND_STEREO_POLARITY; 5003typedef enum BLND_CONTROL_BLND_FEEDTHROUGH_EN { 5004 BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0x0, 5005 BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 0x1, 5006} BLND_CONTROL_BLND_FEEDTHROUGH_EN; 5007typedef enum BLND_CONTROL_BLND_ALPHA_MODE { 5008 BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x0, 5009 BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN= 0x1, 5010 BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x2, 5011 BLND_CONTROL_BLND_ALPHA_MODE_UNUSED = 0x3, 5012} BLND_CONTROL_BLND_ALPHA_MODE; 5013typedef enum BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY { 5014 BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_FALSE = 0x0, 5015 BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_TRUE = 0x1, 5016} BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY; 5017typedef enum BLND_CONTROL_BLND_MULTIPLIED_MODE { 5018 BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x0, 5019 BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 0x1, 5020} BLND_CONTROL_BLND_MULTIPLIED_MODE; 5021typedef enum BLND_SM_CONTROL2_SM_MODE { 5022 BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0x0, 5023 BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x2, 5024 BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x4, 5025 BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING= 0x6, 5026} BLND_SM_CONTROL2_SM_MODE; 5027typedef enum BLND_SM_CONTROL2_SM_FRAME_ALTERNATE { 5028 BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x0, 5029 BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x1, 5030} BLND_SM_CONTROL2_SM_FRAME_ALTERNATE; 5031typedef enum BLND_SM_CONTROL2_SM_FIELD_ALTERNATE { 5032 BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x0, 5033 BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x1, 5034} BLND_SM_CONTROL2_SM_FIELD_ALTERNATE; 5035typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL { 5036 BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE= 0x0, 5037 BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED= 0x1, 5038 BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW= 0x2, 5039 BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH= 0x3, 5040} BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL; 5041typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL { 5042 BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x0, 5043 BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x1, 5044 BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x2, 5045 BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH= 0x3, 5046} BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL; 5047typedef enum BLND_CONTROL2_PTI_ENABLE { 5048 BLND_CONTROL2_PTI_ENABLE_FALSE = 0x0, 5049 BLND_CONTROL2_PTI_ENABLE_TRUE = 0x1, 5050} BLND_CONTROL2_PTI_ENABLE; 5051typedef enum BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN { 5052 BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x0, 5053 BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x1, 5054} BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN; 5055typedef enum BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN { 5056 BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x0, 5057 BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x1, 5058} BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN; 5059typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK { 5060 BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE= 0x0, 5061 BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE= 0x1, 5062} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK; 5063typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK { 5064 BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE= 0x0, 5065 BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE= 0x1, 5066} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK; 5067typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK { 5068 BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE= 0x0, 5069 BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE= 0x1, 5070} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK; 5071typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK { 5072 BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE= 0x0, 5073 BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE= 0x1, 5074} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; 5075typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK { 5076 BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE= 0x0, 5077 BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE= 0x1, 5078} BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK; 5079typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK { 5080 BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE= 0x0, 5081 BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE= 0x1, 5082} BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK; 5083typedef enum BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK { 5084 BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x0, 5085 BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x1, 5086} BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK; 5087typedef enum BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK { 5088 BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x0, 5089 BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x1, 5090} BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK; 5091typedef enum BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE { 5092 BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x0, 5093 BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x1, 5094} BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE; 5095typedef enum BLND_DEBUG_BLND_CNV_MUX_SELECT { 5096 BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0x0, 5097 BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 0x1, 5098} BLND_DEBUG_BLND_CNV_MUX_SELECT; 5099typedef enum BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN { 5100 BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE= 0x0, 5101 BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE= 0x1, 5102} BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN; 5103typedef enum SurfaceEndian { 5104 ENDIAN_NONE = 0x0, 5105 ENDIAN_8IN16 = 0x1, 5106 ENDIAN_8IN32 = 0x2, 5107 ENDIAN_8IN64 = 0x3, 5108} SurfaceEndian; 5109typedef enum ArrayMode { 5110 ARRAY_LINEAR_GENERAL = 0x0, 5111 ARRAY_LINEAR_ALIGNED = 0x1, 5112 ARRAY_1D_TILED_THIN1 = 0x2, 5113 ARRAY_1D_TILED_THICK = 0x3, 5114 ARRAY_2D_TILED_THIN1 = 0x4, 5115 ARRAY_PRT_TILED_THIN1 = 0x5, 5116 ARRAY_PRT_2D_TILED_THIN1 = 0x6, 5117 ARRAY_2D_TILED_THICK = 0x7, 5118 ARRAY_2D_TILED_XTHICK = 0x8, 5119 ARRAY_PRT_TILED_THICK = 0x9, 5120 ARRAY_PRT_2D_TILED_THICK = 0xa, 5121 ARRAY_PRT_3D_TILED_THIN1 = 0xb, 5122 ARRAY_3D_TILED_THIN1 = 0xc, 5123 ARRAY_3D_TILED_THICK = 0xd, 5124 ARRAY_3D_TILED_XTHICK = 0xe, 5125 ARRAY_PRT_3D_TILED_THICK = 0xf, 5126} ArrayMode; 5127typedef enum PipeTiling { 5128 CONFIG_1_PIPE = 0x0, 5129 CONFIG_2_PIPE = 0x1, 5130 CONFIG_4_PIPE = 0x2, 5131 CONFIG_8_PIPE = 0x3, 5132} PipeTiling; 5133typedef enum BankTiling { 5134 CONFIG_4_BANK = 0x0, 5135 CONFIG_8_BANK = 0x1, 5136} BankTiling; 5137typedef enum GroupInterleave { 5138 CONFIG_256B_GROUP = 0x0, 5139 CONFIG_512B_GROUP = 0x1, 5140} GroupInterleave; 5141typedef enum RowTiling { 5142 CONFIG_1KB_ROW = 0x0, 5143 CONFIG_2KB_ROW = 0x1, 5144 CONFIG_4KB_ROW = 0x2, 5145 CONFIG_8KB_ROW = 0x3, 5146 CONFIG_1KB_ROW_OPT = 0x4, 5147 CONFIG_2KB_ROW_OPT = 0x5, 5148 CONFIG_4KB_ROW_OPT = 0x6, 5149 CONFIG_8KB_ROW_OPT = 0x7, 5150} RowTiling; 5151typedef enum BankSwapBytes { 5152 CONFIG_128B_SWAPS = 0x0, 5153 CONFIG_256B_SWAPS = 0x1, 5154 CONFIG_512B_SWAPS = 0x2, 5155 CONFIG_1KB_SWAPS = 0x3, 5156} BankSwapBytes; 5157typedef enum SampleSplitBytes { 5158 CONFIG_1KB_SPLIT = 0x0, 5159 CONFIG_2KB_SPLIT = 0x1, 5160 CONFIG_4KB_SPLIT = 0x2, 5161 CONFIG_8KB_SPLIT = 0x3, 5162} SampleSplitBytes; 5163typedef enum NumPipes { 5164 ADDR_CONFIG_1_PIPE = 0x0, 5165 ADDR_CONFIG_2_PIPE = 0x1, 5166 ADDR_CONFIG_4_PIPE = 0x2, 5167 ADDR_CONFIG_8_PIPE = 0x3, 5168} NumPipes; 5169typedef enum PipeInterleaveSize { 5170 ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, 5171 ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, 5172} PipeInterleaveSize; 5173typedef enum BankInterleaveSize { 5174 ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, 5175 ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, 5176 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, 5177 ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, 5178} BankInterleaveSize; 5179typedef enum NumShaderEngines { 5180 ADDR_CONFIG_1_SHADER_ENGINE = 0x0, 5181 ADDR_CONFIG_2_SHADER_ENGINE = 0x1, 5182} NumShaderEngines; 5183typedef enum ShaderEngineTileSize { 5184 ADDR_CONFIG_SE_TILE_16 = 0x0, 5185 ADDR_CONFIG_SE_TILE_32 = 0x1, 5186} ShaderEngineTileSize; 5187typedef enum NumGPUs { 5188 ADDR_CONFIG_1_GPU = 0x0, 5189 ADDR_CONFIG_2_GPU = 0x1, 5190 ADDR_CONFIG_4_GPU = 0x2, 5191} NumGPUs; 5192typedef enum MultiGPUTileSize { 5193 ADDR_CONFIG_GPU_TILE_16 = 0x0, 5194 ADDR_CONFIG_GPU_TILE_32 = 0x1, 5195 ADDR_CONFIG_GPU_TILE_64 = 0x2, 5196 ADDR_CONFIG_GPU_TILE_128 = 0x3, 5197} MultiGPUTileSize; 5198typedef enum RowSize { 5199 ADDR_CONFIG_1KB_ROW = 0x0, 5200 ADDR_CONFIG_2KB_ROW = 0x1, 5201 ADDR_CONFIG_4KB_ROW = 0x2, 5202} RowSize; 5203typedef enum NumLowerPipes { 5204 ADDR_CONFIG_1_LOWER_PIPES = 0x0, 5205 ADDR_CONFIG_2_LOWER_PIPES = 0x1, 5206} NumLowerPipes; 5207typedef enum DebugBlockId { 5208 DBG_CLIENT_BLKID_RESERVED = 0x0, 5209 DBG_CLIENT_BLKID_dbg = 0x1, 5210 DBG_CLIENT_BLKID_scf2 = 0x2, 5211 DBG_CLIENT_BLKID_mcd5 = 0x3, 5212 DBG_CLIENT_BLKID_vmc = 0x4, 5213 DBG_CLIENT_BLKID_sx30 = 0x5, 5214 DBG_CLIENT_BLKID_mcd2 = 0x6, 5215 DBG_CLIENT_BLKID_bci1 = 0x7, 5216 DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8, 5217 DBG_CLIENT_BLKID_mcc0 = 0x9, 5218 DBG_CLIENT_BLKID_uvdf_2 = 0xa, 5219 DBG_CLIENT_BLKID_uvdf_3 = 0xb, 5220 DBG_CLIENT_BLKID_uvdt_0 = 0xc, 5221 DBG_CLIENT_BLKID_uvdi_0 = 0xd, 5222 DBG_CLIENT_BLKID_bci0 = 0xe, 5223 DBG_CLIENT_BLKID_vceb0_1 = 0xf, 5224 DBG_CLIENT_BLKID_cb100 = 0x10, 5225 DBG_CLIENT_BLKID_cb001 = 0x11, 5226 DBG_CLIENT_BLKID_mcd4 = 0x12, 5227 DBG_CLIENT_BLKID_tmonw00 = 0x13, 5228 DBG_CLIENT_BLKID_cb101 = 0x14, 5229 DBG_CLIENT_BLKID_sx10 = 0x15, 5230 DBG_CLIENT_BLKID_cb301 = 0x16, 5231 DBG_CLIENT_BLKID_tmonw01 = 0x17, 5232 DBG_CLIENT_BLKID_vcea0_0 = 0x18, 5233 DBG_CLIENT_BLKID_vcea0_1 = 0x19, 5234 DBG_CLIENT_BLKID_vcea0_2 = 0x1a, 5235 DBG_CLIENT_BLKID_vcea0_3 = 0x1b, 5236 DBG_CLIENT_BLKID_scf1 = 0x1c, 5237 DBG_CLIENT_BLKID_sx20 = 0x1d, 5238 DBG_CLIENT_BLKID_spim1 = 0x1e, 5239 DBG_CLIENT_BLKID_pa10 = 0x1f, 5240 DBG_CLIENT_BLKID_pa00 = 0x20, 5241 DBG_CLIENT_BLKID_gmcon = 0x21, 5242 DBG_CLIENT_BLKID_mcb = 0x22, 5243 DBG_CLIENT_BLKID_vgt0 = 0x23, 5244 DBG_CLIENT_BLKID_pc0 = 0x24, 5245 DBG_CLIENT_BLKID_bci2 = 0x25, 5246 DBG_CLIENT_BLKID_uvdb_0 = 0x26, 5247 DBG_CLIENT_BLKID_spim3 = 0x27, 5248 DBG_CLIENT_BLKID_cpc_0 = 0x28, 5249 DBG_CLIENT_BLKID_cpc_1 = 0x29, 5250 DBG_CLIENT_BLKID_uvdm_0 = 0x2a, 5251 DBG_CLIENT_BLKID_uvdm_1 = 0x2b, 5252 DBG_CLIENT_BLKID_uvdm_2 = 0x2c, 5253 DBG_CLIENT_BLKID_uvdm_3 = 0x2d, 5254 DBG_CLIENT_BLKID_cb000 = 0x2e, 5255 DBG_CLIENT_BLKID_spim0 = 0x2f, 5256 DBG_CLIENT_BLKID_mcc2 = 0x30, 5257 DBG_CLIENT_BLKID_ds0 = 0x31, 5258 DBG_CLIENT_BLKID_srbm = 0x32, 5259 DBG_CLIENT_BLKID_ih = 0x33, 5260 DBG_CLIENT_BLKID_sem = 0x34, 5261 DBG_CLIENT_BLKID_sdma_0 = 0x35, 5262 DBG_CLIENT_BLKID_sdma_1 = 0x36, 5263 DBG_CLIENT_BLKID_hdp = 0x37, 5264 DBG_CLIENT_BLKID_cb200 = 0x38, 5265 DBG_CLIENT_BLKID_scf3 = 0x39, 5266 DBG_CLIENT_BLKID_vceb1_0 = 0x3a, 5267 DBG_CLIENT_BLKID_vcea1_0 = 0x3b, 5268 DBG_CLIENT_BLKID_vcea1_1 = 0x3c, 5269 DBG_CLIENT_BLKID_vcea1_2 = 0x3d, 5270 DBG_CLIENT_BLKID_vcea1_3 = 0x3e, 5271 DBG_CLIENT_BLKID_bci3 = 0x3f, 5272 DBG_CLIENT_BLKID_mcd0 = 0x40, 5273 DBG_CLIENT_BLKID_pa11 = 0x41, 5274 DBG_CLIENT_BLKID_pa01 = 0x42, 5275 DBG_CLIENT_BLKID_cb201 = 0x43, 5276 DBG_CLIENT_BLKID_spim2 = 0x44, 5277 DBG_CLIENT_BLKID_vgt2 = 0x45, 5278 DBG_CLIENT_BLKID_pc2 = 0x46, 5279 DBG_CLIENT_BLKID_smu_0 = 0x47, 5280 DBG_CLIENT_BLKID_smu_1 = 0x48, 5281 DBG_CLIENT_BLKID_smu_2 = 0x49, 5282 DBG_CLIENT_BLKID_cb1 = 0x4a, 5283 DBG_CLIENT_BLKID_ia0 = 0x4b, 5284 DBG_CLIENT_BLKID_wd = 0x4c, 5285 DBG_CLIENT_BLKID_ia1 = 0x4d, 5286 DBG_CLIENT_BLKID_vcec1_0 = 0x4e, 5287 DBG_CLIENT_BLKID_scf0 = 0x4f, 5288 DBG_CLIENT_BLKID_vgt1 = 0x50, 5289 DBG_CLIENT_BLKID_pc1 = 0x51, 5290 DBG_CLIENT_BLKID_cb0 = 0x52, 5291 DBG_CLIENT_BLKID_gdc_one_0 = 0x53, 5292 DBG_CLIENT_BLKID_gdc_one_1 = 0x54, 5293 DBG_CLIENT_BLKID_gdc_one_2 = 0x55, 5294 DBG_CLIENT_BLKID_gdc_one_3 = 0x56, 5295 DBG_CLIENT_BLKID_gdc_one_4 = 0x57, 5296 DBG_CLIENT_BLKID_gdc_one_5 = 0x58, 5297 DBG_CLIENT_BLKID_gdc_one_6 = 0x59, 5298 DBG_CLIENT_BLKID_gdc_one_7 = 0x5a, 5299 DBG_CLIENT_BLKID_gdc_one_8 = 0x5b, 5300 DBG_CLIENT_BLKID_gdc_one_9 = 0x5c, 5301 DBG_CLIENT_BLKID_gdc_one_10 = 0x5d, 5302 DBG_CLIENT_BLKID_gdc_one_11 = 0x5e, 5303 DBG_CLIENT_BLKID_gdc_one_12 = 0x5f, 5304 DBG_CLIENT_BLKID_gdc_one_13 = 0x60, 5305 DBG_CLIENT_BLKID_gdc_one_14 = 0x61, 5306 DBG_CLIENT_BLKID_gdc_one_15 = 0x62, 5307 DBG_CLIENT_BLKID_gdc_one_16 = 0x63, 5308 DBG_CLIENT_BLKID_gdc_one_17 = 0x64, 5309 DBG_CLIENT_BLKID_gdc_one_18 = 0x65, 5310 DBG_CLIENT_BLKID_gdc_one_19 = 0x66, 5311 DBG_CLIENT_BLKID_gdc_one_20 = 0x67, 5312 DBG_CLIENT_BLKID_gdc_one_21 = 0x68, 5313 DBG_CLIENT_BLKID_gdc_one_22 = 0x69, 5314 DBG_CLIENT_BLKID_gdc_one_23 = 0x6a, 5315 DBG_CLIENT_BLKID_gdc_one_24 = 0x6b, 5316 DBG_CLIENT_BLKID_gdc_one_25 = 0x6c, 5317 DBG_CLIENT_BLKID_gdc_one_26 = 0x6d, 5318 DBG_CLIENT_BLKID_gdc_one_27 = 0x6e, 5319 DBG_CLIENT_BLKID_gdc_one_28 = 0x6f, 5320 DBG_CLIENT_BLKID_gdc_one_29 = 0x70, 5321 DBG_CLIENT_BLKID_gdc_one_30 = 0x71, 5322 DBG_CLIENT_BLKID_gdc_one_31 = 0x72, 5323 DBG_CLIENT_BLKID_gdc_one_32 = 0x73, 5324 DBG_CLIENT_BLKID_gdc_one_33 = 0x74, 5325 DBG_CLIENT_BLKID_gdc_one_34 = 0x75, 5326 DBG_CLIENT_BLKID_gdc_one_35 = 0x76, 5327 DBG_CLIENT_BLKID_vceb0_0 = 0x77, 5328 DBG_CLIENT_BLKID_vgt3 = 0x78, 5329 DBG_CLIENT_BLKID_pc3 = 0x79, 5330 DBG_CLIENT_BLKID_mcd3 = 0x7a, 5331 DBG_CLIENT_BLKID_uvdu_0 = 0x7b, 5332 DBG_CLIENT_BLKID_uvdu_1 = 0x7c, 5333 DBG_CLIENT_BLKID_uvdu_2 = 0x7d, 5334 DBG_CLIENT_BLKID_uvdu_3 = 0x7e, 5335 DBG_CLIENT_BLKID_uvdu_4 = 0x7f, 5336 DBG_CLIENT_BLKID_uvdu_5 = 0x80, 5337 DBG_CLIENT_BLKID_uvdu_6 = 0x81, 5338 DBG_CLIENT_BLKID_cb300 = 0x82, 5339 DBG_CLIENT_BLKID_mcd1 = 0x83, 5340 DBG_CLIENT_BLKID_sx00 = 0x84, 5341 DBG_CLIENT_BLKID_uvdf_0 = 0x85, 5342 DBG_CLIENT_BLKID_uvdf_1 = 0x86, 5343 DBG_CLIENT_BLKID_mcc3 = 0x87, 5344 DBG_CLIENT_BLKID_cpg_0 = 0x88, 5345 DBG_CLIENT_BLKID_cpg_1 = 0x89, 5346 DBG_CLIENT_BLKID_gck = 0x8a, 5347 DBG_CLIENT_BLKID_mcc1 = 0x8b, 5348 DBG_CLIENT_BLKID_cpf_0 = 0x8c, 5349 DBG_CLIENT_BLKID_cpf_1 = 0x8d, 5350 DBG_CLIENT_BLKID_rlc = 0x8e, 5351 DBG_CLIENT_BLKID_grbm = 0x8f, 5352 DBG_CLIENT_BLKID_sammsp = 0x90, 5353 DBG_CLIENT_BLKID_dci_pg = 0x91, 5354 DBG_CLIENT_BLKID_dci_0 = 0x92, 5355 DBG_CLIENT_BLKID_dccg0_0 = 0x93, 5356 DBG_CLIENT_BLKID_dccg0_1 = 0x94, 5357 DBG_CLIENT_BLKID_dccg0_2 = 0x95, 5358 DBG_CLIENT_BLKID_dccg0_3 = 0x96, 5359 DBG_CLIENT_BLKID_dccg0_4 = 0x97, 5360 DBG_CLIENT_BLKID_dccg0_5 = 0x98, 5361 DBG_CLIENT_BLKID_dccg0_6 = 0x99, 5362 DBG_CLIENT_BLKID_dccg0_7 = 0x9a, 5363 DBG_CLIENT_BLKID_dccg0_8 = 0x9b, 5364 DBG_CLIENT_BLKID_dcfe01_0 = 0x9c, 5365 DBG_CLIENT_BLKID_dcfe02_0 = 0x9d, 5366 DBG_CLIENT_BLKID_dcfe03_0 = 0x9e, 5367 DBG_CLIENT_BLKID_dcfe04_0 = 0x9f, 5368 DBG_CLIENT_BLKID_dcfe05_0 = 0xa0, 5369 DBG_CLIENT_BLKID_dcfe06_0 = 0xa1, 5370 DBG_CLIENT_BLKID_uvde_0 = 0xa2, 5371 DBG_CLIENT_BLKID_RESERVED_LAST = 0xa3, 5372} DebugBlockId; 5373typedef enum DebugBlockId_OLD { 5374 DBG_BLOCK_ID_RESERVED = 0x0, 5375 DBG_BLOCK_ID_DBG = 0x1, 5376 DBG_BLOCK_ID_VMC = 0x2, 5377 DBG_BLOCK_ID_PDMA = 0x3, 5378 DBG_BLOCK_ID_CG = 0x4, 5379 DBG_BLOCK_ID_SRBM = 0x5, 5380 DBG_BLOCK_ID_GRBM = 0x6, 5381 DBG_BLOCK_ID_RLC = 0x7, 5382 DBG_BLOCK_ID_CSC = 0x8, 5383 DBG_BLOCK_ID_SEM = 0x9, 5384 DBG_BLOCK_ID_IH = 0xa, 5385 DBG_BLOCK_ID_SC = 0xb, 5386 DBG_BLOCK_ID_SQ = 0xc, 5387 DBG_BLOCK_ID_AVP = 0xd, 5388 DBG_BLOCK_ID_GMCON = 0xe, 5389 DBG_BLOCK_ID_SMU = 0xf, 5390 DBG_BLOCK_ID_DMA0 = 0x10, 5391 DBG_BLOCK_ID_DMA1 = 0x11, 5392 DBG_BLOCK_ID_SPIM = 0x12, 5393 DBG_BLOCK_ID_GDS = 0x13, 5394 DBG_BLOCK_ID_SPIS = 0x14, 5395 DBG_BLOCK_ID_UNUSED0 = 0x15, 5396 DBG_BLOCK_ID_PA0 = 0x16, 5397 DBG_BLOCK_ID_PA1 = 0x17, 5398 DBG_BLOCK_ID_CP0 = 0x18, 5399 DBG_BLOCK_ID_CP1 = 0x19, 5400 DBG_BLOCK_ID_CP2 = 0x1a, 5401 DBG_BLOCK_ID_UNUSED1 = 0x1b, 5402 DBG_BLOCK_ID_UVDU = 0x1c, 5403 DBG_BLOCK_ID_UVDM = 0x1d, 5404 DBG_BLOCK_ID_VCE = 0x1e, 5405 DBG_BLOCK_ID_UNUSED2 = 0x1f, 5406 DBG_BLOCK_ID_VGT0 = 0x20, 5407 DBG_BLOCK_ID_VGT1 = 0x21, 5408 DBG_BLOCK_ID_IA = 0x22, 5409 DBG_BLOCK_ID_UNUSED3 = 0x23, 5410 DBG_BLOCK_ID_SCT0 = 0x24, 5411 DBG_BLOCK_ID_SCT1 = 0x25, 5412 DBG_BLOCK_ID_SPM0 = 0x26, 5413 DBG_BLOCK_ID_SPM1 = 0x27, 5414 DBG_BLOCK_ID_TCAA = 0x28, 5415 DBG_BLOCK_ID_TCAB = 0x29, 5416 DBG_BLOCK_ID_TCCA = 0x2a, 5417 DBG_BLOCK_ID_TCCB = 0x2b, 5418 DBG_BLOCK_ID_MCC0 = 0x2c, 5419 DBG_BLOCK_ID_MCC1 = 0x2d, 5420 DBG_BLOCK_ID_MCC2 = 0x2e, 5421 DBG_BLOCK_ID_MCC3 = 0x2f, 5422 DBG_BLOCK_ID_SX0 = 0x30, 5423 DBG_BLOCK_ID_SX1 = 0x31, 5424 DBG_BLOCK_ID_SX2 = 0x32, 5425 DBG_BLOCK_ID_SX3 = 0x33, 5426 DBG_BLOCK_ID_UNUSED4 = 0x34, 5427 DBG_BLOCK_ID_UNUSED5 = 0x35, 5428 DBG_BLOCK_ID_UNUSED6 = 0x36, 5429 DBG_BLOCK_ID_UNUSED7 = 0x37, 5430 DBG_BLOCK_ID_PC0 = 0x38, 5431 DBG_BLOCK_ID_PC1 = 0x39, 5432 DBG_BLOCK_ID_UNUSED8 = 0x3a, 5433 DBG_BLOCK_ID_UNUSED9 = 0x3b, 5434 DBG_BLOCK_ID_UNUSED10 = 0x3c, 5435 DBG_BLOCK_ID_UNUSED11 = 0x3d, 5436 DBG_BLOCK_ID_MCB = 0x3e, 5437 DBG_BLOCK_ID_UNUSED12 = 0x3f, 5438 DBG_BLOCK_ID_SCB0 = 0x40, 5439 DBG_BLOCK_ID_SCB1 = 0x41, 5440 DBG_BLOCK_ID_UNUSED13 = 0x42, 5441 DBG_BLOCK_ID_UNUSED14 = 0x43, 5442 DBG_BLOCK_ID_SCF0 = 0x44, 5443 DBG_BLOCK_ID_SCF1 = 0x45, 5444 DBG_BLOCK_ID_UNUSED15 = 0x46, 5445 DBG_BLOCK_ID_UNUSED16 = 0x47, 5446 DBG_BLOCK_ID_BCI0 = 0x48, 5447 DBG_BLOCK_ID_BCI1 = 0x49, 5448 DBG_BLOCK_ID_BCI2 = 0x4a, 5449 DBG_BLOCK_ID_BCI3 = 0x4b, 5450 DBG_BLOCK_ID_UNUSED17 = 0x4c, 5451 DBG_BLOCK_ID_UNUSED18 = 0x4d, 5452 DBG_BLOCK_ID_UNUSED19 = 0x4e, 5453 DBG_BLOCK_ID_UNUSED20 = 0x4f, 5454 DBG_BLOCK_ID_CB00 = 0x50, 5455 DBG_BLOCK_ID_CB01 = 0x51, 5456 DBG_BLOCK_ID_CB02 = 0x52, 5457 DBG_BLOCK_ID_CB03 = 0x53, 5458 DBG_BLOCK_ID_CB04 = 0x54, 5459 DBG_BLOCK_ID_UNUSED21 = 0x55, 5460 DBG_BLOCK_ID_UNUSED22 = 0x56, 5461 DBG_BLOCK_ID_UNUSED23 = 0x57, 5462 DBG_BLOCK_ID_CB10 = 0x58, 5463 DBG_BLOCK_ID_CB11 = 0x59, 5464 DBG_BLOCK_ID_CB12 = 0x5a, 5465 DBG_BLOCK_ID_CB13 = 0x5b, 5466 DBG_BLOCK_ID_CB14 = 0x5c, 5467 DBG_BLOCK_ID_UNUSED24 = 0x5d, 5468 DBG_BLOCK_ID_UNUSED25 = 0x5e, 5469 DBG_BLOCK_ID_UNUSED26 = 0x5f, 5470 DBG_BLOCK_ID_TCP0 = 0x60, 5471 DBG_BLOCK_ID_TCP1 = 0x61, 5472 DBG_BLOCK_ID_TCP2 = 0x62, 5473 DBG_BLOCK_ID_TCP3 = 0x63, 5474 DBG_BLOCK_ID_TCP4 = 0x64, 5475 DBG_BLOCK_ID_TCP5 = 0x65, 5476 DBG_BLOCK_ID_TCP6 = 0x66, 5477 DBG_BLOCK_ID_TCP7 = 0x67, 5478 DBG_BLOCK_ID_TCP8 = 0x68, 5479 DBG_BLOCK_ID_TCP9 = 0x69, 5480 DBG_BLOCK_ID_TCP10 = 0x6a, 5481 DBG_BLOCK_ID_TCP11 = 0x6b, 5482 DBG_BLOCK_ID_TCP12 = 0x6c, 5483 DBG_BLOCK_ID_TCP13 = 0x6d, 5484 DBG_BLOCK_ID_TCP14 = 0x6e, 5485 DBG_BLOCK_ID_TCP15 = 0x6f, 5486 DBG_BLOCK_ID_TCP16 = 0x70, 5487 DBG_BLOCK_ID_TCP17 = 0x71, 5488 DBG_BLOCK_ID_TCP18 = 0x72, 5489 DBG_BLOCK_ID_TCP19 = 0x73, 5490 DBG_BLOCK_ID_TCP20 = 0x74, 5491 DBG_BLOCK_ID_TCP21 = 0x75, 5492 DBG_BLOCK_ID_TCP22 = 0x76, 5493 DBG_BLOCK_ID_TCP23 = 0x77, 5494 DBG_BLOCK_ID_TCP_RESERVED0 = 0x78, 5495 DBG_BLOCK_ID_TCP_RESERVED1 = 0x79, 5496 DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a, 5497 DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b, 5498 DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c, 5499 DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d, 5500 DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e, 5501 DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f, 5502 DBG_BLOCK_ID_DB00 = 0x80, 5503 DBG_BLOCK_ID_DB01 = 0x81, 5504 DBG_BLOCK_ID_DB02 = 0x82, 5505 DBG_BLOCK_ID_DB03 = 0x83, 5506 DBG_BLOCK_ID_DB04 = 0x84, 5507 DBG_BLOCK_ID_UNUSED27 = 0x85, 5508 DBG_BLOCK_ID_UNUSED28 = 0x86, 5509 DBG_BLOCK_ID_UNUSED29 = 0x87, 5510 DBG_BLOCK_ID_DB10 = 0x88, 5511 DBG_BLOCK_ID_DB11 = 0x89, 5512 DBG_BLOCK_ID_DB12 = 0x8a, 5513 DBG_BLOCK_ID_DB13 = 0x8b, 5514 DBG_BLOCK_ID_DB14 = 0x8c, 5515 DBG_BLOCK_ID_UNUSED30 = 0x8d, 5516 DBG_BLOCK_ID_UNUSED31 = 0x8e, 5517 DBG_BLOCK_ID_UNUSED32 = 0x8f, 5518 DBG_BLOCK_ID_TCC0 = 0x90, 5519 DBG_BLOCK_ID_TCC1 = 0x91, 5520 DBG_BLOCK_ID_TCC2 = 0x92, 5521 DBG_BLOCK_ID_TCC3 = 0x93, 5522 DBG_BLOCK_ID_TCC4 = 0x94, 5523 DBG_BLOCK_ID_TCC5 = 0x95, 5524 DBG_BLOCK_ID_TCC6 = 0x96, 5525 DBG_BLOCK_ID_TCC7 = 0x97, 5526 DBG_BLOCK_ID_SPS00 = 0x98, 5527 DBG_BLOCK_ID_SPS01 = 0x99, 5528 DBG_BLOCK_ID_SPS02 = 0x9a, 5529 DBG_BLOCK_ID_SPS10 = 0x9b, 5530 DBG_BLOCK_ID_SPS11 = 0x9c, 5531 DBG_BLOCK_ID_SPS12 = 0x9d, 5532 DBG_BLOCK_ID_UNUSED33 = 0x9e, 5533 DBG_BLOCK_ID_UNUSED34 = 0x9f, 5534 DBG_BLOCK_ID_TA00 = 0xa0, 5535 DBG_BLOCK_ID_TA01 = 0xa1, 5536 DBG_BLOCK_ID_TA02 = 0xa2, 5537 DBG_BLOCK_ID_TA03 = 0xa3, 5538 DBG_BLOCK_ID_TA04 = 0xa4, 5539 DBG_BLOCK_ID_TA05 = 0xa5, 5540 DBG_BLOCK_ID_TA06 = 0xa6, 5541 DBG_BLOCK_ID_TA07 = 0xa7, 5542 DBG_BLOCK_ID_TA08 = 0xa8, 5543 DBG_BLOCK_ID_TA09 = 0xa9, 5544 DBG_BLOCK_ID_TA0A = 0xaa, 5545 DBG_BLOCK_ID_TA0B = 0xab, 5546 DBG_BLOCK_ID_UNUSED35 = 0xac, 5547 DBG_BLOCK_ID_UNUSED36 = 0xad, 5548 DBG_BLOCK_ID_UNUSED37 = 0xae, 5549 DBG_BLOCK_ID_UNUSED38 = 0xaf, 5550 DBG_BLOCK_ID_TA10 = 0xb0, 5551 DBG_BLOCK_ID_TA11 = 0xb1, 5552 DBG_BLOCK_ID_TA12 = 0xb2, 5553 DBG_BLOCK_ID_TA13 = 0xb3, 5554 DBG_BLOCK_ID_TA14 = 0xb4, 5555 DBG_BLOCK_ID_TA15 = 0xb5, 5556 DBG_BLOCK_ID_TA16 = 0xb6, 5557 DBG_BLOCK_ID_TA17 = 0xb7, 5558 DBG_BLOCK_ID_TA18 = 0xb8, 5559 DBG_BLOCK_ID_TA19 = 0xb9, 5560 DBG_BLOCK_ID_TA1A = 0xba, 5561 DBG_BLOCK_ID_TA1B = 0xbb, 5562 DBG_BLOCK_ID_UNUSED39 = 0xbc, 5563 DBG_BLOCK_ID_UNUSED40 = 0xbd, 5564 DBG_BLOCK_ID_UNUSED41 = 0xbe, 5565 DBG_BLOCK_ID_UNUSED42 = 0xbf, 5566 DBG_BLOCK_ID_TD00 = 0xc0, 5567 DBG_BLOCK_ID_TD01 = 0xc1, 5568 DBG_BLOCK_ID_TD02 = 0xc2, 5569 DBG_BLOCK_ID_TD03 = 0xc3, 5570 DBG_BLOCK_ID_TD04 = 0xc4, 5571 DBG_BLOCK_ID_TD05 = 0xc5, 5572 DBG_BLOCK_ID_TD06 = 0xc6, 5573 DBG_BLOCK_ID_TD07 = 0xc7, 5574 DBG_BLOCK_ID_TD08 = 0xc8, 5575 DBG_BLOCK_ID_TD09 = 0xc9, 5576 DBG_BLOCK_ID_TD0A = 0xca, 5577 DBG_BLOCK_ID_TD0B = 0xcb, 5578 DBG_BLOCK_ID_UNUSED43 = 0xcc, 5579 DBG_BLOCK_ID_UNUSED44 = 0xcd, 5580 DBG_BLOCK_ID_UNUSED45 = 0xce, 5581 DBG_BLOCK_ID_UNUSED46 = 0xcf, 5582 DBG_BLOCK_ID_TD10 = 0xd0, 5583 DBG_BLOCK_ID_TD11 = 0xd1, 5584 DBG_BLOCK_ID_TD12 = 0xd2, 5585 DBG_BLOCK_ID_TD13 = 0xd3, 5586 DBG_BLOCK_ID_TD14 = 0xd4, 5587 DBG_BLOCK_ID_TD15 = 0xd5, 5588 DBG_BLOCK_ID_TD16 = 0xd6, 5589 DBG_BLOCK_ID_TD17 = 0xd7, 5590 DBG_BLOCK_ID_TD18 = 0xd8, 5591 DBG_BLOCK_ID_TD19 = 0xd9, 5592 DBG_BLOCK_ID_TD1A = 0xda, 5593 DBG_BLOCK_ID_TD1B = 0xdb, 5594 DBG_BLOCK_ID_UNUSED47 = 0xdc, 5595 DBG_BLOCK_ID_UNUSED48 = 0xdd, 5596 DBG_BLOCK_ID_UNUSED49 = 0xde, 5597 DBG_BLOCK_ID_UNUSED50 = 0xdf, 5598 DBG_BLOCK_ID_MCD0 = 0xe0, 5599 DBG_BLOCK_ID_MCD1 = 0xe1, 5600 DBG_BLOCK_ID_MCD2 = 0xe2, 5601 DBG_BLOCK_ID_MCD3 = 0xe3, 5602 DBG_BLOCK_ID_MCD4 = 0xe4, 5603 DBG_BLOCK_ID_MCD5 = 0xe5, 5604 DBG_BLOCK_ID_UNUSED51 = 0xe6, 5605 DBG_BLOCK_ID_UNUSED52 = 0xe7, 5606} DebugBlockId_OLD; 5607typedef enum DebugBlockId_BY2 { 5608 DBG_BLOCK_ID_RESERVED_BY2 = 0x0, 5609 DBG_BLOCK_ID_VMC_BY2 = 0x1, 5610 DBG_BLOCK_ID_CG_BY2 = 0x2, 5611 DBG_BLOCK_ID_GRBM_BY2 = 0x3, 5612 DBG_BLOCK_ID_CSC_BY2 = 0x4, 5613 DBG_BLOCK_ID_IH_BY2 = 0x5, 5614 DBG_BLOCK_ID_SQ_BY2 = 0x6, 5615 DBG_BLOCK_ID_GMCON_BY2 = 0x7, 5616 DBG_BLOCK_ID_DMA0_BY2 = 0x8, 5617 DBG_BLOCK_ID_SPIM_BY2 = 0x9, 5618 DBG_BLOCK_ID_SPIS_BY2 = 0xa, 5619 DBG_BLOCK_ID_PA0_BY2 = 0xb, 5620 DBG_BLOCK_ID_CP0_BY2 = 0xc, 5621 DBG_BLOCK_ID_CP2_BY2 = 0xd, 5622 DBG_BLOCK_ID_UVDU_BY2 = 0xe, 5623 DBG_BLOCK_ID_VCE_BY2 = 0xf, 5624 DBG_BLOCK_ID_VGT0_BY2 = 0x10, 5625 DBG_BLOCK_ID_IA_BY2 = 0x11, 5626 DBG_BLOCK_ID_SCT0_BY2 = 0x12, 5627 DBG_BLOCK_ID_SPM0_BY2 = 0x13, 5628 DBG_BLOCK_ID_TCAA_BY2 = 0x14, 5629 DBG_BLOCK_ID_TCCA_BY2 = 0x15, 5630 DBG_BLOCK_ID_MCC0_BY2 = 0x16, 5631 DBG_BLOCK_ID_MCC2_BY2 = 0x17, 5632 DBG_BLOCK_ID_SX0_BY2 = 0x18, 5633 DBG_BLOCK_ID_SX2_BY2 = 0x19, 5634 DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a, 5635 DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b, 5636 DBG_BLOCK_ID_PC0_BY2 = 0x1c, 5637 DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, 5638 DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e, 5639 DBG_BLOCK_ID_MCB_BY2 = 0x1f, 5640 DBG_BLOCK_ID_SCB0_BY2 = 0x20, 5641 DBG_BLOCK_ID_UNUSED13_BY2 = 0x21, 5642 DBG_BLOCK_ID_SCF0_BY2 = 0x22, 5643 DBG_BLOCK_ID_UNUSED15_BY2 = 0x23, 5644 DBG_BLOCK_ID_BCI0_BY2 = 0x24, 5645 DBG_BLOCK_ID_BCI2_BY2 = 0x25, 5646 DBG_BLOCK_ID_UNUSED17_BY2 = 0x26, 5647 DBG_BLOCK_ID_UNUSED19_BY2 = 0x27, 5648 DBG_BLOCK_ID_CB00_BY2 = 0x28, 5649 DBG_BLOCK_ID_CB02_BY2 = 0x29, 5650 DBG_BLOCK_ID_CB04_BY2 = 0x2a, 5651 DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b, 5652 DBG_BLOCK_ID_CB10_BY2 = 0x2c, 5653 DBG_BLOCK_ID_CB12_BY2 = 0x2d, 5654 DBG_BLOCK_ID_CB14_BY2 = 0x2e, 5655 DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f, 5656 DBG_BLOCK_ID_TCP0_BY2 = 0x30, 5657 DBG_BLOCK_ID_TCP2_BY2 = 0x31, 5658 DBG_BLOCK_ID_TCP4_BY2 = 0x32, 5659 DBG_BLOCK_ID_TCP6_BY2 = 0x33, 5660 DBG_BLOCK_ID_TCP8_BY2 = 0x34, 5661 DBG_BLOCK_ID_TCP10_BY2 = 0x35, 5662 DBG_BLOCK_ID_TCP12_BY2 = 0x36, 5663 DBG_BLOCK_ID_TCP14_BY2 = 0x37, 5664 DBG_BLOCK_ID_TCP16_BY2 = 0x38, 5665 DBG_BLOCK_ID_TCP18_BY2 = 0x39, 5666 DBG_BLOCK_ID_TCP20_BY2 = 0x3a, 5667 DBG_BLOCK_ID_TCP22_BY2 = 0x3b, 5668 DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, 5669 DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, 5670 DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, 5671 DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, 5672 DBG_BLOCK_ID_DB00_BY2 = 0x40, 5673 DBG_BLOCK_ID_DB02_BY2 = 0x41, 5674 DBG_BLOCK_ID_DB04_BY2 = 0x42, 5675 DBG_BLOCK_ID_UNUSED28_BY2 = 0x43, 5676 DBG_BLOCK_ID_DB10_BY2 = 0x44, 5677 DBG_BLOCK_ID_DB12_BY2 = 0x45, 5678 DBG_BLOCK_ID_DB14_BY2 = 0x46, 5679 DBG_BLOCK_ID_UNUSED31_BY2 = 0x47, 5680 DBG_BLOCK_ID_TCC0_BY2 = 0x48, 5681 DBG_BLOCK_ID_TCC2_BY2 = 0x49, 5682 DBG_BLOCK_ID_TCC4_BY2 = 0x4a, 5683 DBG_BLOCK_ID_TCC6_BY2 = 0x4b, 5684 DBG_BLOCK_ID_SPS00_BY2 = 0x4c, 5685 DBG_BLOCK_ID_SPS02_BY2 = 0x4d, 5686 DBG_BLOCK_ID_SPS11_BY2 = 0x4e, 5687 DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f, 5688 DBG_BLOCK_ID_TA00_BY2 = 0x50, 5689 DBG_BLOCK_ID_TA02_BY2 = 0x51, 5690 DBG_BLOCK_ID_TA04_BY2 = 0x52, 5691 DBG_BLOCK_ID_TA06_BY2 = 0x53, 5692 DBG_BLOCK_ID_TA08_BY2 = 0x54, 5693 DBG_BLOCK_ID_TA0A_BY2 = 0x55, 5694 DBG_BLOCK_ID_UNUSED35_BY2 = 0x56, 5695 DBG_BLOCK_ID_UNUSED37_BY2 = 0x57, 5696 DBG_BLOCK_ID_TA10_BY2 = 0x58, 5697 DBG_BLOCK_ID_TA12_BY2 = 0x59, 5698 DBG_BLOCK_ID_TA14_BY2 = 0x5a, 5699 DBG_BLOCK_ID_TA16_BY2 = 0x5b, 5700 DBG_BLOCK_ID_TA18_BY2 = 0x5c, 5701 DBG_BLOCK_ID_TA1A_BY2 = 0x5d, 5702 DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e, 5703 DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f, 5704 DBG_BLOCK_ID_TD00_BY2 = 0x60, 5705 DBG_BLOCK_ID_TD02_BY2 = 0x61, 5706 DBG_BLOCK_ID_TD04_BY2 = 0x62, 5707 DBG_BLOCK_ID_TD06_BY2 = 0x63, 5708 DBG_BLOCK_ID_TD08_BY2 = 0x64, 5709 DBG_BLOCK_ID_TD0A_BY2 = 0x65, 5710 DBG_BLOCK_ID_UNUSED43_BY2 = 0x66, 5711 DBG_BLOCK_ID_UNUSED45_BY2 = 0x67, 5712 DBG_BLOCK_ID_TD10_BY2 = 0x68, 5713 DBG_BLOCK_ID_TD12_BY2 = 0x69, 5714 DBG_BLOCK_ID_TD14_BY2 = 0x6a, 5715 DBG_BLOCK_ID_TD16_BY2 = 0x6b, 5716 DBG_BLOCK_ID_TD18_BY2 = 0x6c, 5717 DBG_BLOCK_ID_TD1A_BY2 = 0x6d, 5718 DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e, 5719 DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f, 5720 DBG_BLOCK_ID_MCD0_BY2 = 0x70, 5721 DBG_BLOCK_ID_MCD2_BY2 = 0x71, 5722 DBG_BLOCK_ID_MCD4_BY2 = 0x72, 5723 DBG_BLOCK_ID_UNUSED51_BY2 = 0x73, 5724} DebugBlockId_BY2; 5725typedef enum DebugBlockId_BY4 { 5726 DBG_BLOCK_ID_RESERVED_BY4 = 0x0, 5727 DBG_BLOCK_ID_CG_BY4 = 0x1, 5728 DBG_BLOCK_ID_CSC_BY4 = 0x2, 5729 DBG_BLOCK_ID_SQ_BY4 = 0x3, 5730 DBG_BLOCK_ID_DMA0_BY4 = 0x4, 5731 DBG_BLOCK_ID_SPIS_BY4 = 0x5, 5732 DBG_BLOCK_ID_CP0_BY4 = 0x6, 5733 DBG_BLOCK_ID_UVDU_BY4 = 0x7, 5734 DBG_BLOCK_ID_VGT0_BY4 = 0x8, 5735 DBG_BLOCK_ID_SCT0_BY4 = 0x9, 5736 DBG_BLOCK_ID_TCAA_BY4 = 0xa, 5737 DBG_BLOCK_ID_MCC0_BY4 = 0xb, 5738 DBG_BLOCK_ID_SX0_BY4 = 0xc, 5739 DBG_BLOCK_ID_UNUSED4_BY4 = 0xd, 5740 DBG_BLOCK_ID_PC0_BY4 = 0xe, 5741 DBG_BLOCK_ID_UNUSED10_BY4 = 0xf, 5742 DBG_BLOCK_ID_SCB0_BY4 = 0x10, 5743 DBG_BLOCK_ID_SCF0_BY4 = 0x11, 5744 DBG_BLOCK_ID_BCI0_BY4 = 0x12, 5745 DBG_BLOCK_ID_UNUSED17_BY4 = 0x13, 5746 DBG_BLOCK_ID_CB00_BY4 = 0x14, 5747 DBG_BLOCK_ID_CB04_BY4 = 0x15, 5748 DBG_BLOCK_ID_CB10_BY4 = 0x16, 5749 DBG_BLOCK_ID_CB14_BY4 = 0x17, 5750 DBG_BLOCK_ID_TCP0_BY4 = 0x18, 5751 DBG_BLOCK_ID_TCP4_BY4 = 0x19, 5752 DBG_BLOCK_ID_TCP8_BY4 = 0x1a, 5753 DBG_BLOCK_ID_TCP12_BY4 = 0x1b, 5754 DBG_BLOCK_ID_TCP16_BY4 = 0x1c, 5755 DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 5756 DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, 5757 DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, 5758 DBG_BLOCK_ID_DB_BY4 = 0x20, 5759 DBG_BLOCK_ID_DB04_BY4 = 0x21, 5760 DBG_BLOCK_ID_DB10_BY4 = 0x22, 5761 DBG_BLOCK_ID_DB14_BY4 = 0x23, 5762 DBG_BLOCK_ID_TCC0_BY4 = 0x24, 5763 DBG_BLOCK_ID_TCC4_BY4 = 0x25, 5764 DBG_BLOCK_ID_SPS00_BY4 = 0x26, 5765 DBG_BLOCK_ID_SPS11_BY4 = 0x27, 5766 DBG_BLOCK_ID_TA00_BY4 = 0x28, 5767 DBG_BLOCK_ID_TA04_BY4 = 0x29, 5768 DBG_BLOCK_ID_TA08_BY4 = 0x2a, 5769 DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b, 5770 DBG_BLOCK_ID_TA10_BY4 = 0x2c, 5771 DBG_BLOCK_ID_TA14_BY4 = 0x2d, 5772 DBG_BLOCK_ID_TA18_BY4 = 0x2e, 5773 DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f, 5774 DBG_BLOCK_ID_TD00_BY4 = 0x30, 5775 DBG_BLOCK_ID_TD04_BY4 = 0x31, 5776 DBG_BLOCK_ID_TD08_BY4 = 0x32, 5777 DBG_BLOCK_ID_UNUSED43_BY4 = 0x33, 5778 DBG_BLOCK_ID_TD10_BY4 = 0x34, 5779 DBG_BLOCK_ID_TD14_BY4 = 0x35, 5780 DBG_BLOCK_ID_TD18_BY4 = 0x36, 5781 DBG_BLOCK_ID_UNUSED47_BY4 = 0x37, 5782 DBG_BLOCK_ID_MCD0_BY4 = 0x38, 5783 DBG_BLOCK_ID_MCD4_BY4 = 0x39, 5784} DebugBlockId_BY4; 5785typedef enum DebugBlockId_BY8 { 5786 DBG_BLOCK_ID_RESERVED_BY8 = 0x0, 5787 DBG_BLOCK_ID_CSC_BY8 = 0x1, 5788 DBG_BLOCK_ID_DMA0_BY8 = 0x2, 5789 DBG_BLOCK_ID_CP0_BY8 = 0x3, 5790 DBG_BLOCK_ID_VGT0_BY8 = 0x4, 5791 DBG_BLOCK_ID_TCAA_BY8 = 0x5, 5792 DBG_BLOCK_ID_SX0_BY8 = 0x6, 5793 DBG_BLOCK_ID_PC0_BY8 = 0x7, 5794 DBG_BLOCK_ID_SCB0_BY8 = 0x8, 5795 DBG_BLOCK_ID_BCI0_BY8 = 0x9, 5796 DBG_BLOCK_ID_CB00_BY8 = 0xa, 5797 DBG_BLOCK_ID_CB10_BY8 = 0xb, 5798 DBG_BLOCK_ID_TCP0_BY8 = 0xc, 5799 DBG_BLOCK_ID_TCP8_BY8 = 0xd, 5800 DBG_BLOCK_ID_TCP16_BY8 = 0xe, 5801 DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, 5802 DBG_BLOCK_ID_DB00_BY8 = 0x10, 5803 DBG_BLOCK_ID_DB10_BY8 = 0x11, 5804 DBG_BLOCK_ID_TCC0_BY8 = 0x12, 5805 DBG_BLOCK_ID_SPS00_BY8 = 0x13, 5806 DBG_BLOCK_ID_TA00_BY8 = 0x14, 5807 DBG_BLOCK_ID_TA08_BY8 = 0x15, 5808 DBG_BLOCK_ID_TA10_BY8 = 0x16, 5809 DBG_BLOCK_ID_TA18_BY8 = 0x17, 5810 DBG_BLOCK_ID_TD00_BY8 = 0x18, 5811 DBG_BLOCK_ID_TD08_BY8 = 0x19, 5812 DBG_BLOCK_ID_TD10_BY8 = 0x1a, 5813 DBG_BLOCK_ID_TD18_BY8 = 0x1b, 5814 DBG_BLOCK_ID_MCD0_BY8 = 0x1c, 5815} DebugBlockId_BY8; 5816typedef enum DebugBlockId_BY16 { 5817 DBG_BLOCK_ID_RESERVED_BY16 = 0x0, 5818 DBG_BLOCK_ID_DMA0_BY16 = 0x1, 5819 DBG_BLOCK_ID_VGT0_BY16 = 0x2, 5820 DBG_BLOCK_ID_SX0_BY16 = 0x3, 5821 DBG_BLOCK_ID_SCB0_BY16 = 0x4, 5822 DBG_BLOCK_ID_CB00_BY16 = 0x5, 5823 DBG_BLOCK_ID_TCP0_BY16 = 0x6, 5824 DBG_BLOCK_ID_TCP16_BY16 = 0x7, 5825 DBG_BLOCK_ID_DB00_BY16 = 0x8, 5826 DBG_BLOCK_ID_TCC0_BY16 = 0x9, 5827 DBG_BLOCK_ID_TA00_BY16 = 0xa, 5828 DBG_BLOCK_ID_TA10_BY16 = 0xb, 5829 DBG_BLOCK_ID_TD00_BY16 = 0xc, 5830 DBG_BLOCK_ID_TD10_BY16 = 0xd, 5831 DBG_BLOCK_ID_MCD0_BY16 = 0xe, 5832} DebugBlockId_BY16; 5833typedef enum ColorTransform { 5834 DCC_CT_AUTO = 0x0, 5835 DCC_CT_NONE = 0x1, 5836 ABGR_TO_A_BG_G_RB = 0x2, 5837 BGRA_TO_BG_G_RB_A = 0x3, 5838} ColorTransform; 5839typedef enum CompareRef { 5840 REF_NEVER = 0x0, 5841 REF_LESS = 0x1, 5842 REF_EQUAL = 0x2, 5843 REF_LEQUAL = 0x3, 5844 REF_GREATER = 0x4, 5845 REF_NOTEQUAL = 0x5, 5846 REF_GEQUAL = 0x6, 5847 REF_ALWAYS = 0x7, 5848} CompareRef; 5849typedef enum ReadSize { 5850 READ_256_BITS = 0x0, 5851 READ_512_BITS = 0x1, 5852} ReadSize; 5853typedef enum DepthFormat { 5854 DEPTH_INVALID = 0x0, 5855 DEPTH_16 = 0x1, 5856 DEPTH_X8_24 = 0x2, 5857 DEPTH_8_24 = 0x3, 5858 DEPTH_X8_24_FLOAT = 0x4, 5859 DEPTH_8_24_FLOAT = 0x5, 5860 DEPTH_32_FLOAT = 0x6, 5861 DEPTH_X24_8_32_FLOAT = 0x7, 5862} DepthFormat; 5863typedef enum ZFormat { 5864 Z_INVALID = 0x0, 5865 Z_16 = 0x1, 5866 Z_24 = 0x2, 5867 Z_32_FLOAT = 0x3, 5868} ZFormat; 5869typedef enum StencilFormat { 5870 STENCIL_INVALID = 0x0, 5871 STENCIL_8 = 0x1, 5872} StencilFormat; 5873typedef enum CmaskMode { 5874 CMASK_CLEAR_NONE = 0x0, 5875 CMASK_CLEAR_ONE = 0x1, 5876 CMASK_CLEAR_ALL = 0x2, 5877 CMASK_ANY_EXPANDED = 0x3, 5878 CMASK_ALPHA0_FRAG1 = 0x4, 5879 CMASK_ALPHA0_FRAG2 = 0x5, 5880 CMASK_ALPHA0_FRAG4 = 0x6, 5881 CMASK_ALPHA0_FRAGS = 0x7, 5882 CMASK_ALPHA1_FRAG1 = 0x8, 5883 CMASK_ALPHA1_FRAG2 = 0x9, 5884 CMASK_ALPHA1_FRAG4 = 0xa, 5885 CMASK_ALPHA1_FRAGS = 0xb, 5886 CMASK_ALPHAX_FRAG1 = 0xc, 5887 CMASK_ALPHAX_FRAG2 = 0xd, 5888 CMASK_ALPHAX_FRAG4 = 0xe, 5889 CMASK_ALPHAX_FRAGS = 0xf, 5890} CmaskMode; 5891typedef enum QuadExportFormat { 5892 EXPORT_UNUSED = 0x0, 5893 EXPORT_32_R = 0x1, 5894 EXPORT_32_GR = 0x2, 5895 EXPORT_32_AR = 0x3, 5896 EXPORT_FP16_ABGR = 0x4, 5897 EXPORT_UNSIGNED16_ABGR = 0x5, 5898 EXPORT_SIGNED16_ABGR = 0x6, 5899 EXPORT_32_ABGR = 0x7, 5900} QuadExportFormat; 5901typedef enum QuadExportFormatOld { 5902 EXPORT_4P_32BPC_ABGR = 0x0, 5903 EXPORT_4P_16BPC_ABGR = 0x1, 5904 EXPORT_4P_32BPC_GR = 0x2, 5905 EXPORT_4P_32BPC_AR = 0x3, 5906 EXPORT_2P_32BPC_ABGR = 0x4, 5907 EXPORT_8P_32BPC_R = 0x5, 5908} QuadExportFormatOld; 5909typedef enum ColorFormat { 5910 COLOR_INVALID = 0x0, 5911 COLOR_8 = 0x1, 5912 COLOR_16 = 0x2, 5913 COLOR_8_8 = 0x3, 5914 COLOR_32 = 0x4, 5915 COLOR_16_16 = 0x5, 5916 COLOR_10_11_11 = 0x6, 5917 COLOR_11_11_10 = 0x7, 5918 COLOR_10_10_10_2 = 0x8, 5919 COLOR_2_10_10_10 = 0x9, 5920 COLOR_8_8_8_8 = 0xa, 5921 COLOR_32_32 = 0xb, 5922 COLOR_16_16_16_16 = 0xc, 5923 COLOR_RESERVED_13 = 0xd, 5924 COLOR_32_32_32_32 = 0xe, 5925 COLOR_RESERVED_15 = 0xf, 5926 COLOR_5_6_5 = 0x10, 5927 COLOR_1_5_5_5 = 0x11, 5928 COLOR_5_5_5_1 = 0x12, 5929 COLOR_4_4_4_4 = 0x13, 5930 COLOR_8_24 = 0x14, 5931 COLOR_24_8 = 0x15, 5932 COLOR_X24_8_32_FLOAT = 0x16, 5933 COLOR_RESERVED_23 = 0x17, 5934} ColorFormat; 5935typedef enum SurfaceFormat { 5936 FMT_INVALID = 0x0, 5937 FMT_8 = 0x1, 5938 FMT_16 = 0x2, 5939 FMT_8_8 = 0x3, 5940 FMT_32 = 0x4, 5941 FMT_16_16 = 0x5, 5942 FMT_10_11_11 = 0x6, 5943 FMT_11_11_10 = 0x7, 5944 FMT_10_10_10_2 = 0x8, 5945 FMT_2_10_10_10 = 0x9, 5946 FMT_8_8_8_8 = 0xa, 5947 FMT_32_32 = 0xb, 5948 FMT_16_16_16_16 = 0xc, 5949 FMT_32_32_32 = 0xd, 5950 FMT_32_32_32_32 = 0xe, 5951 FMT_RESERVED_4 = 0xf, 5952 FMT_5_6_5 = 0x10, 5953 FMT_1_5_5_5 = 0x11, 5954 FMT_5_5_5_1 = 0x12, 5955 FMT_4_4_4_4 = 0x13, 5956 FMT_8_24 = 0x14, 5957 FMT_24_8 = 0x15, 5958 FMT_X24_8_32_FLOAT = 0x16, 5959 FMT_RESERVED_33 = 0x17, 5960 FMT_11_11_10_FLOAT = 0x18, 5961 FMT_16_FLOAT = 0x19, 5962 FMT_32_FLOAT = 0x1a, 5963 FMT_16_16_FLOAT = 0x1b, 5964 FMT_8_24_FLOAT = 0x1c, 5965 FMT_24_8_FLOAT = 0x1d, 5966 FMT_32_32_FLOAT = 0x1e, 5967 FMT_10_11_11_FLOAT = 0x1f, 5968 FMT_16_16_16_16_FLOAT = 0x20, 5969 FMT_3_3_2 = 0x21, 5970 FMT_6_5_5 = 0x22, 5971 FMT_32_32_32_32_FLOAT = 0x23, 5972 FMT_RESERVED_36 = 0x24, 5973 FMT_1 = 0x25, 5974 FMT_1_REVERSED = 0x26, 5975 FMT_GB_GR = 0x27, 5976 FMT_BG_RG = 0x28, 5977 FMT_32_AS_8 = 0x29, 5978 FMT_32_AS_8_8 = 0x2a, 5979 FMT_5_9_9_9_SHAREDEXP = 0x2b, 5980 FMT_8_8_8 = 0x2c, 5981 FMT_16_16_16 = 0x2d, 5982 FMT_16_16_16_FLOAT = 0x2e, 5983 FMT_4_4 = 0x2f, 5984 FMT_32_32_32_FLOAT = 0x30, 5985 FMT_BC1 = 0x31, 5986 FMT_BC2 = 0x32, 5987 FMT_BC3 = 0x33, 5988 FMT_BC4 = 0x34, 5989 FMT_BC5 = 0x35, 5990 FMT_BC6 = 0x36, 5991 FMT_BC7 = 0x37, 5992 FMT_32_AS_32_32_32_32 = 0x38, 5993 FMT_APC3 = 0x39, 5994 FMT_APC4 = 0x3a, 5995 FMT_APC5 = 0x3b, 5996 FMT_APC6 = 0x3c, 5997 FMT_APC7 = 0x3d, 5998 FMT_CTX1 = 0x3e, 5999 FMT_RESERVED_63 = 0x3f, 6000} SurfaceFormat; 6001typedef enum BUF_DATA_FORMAT { 6002 BUF_DATA_FORMAT_INVALID = 0x0, 6003 BUF_DATA_FORMAT_8 = 0x1, 6004 BUF_DATA_FORMAT_16 = 0x2, 6005 BUF_DATA_FORMAT_8_8 = 0x3, 6006 BUF_DATA_FORMAT_32 = 0x4, 6007 BUF_DATA_FORMAT_16_16 = 0x5, 6008 BUF_DATA_FORMAT_10_11_11 = 0x6, 6009 BUF_DATA_FORMAT_11_11_10 = 0x7, 6010 BUF_DATA_FORMAT_10_10_10_2 = 0x8, 6011 BUF_DATA_FORMAT_2_10_10_10 = 0x9, 6012 BUF_DATA_FORMAT_8_8_8_8 = 0xa, 6013 BUF_DATA_FORMAT_32_32 = 0xb, 6014 BUF_DATA_FORMAT_16_16_16_16 = 0xc, 6015 BUF_DATA_FORMAT_32_32_32 = 0xd, 6016 BUF_DATA_FORMAT_32_32_32_32 = 0xe, 6017 BUF_DATA_FORMAT_RESERVED_15 = 0xf, 6018} BUF_DATA_FORMAT; 6019typedef enum IMG_DATA_FORMAT { 6020 IMG_DATA_FORMAT_INVALID = 0x0, 6021 IMG_DATA_FORMAT_8 = 0x1, 6022 IMG_DATA_FORMAT_16 = 0x2, 6023 IMG_DATA_FORMAT_8_8 = 0x3, 6024 IMG_DATA_FORMAT_32 = 0x4, 6025 IMG_DATA_FORMAT_16_16 = 0x5, 6026 IMG_DATA_FORMAT_10_11_11 = 0x6, 6027 IMG_DATA_FORMAT_11_11_10 = 0x7, 6028 IMG_DATA_FORMAT_10_10_10_2 = 0x8, 6029 IMG_DATA_FORMAT_2_10_10_10 = 0x9, 6030 IMG_DATA_FORMAT_8_8_8_8 = 0xa, 6031 IMG_DATA_FORMAT_32_32 = 0xb, 6032 IMG_DATA_FORMAT_16_16_16_16 = 0xc, 6033 IMG_DATA_FORMAT_32_32_32 = 0xd, 6034 IMG_DATA_FORMAT_32_32_32_32 = 0xe, 6035 IMG_DATA_FORMAT_RESERVED_15 = 0xf, 6036 IMG_DATA_FORMAT_5_6_5 = 0x10, 6037 IMG_DATA_FORMAT_1_5_5_5 = 0x11, 6038 IMG_DATA_FORMAT_5_5_5_1 = 0x12, 6039 IMG_DATA_FORMAT_4_4_4_4 = 0x13, 6040 IMG_DATA_FORMAT_8_24 = 0x14, 6041 IMG_DATA_FORMAT_24_8 = 0x15, 6042 IMG_DATA_FORMAT_X24_8_32 = 0x16, 6043 IMG_DATA_FORMAT_RESERVED_23 = 0x17, 6044 IMG_DATA_FORMAT_RESERVED_24 = 0x18, 6045 IMG_DATA_FORMAT_RESERVED_25 = 0x19, 6046 IMG_DATA_FORMAT_RESERVED_26 = 0x1a, 6047 IMG_DATA_FORMAT_RESERVED_27 = 0x1b, 6048 IMG_DATA_FORMAT_RESERVED_28 = 0x1c, 6049 IMG_DATA_FORMAT_RESERVED_29 = 0x1d, 6050 IMG_DATA_FORMAT_RESERVED_30 = 0x1e, 6051 IMG_DATA_FORMAT_RESERVED_31 = 0x1f, 6052 IMG_DATA_FORMAT_GB_GR = 0x20, 6053 IMG_DATA_FORMAT_BG_RG = 0x21, 6054 IMG_DATA_FORMAT_5_9_9_9 = 0x22, 6055 IMG_DATA_FORMAT_BC1 = 0x23, 6056 IMG_DATA_FORMAT_BC2 = 0x24, 6057 IMG_DATA_FORMAT_BC3 = 0x25, 6058 IMG_DATA_FORMAT_BC4 = 0x26, 6059 IMG_DATA_FORMAT_BC5 = 0x27, 6060 IMG_DATA_FORMAT_BC6 = 0x28, 6061 IMG_DATA_FORMAT_BC7 = 0x29, 6062 IMG_DATA_FORMAT_RESERVED_42 = 0x2a, 6063 IMG_DATA_FORMAT_RESERVED_43 = 0x2b, 6064 IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, 6065 IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, 6066 IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, 6067 IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, 6068 IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, 6069 IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, 6070 IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, 6071 IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, 6072 IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, 6073 IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, 6074 IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, 6075 IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, 6076 IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, 6077 IMG_DATA_FORMAT_4_4 = 0x39, 6078 IMG_DATA_FORMAT_6_5_5 = 0x3a, 6079 IMG_DATA_FORMAT_1 = 0x3b, 6080 IMG_DATA_FORMAT_1_REVERSED = 0x3c, 6081 IMG_DATA_FORMAT_32_AS_8 = 0x3d, 6082 IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, 6083 IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, 6084} IMG_DATA_FORMAT; 6085typedef enum BUF_NUM_FORMAT { 6086 BUF_NUM_FORMAT_UNORM = 0x0, 6087 BUF_NUM_FORMAT_SNORM = 0x1, 6088 BUF_NUM_FORMAT_USCALED = 0x2, 6089 BUF_NUM_FORMAT_SSCALED = 0x3, 6090 BUF_NUM_FORMAT_UINT = 0x4, 6091 BUF_NUM_FORMAT_SINT = 0x5, 6092 BUF_NUM_FORMAT_RESERVED_6 = 0x6, 6093 BUF_NUM_FORMAT_FLOAT = 0x7, 6094} BUF_NUM_FORMAT; 6095typedef enum IMG_NUM_FORMAT { 6096 IMG_NUM_FORMAT_UNORM = 0x0, 6097 IMG_NUM_FORMAT_SNORM = 0x1, 6098 IMG_NUM_FORMAT_USCALED = 0x2, 6099 IMG_NUM_FORMAT_SSCALED = 0x3, 6100 IMG_NUM_FORMAT_UINT = 0x4, 6101 IMG_NUM_FORMAT_SINT = 0x5, 6102 IMG_NUM_FORMAT_RESERVED_6 = 0x6, 6103 IMG_NUM_FORMAT_FLOAT = 0x7, 6104 IMG_NUM_FORMAT_RESERVED_8 = 0x8, 6105 IMG_NUM_FORMAT_SRGB = 0x9, 6106 IMG_NUM_FORMAT_RESERVED_10 = 0xa, 6107 IMG_NUM_FORMAT_RESERVED_11 = 0xb, 6108 IMG_NUM_FORMAT_RESERVED_12 = 0xc, 6109 IMG_NUM_FORMAT_RESERVED_13 = 0xd, 6110 IMG_NUM_FORMAT_RESERVED_14 = 0xe, 6111 IMG_NUM_FORMAT_RESERVED_15 = 0xf, 6112} IMG_NUM_FORMAT; 6113typedef enum TileType { 6114 ARRAY_COLOR_TILE = 0x0, 6115 ARRAY_DEPTH_TILE = 0x1, 6116} TileType; 6117typedef enum NonDispTilingOrder { 6118 ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, 6119 ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, 6120} NonDispTilingOrder; 6121typedef enum MicroTileMode { 6122 ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, 6123 ADDR_SURF_THIN_MICRO_TILING = 0x1, 6124 ADDR_SURF_DEPTH_MICRO_TILING = 0x2, 6125 ADDR_SURF_ROTATED_MICRO_TILING = 0x3, 6126 ADDR_SURF_THICK_MICRO_TILING = 0x4, 6127} MicroTileMode; 6128typedef enum TileSplit { 6129 ADDR_SURF_TILE_SPLIT_64B = 0x0, 6130 ADDR_SURF_TILE_SPLIT_128B = 0x1, 6131 ADDR_SURF_TILE_SPLIT_256B = 0x2, 6132 ADDR_SURF_TILE_SPLIT_512B = 0x3, 6133 ADDR_SURF_TILE_SPLIT_1KB = 0x4, 6134 ADDR_SURF_TILE_SPLIT_2KB = 0x5, 6135 ADDR_SURF_TILE_SPLIT_4KB = 0x6, 6136} TileSplit; 6137typedef enum SampleSplit { 6138 ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, 6139 ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, 6140 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, 6141 ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, 6142} SampleSplit; 6143typedef enum PipeConfig { 6144 ADDR_SURF_P2 = 0x0, 6145 ADDR_SURF_P2_RESERVED0 = 0x1, 6146 ADDR_SURF_P2_RESERVED1 = 0x2, 6147 ADDR_SURF_P2_RESERVED2 = 0x3, 6148 ADDR_SURF_P4_8x16 = 0x4, 6149 ADDR_SURF_P4_16x16 = 0x5, 6150 ADDR_SURF_P4_16x32 = 0x6, 6151 ADDR_SURF_P4_32x32 = 0x7, 6152 ADDR_SURF_P8_16x16_8x16 = 0x8, 6153 ADDR_SURF_P8_16x32_8x16 = 0x9, 6154 ADDR_SURF_P8_32x32_8x16 = 0xa, 6155 ADDR_SURF_P8_16x32_16x16 = 0xb, 6156 ADDR_SURF_P8_32x32_16x16 = 0xc, 6157 ADDR_SURF_P8_32x32_16x32 = 0xd, 6158 ADDR_SURF_P8_32x64_32x32 = 0xe, 6159 ADDR_SURF_P8_RESERVED0 = 0xf, 6160 ADDR_SURF_P16_32x32_8x16 = 0x10, 6161 ADDR_SURF_P16_32x32_16x16 = 0x11, 6162} PipeConfig; 6163typedef enum NumBanks { 6164 ADDR_SURF_2_BANK = 0x0, 6165 ADDR_SURF_4_BANK = 0x1, 6166 ADDR_SURF_8_BANK = 0x2, 6167 ADDR_SURF_16_BANK = 0x3, 6168} NumBanks; 6169typedef enum BankWidth { 6170 ADDR_SURF_BANK_WIDTH_1 = 0x0, 6171 ADDR_SURF_BANK_WIDTH_2 = 0x1, 6172 ADDR_SURF_BANK_WIDTH_4 = 0x2, 6173 ADDR_SURF_BANK_WIDTH_8 = 0x3, 6174} BankWidth; 6175typedef enum BankHeight { 6176 ADDR_SURF_BANK_HEIGHT_1 = 0x0, 6177 ADDR_SURF_BANK_HEIGHT_2 = 0x1, 6178 ADDR_SURF_BANK_HEIGHT_4 = 0x2, 6179 ADDR_SURF_BANK_HEIGHT_8 = 0x3, 6180} BankHeight; 6181typedef enum BankWidthHeight { 6182 ADDR_SURF_BANK_WH_1 = 0x0, 6183 ADDR_SURF_BANK_WH_2 = 0x1, 6184 ADDR_SURF_BANK_WH_4 = 0x2, 6185 ADDR_SURF_BANK_WH_8 = 0x3, 6186} BankWidthHeight; 6187typedef enum MacroTileAspect { 6188 ADDR_SURF_MACRO_ASPECT_1 = 0x0, 6189 ADDR_SURF_MACRO_ASPECT_2 = 0x1, 6190 ADDR_SURF_MACRO_ASPECT_4 = 0x2, 6191 ADDR_SURF_MACRO_ASPECT_8 = 0x3, 6192} MacroTileAspect; 6193typedef enum GATCL1RequestType { 6194 GATCL1_TYPE_NORMAL = 0x0, 6195 GATCL1_TYPE_SHOOTDOWN = 0x1, 6196 GATCL1_TYPE_BYPASS = 0x2, 6197} GATCL1RequestType; 6198typedef enum TCC_CACHE_POLICIES { 6199 TCC_CACHE_POLICY_LRU = 0x0, 6200 TCC_CACHE_POLICY_STREAM = 0x1, 6201} TCC_CACHE_POLICIES; 6202typedef enum MTYPE { 6203 MTYPE_NC_NV = 0x0, 6204 MTYPE_NC = 0x1, 6205 MTYPE_CC = 0x2, 6206 MTYPE_UC = 0x3, 6207} MTYPE; 6208typedef enum PERFMON_COUNTER_MODE { 6209 PERFMON_COUNTER_MODE_ACCUM = 0x0, 6210 PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, 6211 PERFMON_COUNTER_MODE_MAX = 0x2, 6212 PERFMON_COUNTER_MODE_DIRTY = 0x3, 6213 PERFMON_COUNTER_MODE_SAMPLE = 0x4, 6214 PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, 6215 PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, 6216 PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, 6217 PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, 6218 PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, 6219 PERFMON_COUNTER_MODE_RESERVED = 0xf, 6220} PERFMON_COUNTER_MODE; 6221typedef enum PERFMON_SPM_MODE { 6222 PERFMON_SPM_MODE_OFF = 0x0, 6223 PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, 6224 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, 6225 PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, 6226 PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, 6227 PERFMON_SPM_MODE_RESERVED_5 = 0x5, 6228 PERFMON_SPM_MODE_RESERVED_6 = 0x6, 6229 PERFMON_SPM_MODE_RESERVED_7 = 0x7, 6230 PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, 6231 PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, 6232 PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, 6233} PERFMON_SPM_MODE; 6234typedef enum SurfaceTiling { 6235 ARRAY_LINEAR = 0x0, 6236 ARRAY_TILED = 0x1, 6237} SurfaceTiling; 6238typedef enum SurfaceArray { 6239 ARRAY_1D = 0x0, 6240 ARRAY_2D = 0x1, 6241 ARRAY_3D = 0x2, 6242 ARRAY_3D_SLICE = 0x3, 6243} SurfaceArray; 6244typedef enum ColorArray { 6245 ARRAY_2D_ALT_COLOR = 0x0, 6246 ARRAY_2D_COLOR = 0x1, 6247 ARRAY_3D_SLICE_COLOR = 0x3, 6248} ColorArray; 6249typedef enum DepthArray { 6250 ARRAY_2D_ALT_DEPTH = 0x0, 6251 ARRAY_2D_DEPTH = 0x1, 6252} DepthArray; 6253typedef enum ENUM_NUM_SIMD_PER_CU { 6254 NUM_SIMD_PER_CU = 0x4, 6255} ENUM_NUM_SIMD_PER_CU; 6256typedef enum MEM_PWR_FORCE_CTRL { 6257 NO_FORCE_REQUEST = 0x0, 6258 FORCE_LIGHT_SLEEP_REQUEST = 0x1, 6259 FORCE_DEEP_SLEEP_REQUEST = 0x2, 6260 FORCE_SHUT_DOWN_REQUEST = 0x3, 6261} MEM_PWR_FORCE_CTRL; 6262typedef enum MEM_PWR_FORCE_CTRL2 { 6263 NO_FORCE_REQ = 0x0, 6264 FORCE_LIGHT_SLEEP_REQ = 0x1, 6265} MEM_PWR_FORCE_CTRL2; 6266typedef enum MEM_PWR_DIS_CTRL { 6267 ENABLE_MEM_PWR_CTRL = 0x0, 6268 DISABLE_MEM_PWR_CTRL = 0x1, 6269} MEM_PWR_DIS_CTRL; 6270typedef enum MEM_PWR_SEL_CTRL { 6271 DYNAMIC_SHUT_DOWN_ENABLE = 0x0, 6272 DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, 6273 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, 6274} MEM_PWR_SEL_CTRL; 6275typedef enum MEM_PWR_SEL_CTRL2 { 6276 DYNAMIC_DEEP_SLEEP_EN = 0x0, 6277 DYNAMIC_LIGHT_SLEEP_EN = 0x1, 6278} MEM_PWR_SEL_CTRL2; 6279typedef enum HPD_INT_CONTROL_ACK { 6280 HPD_INT_CONTROL_ACK_0 = 0x0, 6281 HPD_INT_CONTROL_ACK_1 = 0x1, 6282} HPD_INT_CONTROL_ACK; 6283typedef enum HPD_INT_CONTROL_POLARITY { 6284 HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0x0, 6285 HPD_INT_CONTROL_GEN_INT_ON_CON = 0x1, 6286} HPD_INT_CONTROL_POLARITY; 6287typedef enum HPD_INT_CONTROL_RX_INT_ACK { 6288 HPD_INT_CONTROL_RX_INT_ACK_0 = 0x0, 6289 HPD_INT_CONTROL_RX_INT_ACK_1 = 0x1, 6290} HPD_INT_CONTROL_RX_INT_ACK; 6291typedef enum DPDBG_EN { 6292 DPDBG_DISABLE = 0x0, 6293 DPDBG_ENABLE = 0x1, 6294} DPDBG_EN; 6295typedef enum DPDBG_INPUT_EN { 6296 DPDBG_INPUT_DISABLE = 0x0, 6297 DPDBG_INPUT_ENABLE = 0x1, 6298} DPDBG_INPUT_EN; 6299typedef enum DPDBG_ERROR_DETECTION_MODE { 6300 DPDBG_ERROR_DETECTION_MODE_CSC = 0x0, 6301 DPDBG_ERROR_DETECTION_MODE_RS_ENCODING = 0x1, 6302} DPDBG_ERROR_DETECTION_MODE; 6303typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK { 6304 DPDBG_FIFO_OVERFLOW_INT_DISABLE = 0x0, 6305 DPDBG_FIFO_OVERFLOW_INT_ENABLE = 0x1, 6306} DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK; 6307typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE { 6308 DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED = 0x0, 6309 DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED = 0x1, 6310} DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE; 6311typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK { 6312 DPDBG_FIFO_OVERFLOW_INT_NO_ACK = 0x0, 6313 DPDBG_FIFO_OVERFLOW_INT_CLEAR = 0x1, 6314} DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK; 6315typedef enum PM_ASSERT_RESET { 6316 PM_ASSERT_RESET_0 = 0x0, 6317 PM_ASSERT_RESET_1 = 0x1, 6318} PM_ASSERT_RESET; 6319typedef enum DAC_MUX_SELECT { 6320 DAC_MUX_SELECT_DACA = 0x0, 6321 DAC_MUX_SELECT_DACB = 0x1, 6322} DAC_MUX_SELECT; 6323typedef enum TMDS_DVO_MUX_SELECT { 6324 TMDS_DVO_MUX_SELECT_B = 0x0, 6325 TMDS_DVO_MUX_SELECT_G = 0x1, 6326 TMDS_DVO_MUX_SELECT_R = 0x2, 6327 TMDS_DVO_MUX_SELECT_RESERVED = 0x3, 6328} TMDS_DVO_MUX_SELECT; 6329typedef enum DACA_SOFT_RESET { 6330 DACA_SOFT_RESET_0 = 0x0, 6331 DACA_SOFT_RESET_1 = 0x1, 6332} DACA_SOFT_RESET; 6333typedef enum I2S0_SPDIF0_SOFT_RESET { 6334 I2S0_SPDIF0_SOFT_RESET_0 = 0x0, 6335 I2S0_SPDIF0_SOFT_RESET_1 = 0x1, 6336} I2S0_SPDIF0_SOFT_RESET; 6337typedef enum I2S1_SOFT_RESET { 6338 I2S1_SOFT_RESET_0 = 0x0, 6339 I2S1_SOFT_RESET_1 = 0x1, 6340} I2S1_SOFT_RESET; 6341typedef enum SPDIF1_SOFT_RESET { 6342 SPDIF1_SOFT_RESET_0 = 0x0, 6343 SPDIF1_SOFT_RESET_1 = 0x1, 6344} SPDIF1_SOFT_RESET; 6345typedef enum DB_CLK_SOFT_RESET { 6346 DB_CLK_SOFT_RESET_0 = 0x0, 6347 DB_CLK_SOFT_RESET_1 = 0x1, 6348} DB_CLK_SOFT_RESET; 6349typedef enum FMT0_SOFT_RESET { 6350 FMT0_SOFT_RESET_0 = 0x0, 6351 FMT0_SOFT_RESET_1 = 0x1, 6352} FMT0_SOFT_RESET; 6353typedef enum FMT1_SOFT_RESET { 6354 FMT1_SOFT_RESET_0 = 0x0, 6355 FMT1_SOFT_RESET_1 = 0x1, 6356} FMT1_SOFT_RESET; 6357typedef enum FMT2_SOFT_RESET { 6358 FMT2_SOFT_RESET_0 = 0x0, 6359 FMT2_SOFT_RESET_1 = 0x1, 6360} FMT2_SOFT_RESET; 6361typedef enum FMT3_SOFT_RESET { 6362 FMT3_SOFT_RESET_0 = 0x0, 6363 FMT3_SOFT_RESET_1 = 0x1, 6364} FMT3_SOFT_RESET; 6365typedef enum FMT4_SOFT_RESET { 6366 FMT4_SOFT_RESET_0 = 0x0, 6367 FMT4_SOFT_RESET_1 = 0x1, 6368} FMT4_SOFT_RESET; 6369typedef enum FMT5_SOFT_RESET { 6370 FMT5_SOFT_RESET_0 = 0x0, 6371 FMT5_SOFT_RESET_1 = 0x1, 6372} FMT5_SOFT_RESET; 6373typedef enum MVP_SOFT_RESET { 6374 MVP_SOFT_RESET_0 = 0x0, 6375 MVP_SOFT_RESET_1 = 0x1, 6376} MVP_SOFT_RESET; 6377typedef enum ABM_SOFT_RESET { 6378 ABM_SOFT_RESET_0 = 0x0, 6379 ABM_SOFT_RESET_1 = 0x1, 6380} ABM_SOFT_RESET; 6381typedef enum DVO_SOFT_RESET { 6382 DVO_SOFT_RESET_0 = 0x0, 6383 DVO_SOFT_RESET_1 = 0x1, 6384} DVO_SOFT_RESET; 6385typedef enum DIGA_FE_SOFT_RESET { 6386 DIGA_FE_SOFT_RESET_0 = 0x0, 6387 DIGA_FE_SOFT_RESET_1 = 0x1, 6388} DIGA_FE_SOFT_RESET; 6389typedef enum DIGA_BE_SOFT_RESET { 6390 DIGA_BE_SOFT_RESET_0 = 0x0, 6391 DIGA_BE_SOFT_RESET_1 = 0x1, 6392} DIGA_BE_SOFT_RESET; 6393typedef enum DIGB_FE_SOFT_RESET { 6394 DIGB_FE_SOFT_RESET_0 = 0x0, 6395 DIGB_FE_SOFT_RESET_1 = 0x1, 6396} DIGB_FE_SOFT_RESET; 6397typedef enum DIGB_BE_SOFT_RESET { 6398 DIGB_BE_SOFT_RESET_0 = 0x0, 6399 DIGB_BE_SOFT_RESET_1 = 0x1, 6400} DIGB_BE_SOFT_RESET; 6401typedef enum DIGC_FE_SOFT_RESET { 6402 DIGC_FE_SOFT_RESET_0 = 0x0, 6403 DIGC_FE_SOFT_RESET_1 = 0x1, 6404} DIGC_FE_SOFT_RESET; 6405typedef enum DIGC_BE_SOFT_RESET { 6406 DIGC_BE_SOFT_RESET_0 = 0x0, 6407 DIGC_BE_SOFT_RESET_1 = 0x1, 6408} DIGC_BE_SOFT_RESET; 6409typedef enum DIGD_FE_SOFT_RESET { 6410 DIGD_FE_SOFT_RESET_0 = 0x0, 6411 DIGD_FE_SOFT_RESET_1 = 0x1, 6412} DIGD_FE_SOFT_RESET; 6413typedef enum DIGD_BE_SOFT_RESET { 6414 DIGD_BE_SOFT_RESET_0 = 0x0, 6415 DIGD_BE_SOFT_RESET_1 = 0x1, 6416} DIGD_BE_SOFT_RESET; 6417typedef enum DIGE_FE_SOFT_RESET { 6418 DIGE_FE_SOFT_RESET_0 = 0x0, 6419 DIGE_FE_SOFT_RESET_1 = 0x1, 6420} DIGE_FE_SOFT_RESET; 6421typedef enum DIGE_BE_SOFT_RESET { 6422 DIGE_BE_SOFT_RESET_0 = 0x0, 6423 DIGE_BE_SOFT_RESET_1 = 0x1, 6424} DIGE_BE_SOFT_RESET; 6425typedef enum DIGF_FE_SOFT_RESET { 6426 DIGF_FE_SOFT_RESET_0 = 0x0, 6427 DIGF_FE_SOFT_RESET_1 = 0x1, 6428} DIGF_FE_SOFT_RESET; 6429typedef enum DIGF_BE_SOFT_RESET { 6430 DIGF_BE_SOFT_RESET_0 = 0x0, 6431 DIGF_BE_SOFT_RESET_1 = 0x1, 6432} DIGF_BE_SOFT_RESET; 6433typedef enum DIGG_FE_SOFT_RESET { 6434 DIGG_FE_SOFT_RESET_0 = 0x0, 6435 DIGG_FE_SOFT_RESET_1 = 0x1, 6436} DIGG_FE_SOFT_RESET; 6437typedef enum DIGG_BE_SOFT_RESET { 6438 DIGG_BE_SOFT_RESET_0 = 0x0, 6439 DIGG_BE_SOFT_RESET_1 = 0x1, 6440} DIGG_BE_SOFT_RESET; 6441typedef enum DPDBG_SOFT_RESET { 6442 DPDBG_SOFT_RESET_0 = 0x0, 6443 DPDBG_SOFT_RESET_1 = 0x1, 6444} DPDBG_SOFT_RESET; 6445typedef enum DIGLPA_FE_SOFT_RESET { 6446 DIGLPA_FE_SOFT_RESET_0 = 0x0, 6447 DIGLPA_FE_SOFT_RESET_1 = 0x1, 6448} DIGLPA_FE_SOFT_RESET; 6449typedef enum DIGLPA_BE_SOFT_RESET { 6450 DIGLPA_BE_SOFT_RESET_0 = 0x0, 6451 DIGLPA_BE_SOFT_RESET_1 = 0x1, 6452} DIGLPA_BE_SOFT_RESET; 6453typedef enum DIGLPB_FE_SOFT_RESET { 6454 DIGLPB_FE_SOFT_RESET_0 = 0x0, 6455 DIGLPB_FE_SOFT_RESET_1 = 0x1, 6456} DIGLPB_FE_SOFT_RESET; 6457typedef enum DIGLPB_BE_SOFT_RESET { 6458 DIGLPB_BE_SOFT_RESET_0 = 0x0, 6459 DIGLPB_BE_SOFT_RESET_1 = 0x1, 6460} DIGLPB_BE_SOFT_RESET; 6461typedef enum GENERICA_STEREOSYNC_SEL { 6462 GENERICA_STEREOSYNC_SEL_D1 = 0x0, 6463 GENERICA_STEREOSYNC_SEL_D2 = 0x1, 6464 GENERICA_STEREOSYNC_SEL_D3 = 0x2, 6465 GENERICA_STEREOSYNC_SEL_D4 = 0x3, 6466 GENERICA_STEREOSYNC_SEL_D5 = 0x4, 6467 GENERICA_STEREOSYNC_SEL_D6 = 0x5, 6468 GENERICA_STEREOSYNC_SEL_RESERVED = 0x6, 6469} GENERICA_STEREOSYNC_SEL; 6470typedef enum GENERICB_STEREOSYNC_SEL { 6471 GENERICB_STEREOSYNC_SEL_D1 = 0x0, 6472 GENERICB_STEREOSYNC_SEL_D2 = 0x1, 6473 GENERICB_STEREOSYNC_SEL_D3 = 0x2, 6474 GENERICB_STEREOSYNC_SEL_D4 = 0x3, 6475 GENERICB_STEREOSYNC_SEL_D5 = 0x4, 6476 GENERICB_STEREOSYNC_SEL_D6 = 0x5, 6477 GENERICB_STEREOSYNC_SEL_RESERVED = 0x6, 6478} GENERICB_STEREOSYNC_SEL; 6479typedef enum DCO_DBG_BLOCK_SEL { 6480 DCO_DBG_BLOCK_SEL_DCO = 0x0, 6481 DCO_DBG_BLOCK_SEL_ABM = 0x1, 6482 DCO_DBG_BLOCK_SEL_DVO = 0x2, 6483 DCO_DBG_BLOCK_SEL_DAC = 0x3, 6484 DCO_DBG_BLOCK_SEL_MVP = 0x4, 6485 DCO_DBG_BLOCK_SEL_FMT0 = 0x5, 6486 DCO_DBG_BLOCK_SEL_FMT1 = 0x6, 6487 DCO_DBG_BLOCK_SEL_FMT2 = 0x7, 6488 DCO_DBG_BLOCK_SEL_FMT3 = 0x8, 6489 DCO_DBG_BLOCK_SEL_FMT4 = 0x9, 6490 DCO_DBG_BLOCK_SEL_FMT5 = 0xa, 6491 DCO_DBG_BLOCK_SEL_DIGFE_A = 0xb, 6492 DCO_DBG_BLOCK_SEL_DIGFE_B = 0xc, 6493 DCO_DBG_BLOCK_SEL_DIGFE_C = 0xd, 6494 DCO_DBG_BLOCK_SEL_DIGFE_D = 0xe, 6495 DCO_DBG_BLOCK_SEL_DIGFE_E = 0xf, 6496 DCO_DBG_BLOCK_SEL_DIGFE_F = 0x10, 6497 DCO_DBG_BLOCK_SEL_DIGFE_G = 0x11, 6498 DCO_DBG_BLOCK_SEL_DIGA = 0x12, 6499 DCO_DBG_BLOCK_SEL_DIGB = 0x13, 6500 DCO_DBG_BLOCK_SEL_DIGC = 0x14, 6501 DCO_DBG_BLOCK_SEL_DIGD = 0x15, 6502 DCO_DBG_BLOCK_SEL_DIGE = 0x16, 6503 DCO_DBG_BLOCK_SEL_DIGF = 0x17, 6504 DCO_DBG_BLOCK_SEL_DIGG = 0x18, 6505 DCO_DBG_BLOCK_SEL_DPFE_A = 0x19, 6506 DCO_DBG_BLOCK_SEL_DPFE_B = 0x1a, 6507 DCO_DBG_BLOCK_SEL_DPFE_C = 0x1b, 6508 DCO_DBG_BLOCK_SEL_DPFE_D = 0x1c, 6509 DCO_DBG_BLOCK_SEL_DPFE_E = 0x1d, 6510 DCO_DBG_BLOCK_SEL_DPFE_F = 0x1e, 6511 DCO_DBG_BLOCK_SEL_DPFE_G = 0x1f, 6512 DCO_DBG_BLOCK_SEL_DPA = 0x20, 6513 DCO_DBG_BLOCK_SEL_DPB = 0x21, 6514 DCO_DBG_BLOCK_SEL_DPC = 0x22, 6515 DCO_DBG_BLOCK_SEL_DPD = 0x23, 6516 DCO_DBG_BLOCK_SEL_DPE = 0x24, 6517 DCO_DBG_BLOCK_SEL_DPF = 0x25, 6518 DCO_DBG_BLOCK_SEL_DPG = 0x26, 6519 DCO_DBG_BLOCK_SEL_AUX0 = 0x27, 6520 DCO_DBG_BLOCK_SEL_AUX1 = 0x28, 6521 DCO_DBG_BLOCK_SEL_AUX2 = 0x29, 6522 DCO_DBG_BLOCK_SEL_AUX3 = 0x2a, 6523 DCO_DBG_BLOCK_SEL_AUX4 = 0x2b, 6524 DCO_DBG_BLOCK_SEL_AUX5 = 0x2c, 6525 DCO_DBG_BLOCK_SEL_PERFMON_DCO = 0x2d, 6526 DCO_DBG_BLOCK_SEL_AUDIO_OUT = 0x2e, 6527 DCO_DBG_BLOCK_SEL_DIGLPFEA = 0x2f, 6528 DCO_DBG_BLOCK_SEL_DIGLPFEB = 0x30, 6529 DCO_DBG_BLOCK_SEL_DIGLPA = 0x31, 6530 DCO_DBG_BLOCK_SEL_DIGLPB = 0x32, 6531 DCO_DBG_BLOCK_SEL_DPLPFEA = 0x33, 6532 DCO_DBG_BLOCK_SEL_DPLPFEB = 0x34, 6533 DCO_DBG_BLOCK_SEL_DPLPA = 0x35, 6534 DCO_DBG_BLOCK_SEL_DPLPB = 0x36, 6535} DCO_DBG_BLOCK_SEL; 6536typedef enum DCO_DBG_CLOCK_SEL { 6537 DCO_DBG_CLOCK_SEL_DISPCLK = 0x0, 6538 DCO_DBG_CLOCK_SEL_SCLK = 0x1, 6539 DCO_DBG_CLOCK_SEL_MVPCLK = 0x2, 6540 DCO_DBG_CLOCK_SEL_DVOCLK = 0x3, 6541 DCO_DBG_CLOCK_SEL_DACCLK = 0x4, 6542 DCO_DBG_CLOCK_SEL_REFCLK = 0x5, 6543 DCO_DBG_CLOCK_SEL_SYMCLKA = 0x6, 6544 DCO_DBG_CLOCK_SEL_SYMCLKB = 0x7, 6545 DCO_DBG_CLOCK_SEL_SYMCLKC = 0x8, 6546 DCO_DBG_CLOCK_SEL_SYMCLKD = 0x9, 6547 DCO_DBG_CLOCK_SEL_SYMCLKE = 0xa, 6548 DCO_DBG_CLOCK_SEL_SYMCLKF = 0xb, 6549 DCO_DBG_CLOCK_SEL_SYMCLKG = 0xc, 6550 DCO_DBG_CLOCK_SEL_RESERVED = 0xd, 6551 DCO_DBG_CLOCK_SEL_AM0CLK = 0xe, 6552 DCO_DBG_CLOCK_SEL_AM1CLK = 0xf, 6553 DCO_DBG_CLOCK_SEL_AM2CLK = 0x10, 6554 DCO_DBG_CLOCK_SEL_SYMCLKLPA = 0x11, 6555 DCO_DBG_CLOCK_SEL_SYMCLKLPB = 0x12, 6556} DCO_DBG_CLOCK_SEL; 6557typedef enum DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE { 6558 DCO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0x0, 6559 DCO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 0x1, 6560} DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE; 6561typedef enum FMT420_MEMORY_SOURCE_SEL { 6562 FMT420_MEMORY_SOURCE_SEL_FMT0 = 0x0, 6563 FMT420_MEMORY_SOURCE_SEL_FMT1 = 0x1, 6564 FMT420_MEMORY_SOURCE_SEL_FMT2 = 0x2, 6565 FMT420_MEMORY_SOURCE_SEL_FMT3 = 0x3, 6566 FMT420_MEMORY_SOURCE_SEL_FMT4 = 0x4, 6567 FMT420_MEMORY_SOURCE_SEL_FMT5 = 0x5, 6568 FMT420_MEMORY_SOURCE_SEL_FMT_RESERVED = 0x6, 6569} FMT420_MEMORY_SOURCE_SEL; 6570typedef enum DOUT_I2C_CONTROL_GO { 6571 DOUT_I2C_CONTROL_STOP_TRANSFER = 0x0, 6572 DOUT_I2C_CONTROL_START_TRANSFER = 0x1, 6573} DOUT_I2C_CONTROL_GO; 6574typedef enum DOUT_I2C_CONTROL_SOFT_RESET { 6575 DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0x0, 6576 DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 0x1, 6577} DOUT_I2C_CONTROL_SOFT_RESET; 6578typedef enum DOUT_I2C_CONTROL_SEND_RESET { 6579 DOUT_I2C_CONTROL__NOT_SEND_RESET = 0x0, 6580 DOUT_I2C_CONTROL__SEND_RESET = 0x1, 6581} DOUT_I2C_CONTROL_SEND_RESET; 6582typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET { 6583 DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0x0, 6584 DOUT_I2C_CONTROL_RESET_SW_STATUS = 0x1, 6585} DOUT_I2C_CONTROL_SW_STATUS_RESET; 6586typedef enum DOUT_I2C_CONTROL_DDC_SELECT { 6587 DOUT_I2C_CONTROL_SELECT_DDC1 = 0x0, 6588 DOUT_I2C_CONTROL_SELECT_DDC2 = 0x1, 6589 DOUT_I2C_CONTROL_SELECT_DDC3 = 0x2, 6590 DOUT_I2C_CONTROL_SELECT_DDC4 = 0x3, 6591 DOUT_I2C_CONTROL_SELECT_DDC5 = 0x4, 6592 DOUT_I2C_CONTROL_SELECT_DDC6 = 0x5, 6593 DOUT_I2C_CONTROL_SELECT_DDCVGA = 0x6, 6594} DOUT_I2C_CONTROL_DDC_SELECT; 6595typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT { 6596 DOUT_I2C_CONTROL_TRANS0 = 0x0, 6597 DOUT_I2C_CONTROL_TRANS0_TRANS1 = 0x1, 6598 DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 0x2, 6599 DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 0x3, 6600} DOUT_I2C_CONTROL_TRANSACTION_COUNT; 6601typedef enum DOUT_I2C_CONTROL_DBG_REF_SEL { 6602 DOUT_I2C_CONTROL_NORMAL_DEBUG = 0x0, 6603 DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 0x1, 6604} DOUT_I2C_CONTROL_DBG_REF_SEL; 6605typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY { 6606 DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0x0, 6607 DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 0x1, 6608 DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 0x2, 6609 DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 0x3, 6610} DOUT_I2C_ARBITRATION_SW_PRIORITY; 6611typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO { 6612 DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0x0, 6613 DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 0x1, 6614} DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO; 6615typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER { 6616 DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0x0, 6617 DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 0x1, 6618} DOUT_I2C_ARBITRATION_ABORT_XFER; 6619typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ { 6620 DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0x0, 6621 DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 0x1, 6622} DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ; 6623typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG { 6624 DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0x0, 6625 DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 0x1, 6626} DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG; 6627typedef enum DOUT_I2C_ACK { 6628 DOUT_I2C_NO_ACK = 0x0, 6629 DOUT_I2C_ACK_TO_CLEAN = 0x1, 6630} DOUT_I2C_ACK; 6631typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD { 6632 DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0x0, 6633 DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE= 0x1, 6634 DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE= 0x2, 6635 DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE= 0x3, 6636} DOUT_I2C_DDC_SPEED_THRESHOLD; 6637typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN { 6638 DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR= 0x0, 6639 DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 0x1, 6640} DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN; 6641typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL { 6642 DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0x0, 6643 DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 0x1, 6644} DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL; 6645typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE { 6646 DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0x0, 6647 DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 0x1, 6648} DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE; 6649typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN { 6650 DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR= 0x0, 6651 DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 0x1, 6652} DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN; 6653typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK { 6654 DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0x0, 6655 DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 0x1, 6656} DOUT_I2C_TRANSACTION_STOP_ON_NACK; 6657typedef enum DOUT_I2C_DATA_INDEX_WRITE { 6658 DOUT_I2C_DATA__NOT_INDEX_WRITE = 0x0, 6659 DOUT_I2C_DATA__INDEX_WRITE = 0x1, 6660} DOUT_I2C_DATA_INDEX_WRITE; 6661typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET { 6662 DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION= 0x0, 6663 DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION= 0x1, 6664} DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET; 6665typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE { 6666 DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0x0, 6667 DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 0x1, 6668} DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE; 6669typedef enum BLNDV_CONTROL_BLND_MODE { 6670 BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x0, 6671 BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 0x1, 6672 BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x2, 6673 BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x3, 6674} BLNDV_CONTROL_BLND_MODE; 6675typedef enum BLNDV_CONTROL_BLND_STEREO_TYPE { 6676 BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO= 0x0, 6677 BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO= 0x1, 6678 BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO= 0x2, 6679 BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED = 0x3, 6680} BLNDV_CONTROL_BLND_STEREO_TYPE; 6681typedef enum BLNDV_CONTROL_BLND_STEREO_POLARITY { 6682 BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW = 0x0, 6683 BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH = 0x1, 6684} BLNDV_CONTROL_BLND_STEREO_POLARITY; 6685typedef enum BLNDV_CONTROL_BLND_FEEDTHROUGH_EN { 6686 BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0x0, 6687 BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 0x1, 6688} BLNDV_CONTROL_BLND_FEEDTHROUGH_EN; 6689typedef enum BLNDV_CONTROL_BLND_ALPHA_MODE { 6690 BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA= 0x0, 6691 BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN= 0x1, 6692 BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x2, 6693 BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED = 0x3, 6694} BLNDV_CONTROL_BLND_ALPHA_MODE; 6695typedef enum BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY { 6696 BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE = 0x0, 6697 BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE = 0x1, 6698} BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY; 6699typedef enum BLNDV_CONTROL_BLND_MULTIPLIED_MODE { 6700 BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x0, 6701 BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 0x1, 6702} BLNDV_CONTROL_BLND_MULTIPLIED_MODE; 6703typedef enum BLNDV_SM_CONTROL2_SM_MODE { 6704 BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0x0, 6705 BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x2, 6706 BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x4, 6707 BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING= 0x6, 6708} BLNDV_SM_CONTROL2_SM_MODE; 6709typedef enum BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE { 6710 BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x0, 6711 BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x1, 6712} BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE; 6713typedef enum BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE { 6714 BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x0, 6715 BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x1, 6716} BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE; 6717typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL { 6718 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE= 0x0, 6719 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED= 0x1, 6720 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW= 0x2, 6721 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH= 0x3, 6722} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL; 6723typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL { 6724 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x0, 6725 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x1, 6726 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW= 0x2, 6727 BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH= 0x3, 6728} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL; 6729typedef enum BLNDV_CONTROL2_PTI_ENABLE { 6730 BLNDV_CONTROL2_PTI_ENABLE_FALSE = 0x0, 6731 BLNDV_CONTROL2_PTI_ENABLE_TRUE = 0x1, 6732} BLNDV_CONTROL2_PTI_ENABLE; 6733typedef enum BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN { 6734 BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x0, 6735 BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x1, 6736} BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN; 6737typedef enum BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN { 6738 BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x0, 6739 BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x1, 6740} BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN; 6741typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK { 6742 BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE= 0x0, 6743 BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE= 0x1, 6744} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK; 6745typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK { 6746 BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE= 0x0, 6747 BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE= 0x1, 6748} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK; 6749typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK { 6750 BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE= 0x0, 6751 BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE= 0x1, 6752} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK; 6753typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK { 6754 BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE= 0x0, 6755 BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE= 0x1, 6756} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; 6757typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK { 6758 BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE= 0x0, 6759 BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE= 0x1, 6760} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK; 6761typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK { 6762 BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE= 0x0, 6763 BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE= 0x1, 6764} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK; 6765typedef enum BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK { 6766 BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x0, 6767 BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x1, 6768} BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK; 6769typedef enum BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK { 6770 BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE= 0x0, 6771 BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x1, 6772} BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK; 6773typedef enum BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE { 6774 BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE= 0x0, 6775 BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x1, 6776} BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE; 6777typedef enum BLNDV_DEBUG_BLND_CNV_MUX_SELECT { 6778 BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0x0, 6779 BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 0x1, 6780} BLNDV_DEBUG_BLND_CNV_MUX_SELECT; 6781typedef enum BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN { 6782 BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE= 0x0, 6783 BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE= 0x1, 6784} BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN; 6785typedef enum DPCSTX_DBG_CFGCLK_SEL { 6786 DPCSTX_DBG_CFGCLK_SEL_DC_DPCS_INF = 0x0, 6787 DPCSTX_DBG_CFGCLK_SEL_DPCS_BPHY_INF = 0x1, 6788 DPCSTX_DBG_CFGCLK_SEL_CBUS_SLAVE = 0x2, 6789 DPCSTX_DBG_CFGCLK_SEL_CBUS_MASTER = 0x3, 6790} DPCSTX_DBG_CFGCLK_SEL; 6791typedef enum DPCSTX_TX_SYMCLK_SEL { 6792 DPCSTX_DBG_TX_SYMCLK_SEL_IN0 = 0x0, 6793 DPCSTX_DBG_TX_SYMCLK_SEL_IN1 = 0x1, 6794 DPCSTX_DBG_TX_SYMCLK_SEL_FIFO_WR = 0x2, 6795} DPCSTX_TX_SYMCLK_SEL; 6796typedef enum DPCSTX_TX_SYMCLK_DIV2_SEL { 6797 DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT0 = 0x0, 6798 DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT1 = 0x1, 6799 DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT2 = 0x2, 6800 DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT3 = 0x3, 6801 DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_FIFO_RD = 0x4, 6802 DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_INT = 0x5, 6803} DPCSTX_TX_SYMCLK_DIV2_SEL; 6804typedef enum DPCSTX_DBG_CLOCK_SEL { 6805 DPCSTX_DBG_CLOCK_SEL_DC_CFGCLK = 0x0, 6806 DPCSTX_DBG_CLOCK_SEL_PHY_CFGCLK = 0x1, 6807 DPCSTX_DBG_CLOCK_SEL_TXSYMCLK = 0x2, 6808} DPCSTX_DBG_CLOCK_SEL; 6809typedef enum DPCSTX_DVI_LINK_MODE { 6810 DPCSTX_DVI_LINK_MODE_NORMAL = 0x0, 6811 DPCSTX_DVI_LINK_MODE_DUAL_LINK_MASTER = 0x1, 6812 DPCSTX_DVI_LINK_MODE_DUAL_LINK_SLAVER = 0x2, 6813} DPCSTX_DVI_LINK_MODE; 6814 6815#endif /* DCE_11_2_ENUM_H */ 6816