1/* $NetBSD: athub_1_0_sh_mask.h,v 1.2 2021/12/18 23:45:08 riastradh Exp $ */ 2 3/* 4 * Copyright (C) 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#ifndef _athub_1_0_SH_MASK_HEADER 24#define _athub_1_0_SH_MASK_HEADER 25 26 27// addressBlock: athub_atsdec 28//ATC_ATS_CNTL 29#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0 30#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1 31#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2 32#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8 33#define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER__SHIFT 0x14 34#define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER__SHIFT 0x15 35#define ATC_ATS_CNTL__TRANS_EXE_RETURN__SHIFT 0x16 36#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L 37#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L 38#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L 39#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003F00L 40#define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER_MASK 0x00100000L 41#define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER_MASK 0x00200000L 42#define ATC_ATS_CNTL__TRANS_EXE_RETURN_MASK 0x00C00000L 43//ATC_ATS_STATUS 44#define ATC_ATS_STATUS__BUSY__SHIFT 0x0 45#define ATC_ATS_STATUS__CRASHED__SHIFT 0x1 46#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2 47#define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x3 48#define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x6 49#define ATC_ATS_STATUS__BUSY_MASK 0x00000001L 50#define ATC_ATS_STATUS__CRASHED_MASK 0x00000002L 51#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x00000004L 52#define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING_MASK 0x00000038L 53#define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING_MASK 0x000001C0L 54//ATC_ATS_FAULT_CNTL 55#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0 56#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa 57#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14 58#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x000001FFL 59#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x0007FC00L 60#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x1FF00000L 61//ATC_ATS_FAULT_STATUS_INFO 62#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0 63#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa 64#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf 65#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10 66#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11 67#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12 68#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13 69#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18 70#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x000001FFL 71#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x00007C00L 72#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x00008000L 73#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x00010000L 74#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x00020000L 75#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x00040000L 76#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0x00F80000L 77#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0x0F000000L 78//ATC_ATS_FAULT_STATUS_ADDR 79#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0 80#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xFFFFFFFFL 81//ATC_ATS_DEFAULT_PAGE_LOW 82#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0 83#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xFFFFFFFFL 84//ATC_TRANS_FAULT_RSPCNTRL 85#define ATC_TRANS_FAULT_RSPCNTRL__VMID0__SHIFT 0x0 86#define ATC_TRANS_FAULT_RSPCNTRL__VMID1__SHIFT 0x1 87#define ATC_TRANS_FAULT_RSPCNTRL__VMID2__SHIFT 0x2 88#define ATC_TRANS_FAULT_RSPCNTRL__VMID3__SHIFT 0x3 89#define ATC_TRANS_FAULT_RSPCNTRL__VMID4__SHIFT 0x4 90#define ATC_TRANS_FAULT_RSPCNTRL__VMID5__SHIFT 0x5 91#define ATC_TRANS_FAULT_RSPCNTRL__VMID6__SHIFT 0x6 92#define ATC_TRANS_FAULT_RSPCNTRL__VMID7__SHIFT 0x7 93#define ATC_TRANS_FAULT_RSPCNTRL__VMID8__SHIFT 0x8 94#define ATC_TRANS_FAULT_RSPCNTRL__VMID9__SHIFT 0x9 95#define ATC_TRANS_FAULT_RSPCNTRL__VMID10__SHIFT 0xa 96#define ATC_TRANS_FAULT_RSPCNTRL__VMID11__SHIFT 0xb 97#define ATC_TRANS_FAULT_RSPCNTRL__VMID12__SHIFT 0xc 98#define ATC_TRANS_FAULT_RSPCNTRL__VMID13__SHIFT 0xd 99#define ATC_TRANS_FAULT_RSPCNTRL__VMID14__SHIFT 0xe 100#define ATC_TRANS_FAULT_RSPCNTRL__VMID15__SHIFT 0xf 101#define ATC_TRANS_FAULT_RSPCNTRL__VMID16__SHIFT 0x10 102#define ATC_TRANS_FAULT_RSPCNTRL__VMID17__SHIFT 0x11 103#define ATC_TRANS_FAULT_RSPCNTRL__VMID18__SHIFT 0x12 104#define ATC_TRANS_FAULT_RSPCNTRL__VMID19__SHIFT 0x13 105#define ATC_TRANS_FAULT_RSPCNTRL__VMID20__SHIFT 0x14 106#define ATC_TRANS_FAULT_RSPCNTRL__VMID21__SHIFT 0x15 107#define ATC_TRANS_FAULT_RSPCNTRL__VMID22__SHIFT 0x16 108#define ATC_TRANS_FAULT_RSPCNTRL__VMID23__SHIFT 0x17 109#define ATC_TRANS_FAULT_RSPCNTRL__VMID24__SHIFT 0x18 110#define ATC_TRANS_FAULT_RSPCNTRL__VMID25__SHIFT 0x19 111#define ATC_TRANS_FAULT_RSPCNTRL__VMID26__SHIFT 0x1a 112#define ATC_TRANS_FAULT_RSPCNTRL__VMID27__SHIFT 0x1b 113#define ATC_TRANS_FAULT_RSPCNTRL__VMID28__SHIFT 0x1c 114#define ATC_TRANS_FAULT_RSPCNTRL__VMID29__SHIFT 0x1d 115#define ATC_TRANS_FAULT_RSPCNTRL__VMID30__SHIFT 0x1e 116#define ATC_TRANS_FAULT_RSPCNTRL__VMID31__SHIFT 0x1f 117#define ATC_TRANS_FAULT_RSPCNTRL__VMID0_MASK 0x00000001L 118#define ATC_TRANS_FAULT_RSPCNTRL__VMID1_MASK 0x00000002L 119#define ATC_TRANS_FAULT_RSPCNTRL__VMID2_MASK 0x00000004L 120#define ATC_TRANS_FAULT_RSPCNTRL__VMID3_MASK 0x00000008L 121#define ATC_TRANS_FAULT_RSPCNTRL__VMID4_MASK 0x00000010L 122#define ATC_TRANS_FAULT_RSPCNTRL__VMID5_MASK 0x00000020L 123#define ATC_TRANS_FAULT_RSPCNTRL__VMID6_MASK 0x00000040L 124#define ATC_TRANS_FAULT_RSPCNTRL__VMID7_MASK 0x00000080L 125#define ATC_TRANS_FAULT_RSPCNTRL__VMID8_MASK 0x00000100L 126#define ATC_TRANS_FAULT_RSPCNTRL__VMID9_MASK 0x00000200L 127#define ATC_TRANS_FAULT_RSPCNTRL__VMID10_MASK 0x00000400L 128#define ATC_TRANS_FAULT_RSPCNTRL__VMID11_MASK 0x00000800L 129#define ATC_TRANS_FAULT_RSPCNTRL__VMID12_MASK 0x00001000L 130#define ATC_TRANS_FAULT_RSPCNTRL__VMID13_MASK 0x00002000L 131#define ATC_TRANS_FAULT_RSPCNTRL__VMID14_MASK 0x00004000L 132#define ATC_TRANS_FAULT_RSPCNTRL__VMID15_MASK 0x00008000L 133#define ATC_TRANS_FAULT_RSPCNTRL__VMID16_MASK 0x00010000L 134#define ATC_TRANS_FAULT_RSPCNTRL__VMID17_MASK 0x00020000L 135#define ATC_TRANS_FAULT_RSPCNTRL__VMID18_MASK 0x00040000L 136#define ATC_TRANS_FAULT_RSPCNTRL__VMID19_MASK 0x00080000L 137#define ATC_TRANS_FAULT_RSPCNTRL__VMID20_MASK 0x00100000L 138#define ATC_TRANS_FAULT_RSPCNTRL__VMID21_MASK 0x00200000L 139#define ATC_TRANS_FAULT_RSPCNTRL__VMID22_MASK 0x00400000L 140#define ATC_TRANS_FAULT_RSPCNTRL__VMID23_MASK 0x00800000L 141#define ATC_TRANS_FAULT_RSPCNTRL__VMID24_MASK 0x01000000L 142#define ATC_TRANS_FAULT_RSPCNTRL__VMID25_MASK 0x02000000L 143#define ATC_TRANS_FAULT_RSPCNTRL__VMID26_MASK 0x04000000L 144#define ATC_TRANS_FAULT_RSPCNTRL__VMID27_MASK 0x08000000L 145#define ATC_TRANS_FAULT_RSPCNTRL__VMID28_MASK 0x10000000L 146#define ATC_TRANS_FAULT_RSPCNTRL__VMID29_MASK 0x20000000L 147#define ATC_TRANS_FAULT_RSPCNTRL__VMID30_MASK 0x40000000L 148#define ATC_TRANS_FAULT_RSPCNTRL__VMID31_MASK 0x80000000L 149//ATC_ATS_FAULT_STATUS_INFO2 150#define ATC_ATS_FAULT_STATUS_INFO2__VF__SHIFT 0x0 151#define ATC_ATS_FAULT_STATUS_INFO2__VFID__SHIFT 0x1 152#define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID__SHIFT 0x9 153#define ATC_ATS_FAULT_STATUS_INFO2__VF_MASK 0x00000001L 154#define ATC_ATS_FAULT_STATUS_INFO2__VFID_MASK 0x0000001EL 155#define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID_MASK 0x00003E00L 156//ATHUB_MISC_CNTL 157#define ATHUB_MISC_CNTL__CG_OFFDLY__SHIFT 0x6 158#define ATHUB_MISC_CNTL__CG_ENABLE__SHIFT 0x12 159#define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE__SHIFT 0x13 160#define ATHUB_MISC_CNTL__PG_ENABLE__SHIFT 0x14 161#define ATHUB_MISC_CNTL__PG_OFFDLY__SHIFT 0x15 162#define ATHUB_MISC_CNTL__CG_STATUS__SHIFT 0x1b 163#define ATHUB_MISC_CNTL__PG_STATUS__SHIFT 0x1c 164#define ATHUB_MISC_CNTL__CG_OFFDLY_MASK 0x00000FC0L 165#define ATHUB_MISC_CNTL__CG_ENABLE_MASK 0x00040000L 166#define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK 0x00080000L 167#define ATHUB_MISC_CNTL__PG_ENABLE_MASK 0x00100000L 168#define ATHUB_MISC_CNTL__PG_OFFDLY_MASK 0x07E00000L 169#define ATHUB_MISC_CNTL__CG_STATUS_MASK 0x08000000L 170#define ATHUB_MISC_CNTL__PG_STATUS_MASK 0x10000000L 171//ATC_VMID_PASID_MAPPING_UPDATE_STATUS 172#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0 173#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1 174#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2 175#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3 176#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4 177#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5 178#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6 179#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7 180#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8 181#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9 182#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa 183#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb 184#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc 185#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd 186#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe 187#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf 188#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED__SHIFT 0x10 189#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED__SHIFT 0x11 190#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED__SHIFT 0x12 191#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED__SHIFT 0x13 192#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED__SHIFT 0x14 193#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED__SHIFT 0x15 194#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED__SHIFT 0x16 195#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED__SHIFT 0x17 196#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED__SHIFT 0x18 197#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED__SHIFT 0x19 198#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED__SHIFT 0x1a 199#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED__SHIFT 0x1b 200#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED__SHIFT 0x1c 201#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED__SHIFT 0x1d 202#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED__SHIFT 0x1e 203#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED__SHIFT 0x1f 204#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x00000001L 205#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x00000002L 206#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x00000004L 207#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x00000008L 208#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x00000010L 209#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x00000020L 210#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x00000040L 211#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x00000080L 212#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x00000100L 213#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x00000200L 214#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x00000400L 215#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x00000800L 216#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x00001000L 217#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x00002000L 218#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x00004000L 219#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x00008000L 220#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED_MASK 0x00010000L 221#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED_MASK 0x00020000L 222#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED_MASK 0x00040000L 223#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED_MASK 0x00080000L 224#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED_MASK 0x00100000L 225#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED_MASK 0x00200000L 226#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED_MASK 0x00400000L 227#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED_MASK 0x00800000L 228#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED_MASK 0x01000000L 229#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED_MASK 0x02000000L 230#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED_MASK 0x04000000L 231#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED_MASK 0x08000000L 232#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED_MASK 0x10000000L 233#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED_MASK 0x20000000L 234#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED_MASK 0x40000000L 235#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED_MASK 0x80000000L 236//ATC_VMID0_PASID_MAPPING 237#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0 238#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 239#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f 240#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0x0000FFFFL 241#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 242#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000L 243//ATC_VMID1_PASID_MAPPING 244#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0 245#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 246#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f 247#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0x0000FFFFL 248#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 249#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000L 250//ATC_VMID2_PASID_MAPPING 251#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0 252#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 253#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f 254#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0x0000FFFFL 255#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 256#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000L 257//ATC_VMID3_PASID_MAPPING 258#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0 259#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 260#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f 261#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0x0000FFFFL 262#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 263#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000L 264//ATC_VMID4_PASID_MAPPING 265#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0 266#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 267#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f 268#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0x0000FFFFL 269#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 270#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000L 271//ATC_VMID5_PASID_MAPPING 272#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0 273#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 274#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f 275#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0x0000FFFFL 276#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 277#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000L 278//ATC_VMID6_PASID_MAPPING 279#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0 280#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 281#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f 282#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0x0000FFFFL 283#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 284#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000L 285//ATC_VMID7_PASID_MAPPING 286#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0 287#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 288#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f 289#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0x0000FFFFL 290#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 291#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000L 292//ATC_VMID8_PASID_MAPPING 293#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0 294#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 295#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f 296#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0x0000FFFFL 297#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 298#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000L 299//ATC_VMID9_PASID_MAPPING 300#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0 301#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 302#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f 303#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0x0000FFFFL 304#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 305#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000L 306//ATC_VMID10_PASID_MAPPING 307#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0 308#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 309#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f 310#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0x0000FFFFL 311#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 312#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000L 313//ATC_VMID11_PASID_MAPPING 314#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0 315#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 316#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f 317#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0x0000FFFFL 318#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 319#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000L 320//ATC_VMID12_PASID_MAPPING 321#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0 322#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 323#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f 324#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0x0000FFFFL 325#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 326#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000L 327//ATC_VMID13_PASID_MAPPING 328#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0 329#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 330#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f 331#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0x0000FFFFL 332#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 333#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000L 334//ATC_VMID14_PASID_MAPPING 335#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0 336#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 337#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f 338#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0x0000FFFFL 339#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 340#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000L 341//ATC_VMID15_PASID_MAPPING 342#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0 343#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 344#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f 345#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0x0000FFFFL 346#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 347#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000L 348//ATC_ATS_VMID_STATUS 349#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING__SHIFT 0x0 350#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING__SHIFT 0x1 351#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING__SHIFT 0x2 352#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING__SHIFT 0x3 353#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING__SHIFT 0x4 354#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT 0x5 355#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING__SHIFT 0x6 356#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING__SHIFT 0x7 357#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING__SHIFT 0x8 358#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING__SHIFT 0x9 359#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa 360#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING__SHIFT 0xb 361#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING__SHIFT 0xc 362#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING__SHIFT 0xd 363#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT 0xe 364#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING__SHIFT 0xf 365#define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING__SHIFT 0x10 366#define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING__SHIFT 0x11 367#define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING__SHIFT 0x12 368#define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING__SHIFT 0x13 369#define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING__SHIFT 0x14 370#define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING__SHIFT 0x15 371#define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING__SHIFT 0x16 372#define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING__SHIFT 0x17 373#define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING__SHIFT 0x18 374#define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING__SHIFT 0x19 375#define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING__SHIFT 0x1a 376#define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING__SHIFT 0x1b 377#define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING__SHIFT 0x1c 378#define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING__SHIFT 0x1d 379#define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING__SHIFT 0x1e 380#define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING__SHIFT 0x1f 381#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING_MASK 0x00000001L 382#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING_MASK 0x00000002L 383#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING_MASK 0x00000004L 384#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING_MASK 0x00000008L 385#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING_MASK 0x00000010L 386#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING_MASK 0x00000020L 387#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING_MASK 0x00000040L 388#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING_MASK 0x00000080L 389#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING_MASK 0x00000100L 390#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING_MASK 0x00000200L 391#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING_MASK 0x00000400L 392#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING_MASK 0x00000800L 393#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING_MASK 0x00001000L 394#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING_MASK 0x00002000L 395#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING_MASK 0x00004000L 396#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING_MASK 0x00008000L 397#define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING_MASK 0x00010000L 398#define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING_MASK 0x00020000L 399#define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING_MASK 0x00040000L 400#define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING_MASK 0x00080000L 401#define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING_MASK 0x00100000L 402#define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING_MASK 0x00200000L 403#define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING_MASK 0x00400000L 404#define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING_MASK 0x00800000L 405#define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING_MASK 0x01000000L 406#define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING_MASK 0x02000000L 407#define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING_MASK 0x04000000L 408#define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING_MASK 0x08000000L 409#define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING_MASK 0x10000000L 410#define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING_MASK 0x20000000L 411#define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING_MASK 0x40000000L 412#define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING_MASK 0x80000000L 413//ATC_ATS_GFX_ATCL2_STATUS 414#define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x0 415#define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L 416//ATC_PERFCOUNTER0_CFG 417#define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 418#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 419#define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 420#define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 421#define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 422#define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 423#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 424#define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 425#define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 426#define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 427//ATC_PERFCOUNTER1_CFG 428#define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 429#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 430#define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 431#define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 432#define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 433#define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 434#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 435#define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 436#define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 437#define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 438//ATC_PERFCOUNTER2_CFG 439#define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 440#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 441#define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 442#define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 443#define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 444#define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 445#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 446#define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 447#define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 448#define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 449//ATC_PERFCOUNTER3_CFG 450#define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 451#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 452#define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 453#define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 454#define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 455#define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 456#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 457#define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 458#define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 459#define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 460//ATC_PERFCOUNTER_RSLT_CNTL 461#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 462#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 463#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 464#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 465#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 466#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 467#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 468#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 469#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 470#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 471#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 472#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 473//ATC_PERFCOUNTER_LO 474#define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 475#define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 476//ATC_PERFCOUNTER_HI 477#define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 478#define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 479#define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 480#define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 481//ATHUB_PCIE_ATS_CNTL 482#define ATHUB_PCIE_ATS_CNTL__STU__SHIFT 0x10 483#define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f 484#define ATHUB_PCIE_ATS_CNTL__STU_MASK 0x001F0000L 485#define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L 486//ATHUB_PCIE_PASID_CNTL 487#define ATHUB_PCIE_PASID_CNTL__PASID_EN__SHIFT 0x10 488#define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x11 489#define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x12 490#define ATHUB_PCIE_PASID_CNTL__PASID_EN_MASK 0x00010000L 491#define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x00020000L 492#define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x00040000L 493//ATHUB_PCIE_PAGE_REQ_CNTL 494#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 495#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 496#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x00000001L 497#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x00000002L 498//ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC 499#define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 500#define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL 501//ATHUB_COMMAND 502#define ATHUB_COMMAND__BUS_MASTER_EN__SHIFT 0x2 503#define ATHUB_COMMAND__BUS_MASTER_EN_MASK 0x00000004L 504//ATHUB_PCIE_ATS_CNTL_VF_0 505#define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f 506#define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L 507//ATHUB_PCIE_ATS_CNTL_VF_1 508#define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f 509#define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L 510//ATHUB_PCIE_ATS_CNTL_VF_2 511#define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f 512#define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L 513//ATHUB_PCIE_ATS_CNTL_VF_3 514#define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f 515#define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L 516//ATHUB_PCIE_ATS_CNTL_VF_4 517#define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f 518#define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L 519//ATHUB_PCIE_ATS_CNTL_VF_5 520#define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f 521#define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L 522//ATHUB_PCIE_ATS_CNTL_VF_6 523#define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f 524#define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L 525//ATHUB_PCIE_ATS_CNTL_VF_7 526#define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f 527#define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L 528//ATHUB_PCIE_ATS_CNTL_VF_8 529#define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f 530#define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L 531//ATHUB_PCIE_ATS_CNTL_VF_9 532#define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f 533#define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L 534//ATHUB_PCIE_ATS_CNTL_VF_10 535#define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f 536#define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L 537//ATHUB_PCIE_ATS_CNTL_VF_11 538#define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f 539#define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L 540//ATHUB_PCIE_ATS_CNTL_VF_12 541#define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f 542#define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L 543//ATHUB_PCIE_ATS_CNTL_VF_13 544#define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f 545#define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L 546//ATHUB_PCIE_ATS_CNTL_VF_14 547#define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f 548#define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L 549//ATHUB_PCIE_ATS_CNTL_VF_15 550#define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f 551#define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L 552//ATHUB_MEM_POWER_LS 553#define ATHUB_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 554#define ATHUB_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 555#define ATHUB_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 556#define ATHUB_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 557//ATS_IH_CREDIT 558#define ATS_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 559#define ATS_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 560#define ATS_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 561#define ATS_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L 562//ATHUB_IH_CREDIT 563#define ATHUB_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 564#define ATHUB_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 565#define ATHUB_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 566#define ATHUB_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L 567//ATC_VMID16_PASID_MAPPING 568#define ATC_VMID16_PASID_MAPPING__PASID__SHIFT 0x0 569#define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 570#define ATC_VMID16_PASID_MAPPING__VALID__SHIFT 0x1f 571#define ATC_VMID16_PASID_MAPPING__PASID_MASK 0x0000FFFFL 572#define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 573#define ATC_VMID16_PASID_MAPPING__VALID_MASK 0x80000000L 574//ATC_VMID17_PASID_MAPPING 575#define ATC_VMID17_PASID_MAPPING__PASID__SHIFT 0x0 576#define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 577#define ATC_VMID17_PASID_MAPPING__VALID__SHIFT 0x1f 578#define ATC_VMID17_PASID_MAPPING__PASID_MASK 0x0000FFFFL 579#define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 580#define ATC_VMID17_PASID_MAPPING__VALID_MASK 0x80000000L 581//ATC_VMID18_PASID_MAPPING 582#define ATC_VMID18_PASID_MAPPING__PASID__SHIFT 0x0 583#define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 584#define ATC_VMID18_PASID_MAPPING__VALID__SHIFT 0x1f 585#define ATC_VMID18_PASID_MAPPING__PASID_MASK 0x0000FFFFL 586#define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 587#define ATC_VMID18_PASID_MAPPING__VALID_MASK 0x80000000L 588//ATC_VMID19_PASID_MAPPING 589#define ATC_VMID19_PASID_MAPPING__PASID__SHIFT 0x0 590#define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 591#define ATC_VMID19_PASID_MAPPING__VALID__SHIFT 0x1f 592#define ATC_VMID19_PASID_MAPPING__PASID_MASK 0x0000FFFFL 593#define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 594#define ATC_VMID19_PASID_MAPPING__VALID_MASK 0x80000000L 595//ATC_VMID20_PASID_MAPPING 596#define ATC_VMID20_PASID_MAPPING__PASID__SHIFT 0x0 597#define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 598#define ATC_VMID20_PASID_MAPPING__VALID__SHIFT 0x1f 599#define ATC_VMID20_PASID_MAPPING__PASID_MASK 0x0000FFFFL 600#define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 601#define ATC_VMID20_PASID_MAPPING__VALID_MASK 0x80000000L 602//ATC_VMID21_PASID_MAPPING 603#define ATC_VMID21_PASID_MAPPING__PASID__SHIFT 0x0 604#define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 605#define ATC_VMID21_PASID_MAPPING__VALID__SHIFT 0x1f 606#define ATC_VMID21_PASID_MAPPING__PASID_MASK 0x0000FFFFL 607#define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 608#define ATC_VMID21_PASID_MAPPING__VALID_MASK 0x80000000L 609//ATC_VMID22_PASID_MAPPING 610#define ATC_VMID22_PASID_MAPPING__PASID__SHIFT 0x0 611#define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 612#define ATC_VMID22_PASID_MAPPING__VALID__SHIFT 0x1f 613#define ATC_VMID22_PASID_MAPPING__PASID_MASK 0x0000FFFFL 614#define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 615#define ATC_VMID22_PASID_MAPPING__VALID_MASK 0x80000000L 616//ATC_VMID23_PASID_MAPPING 617#define ATC_VMID23_PASID_MAPPING__PASID__SHIFT 0x0 618#define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 619#define ATC_VMID23_PASID_MAPPING__VALID__SHIFT 0x1f 620#define ATC_VMID23_PASID_MAPPING__PASID_MASK 0x0000FFFFL 621#define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 622#define ATC_VMID23_PASID_MAPPING__VALID_MASK 0x80000000L 623//ATC_VMID24_PASID_MAPPING 624#define ATC_VMID24_PASID_MAPPING__PASID__SHIFT 0x0 625#define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 626#define ATC_VMID24_PASID_MAPPING__VALID__SHIFT 0x1f 627#define ATC_VMID24_PASID_MAPPING__PASID_MASK 0x0000FFFFL 628#define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 629#define ATC_VMID24_PASID_MAPPING__VALID_MASK 0x80000000L 630//ATC_VMID25_PASID_MAPPING 631#define ATC_VMID25_PASID_MAPPING__PASID__SHIFT 0x0 632#define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 633#define ATC_VMID25_PASID_MAPPING__VALID__SHIFT 0x1f 634#define ATC_VMID25_PASID_MAPPING__PASID_MASK 0x0000FFFFL 635#define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 636#define ATC_VMID25_PASID_MAPPING__VALID_MASK 0x80000000L 637//ATC_VMID26_PASID_MAPPING 638#define ATC_VMID26_PASID_MAPPING__PASID__SHIFT 0x0 639#define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 640#define ATC_VMID26_PASID_MAPPING__VALID__SHIFT 0x1f 641#define ATC_VMID26_PASID_MAPPING__PASID_MASK 0x0000FFFFL 642#define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 643#define ATC_VMID26_PASID_MAPPING__VALID_MASK 0x80000000L 644//ATC_VMID27_PASID_MAPPING 645#define ATC_VMID27_PASID_MAPPING__PASID__SHIFT 0x0 646#define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 647#define ATC_VMID27_PASID_MAPPING__VALID__SHIFT 0x1f 648#define ATC_VMID27_PASID_MAPPING__PASID_MASK 0x0000FFFFL 649#define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 650#define ATC_VMID27_PASID_MAPPING__VALID_MASK 0x80000000L 651//ATC_VMID28_PASID_MAPPING 652#define ATC_VMID28_PASID_MAPPING__PASID__SHIFT 0x0 653#define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 654#define ATC_VMID28_PASID_MAPPING__VALID__SHIFT 0x1f 655#define ATC_VMID28_PASID_MAPPING__PASID_MASK 0x0000FFFFL 656#define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 657#define ATC_VMID28_PASID_MAPPING__VALID_MASK 0x80000000L 658//ATC_VMID29_PASID_MAPPING 659#define ATC_VMID29_PASID_MAPPING__PASID__SHIFT 0x0 660#define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 661#define ATC_VMID29_PASID_MAPPING__VALID__SHIFT 0x1f 662#define ATC_VMID29_PASID_MAPPING__PASID_MASK 0x0000FFFFL 663#define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 664#define ATC_VMID29_PASID_MAPPING__VALID_MASK 0x80000000L 665//ATC_VMID30_PASID_MAPPING 666#define ATC_VMID30_PASID_MAPPING__PASID__SHIFT 0x0 667#define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 668#define ATC_VMID30_PASID_MAPPING__VALID__SHIFT 0x1f 669#define ATC_VMID30_PASID_MAPPING__PASID_MASK 0x0000FFFFL 670#define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 671#define ATC_VMID30_PASID_MAPPING__VALID_MASK 0x80000000L 672//ATC_VMID31_PASID_MAPPING 673#define ATC_VMID31_PASID_MAPPING__PASID__SHIFT 0x0 674#define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 675#define ATC_VMID31_PASID_MAPPING__VALID__SHIFT 0x1f 676#define ATC_VMID31_PASID_MAPPING__PASID_MASK 0x0000FFFFL 677#define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 678#define ATC_VMID31_PASID_MAPPING__VALID_MASK 0x80000000L 679//ATC_ATS_MMHUB_ATCL2_STATUS 680#define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x0 681#define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L 682//ATHUB_SHARED_VIRT_RESET_REQ 683#define ATHUB_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 684#define ATHUB_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f 685#define ATHUB_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 686#define ATHUB_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L 687//ATHUB_SHARED_ACTIVE_FCN_ID 688#define ATHUB_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 689#define ATHUB_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f 690#define ATHUB_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 691#define ATHUB_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L 692//ATC_ATS_SDPPORT_CNTL 693#define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE__SHIFT 0x0 694#define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE__SHIFT 0x1 695#define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD__SHIFT 0x3 696#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE__SHIFT 0x7 697#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK__SHIFT 0x8 698#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD__SHIFT 0x9 699#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE__SHIFT 0xd 700#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE__SHIFT 0xe 701#define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE__SHIFT 0xf 702#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN__SHIFT 0x10 703#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV__SHIFT 0x11 704#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN__SHIFT 0x12 705#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x13 706#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN__SHIFT 0x14 707#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV__SHIFT 0x15 708#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN__SHIFT 0x16 709#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV__SHIFT 0x17 710#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN__SHIFT 0x18 711#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV__SHIFT 0x19 712#define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE_MASK 0x00000001L 713#define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE_MASK 0x00000006L 714#define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD_MASK 0x00000078L 715#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE_MASK 0x00000080L 716#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK_MASK 0x00000100L 717#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD_MASK 0x00001E00L 718#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE_MASK 0x00002000L 719#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE_MASK 0x00004000L 720#define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE_MASK 0x00008000L 721#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN_MASK 0x00010000L 722#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV_MASK 0x00020000L 723#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN_MASK 0x00040000L 724#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV_MASK 0x00080000L 725#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN_MASK 0x00100000L 726#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV_MASK 0x00200000L 727#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN_MASK 0x00400000L 728#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV_MASK 0x00800000L 729#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN_MASK 0x01000000L 730#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV_MASK 0x02000000L 731//ATC_ATS_VMID_SNAPSHOT_GFX_STAT 732#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0__SHIFT 0x0 733#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1__SHIFT 0x1 734#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2__SHIFT 0x2 735#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3__SHIFT 0x3 736#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4__SHIFT 0x4 737#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5__SHIFT 0x5 738#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6__SHIFT 0x6 739#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7__SHIFT 0x7 740#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8__SHIFT 0x8 741#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9__SHIFT 0x9 742#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10__SHIFT 0xa 743#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11__SHIFT 0xb 744#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12__SHIFT 0xc 745#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13__SHIFT 0xd 746#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14__SHIFT 0xe 747#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15__SHIFT 0xf 748#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0_MASK 0x00000001L 749#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1_MASK 0x00000002L 750#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2_MASK 0x00000004L 751#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3_MASK 0x00000008L 752#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4_MASK 0x00000010L 753#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5_MASK 0x00000020L 754#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6_MASK 0x00000040L 755#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7_MASK 0x00000080L 756#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8_MASK 0x00000100L 757#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9_MASK 0x00000200L 758#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10_MASK 0x00000400L 759#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11_MASK 0x00000800L 760#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12_MASK 0x00001000L 761#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13_MASK 0x00002000L 762#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14_MASK 0x00004000L 763#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15_MASK 0x00008000L 764//ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT 765#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0__SHIFT 0x0 766#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1__SHIFT 0x1 767#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2__SHIFT 0x2 768#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3__SHIFT 0x3 769#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4__SHIFT 0x4 770#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5__SHIFT 0x5 771#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6__SHIFT 0x6 772#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7__SHIFT 0x7 773#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8__SHIFT 0x8 774#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9__SHIFT 0x9 775#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10__SHIFT 0xa 776#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11__SHIFT 0xb 777#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12__SHIFT 0xc 778#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13__SHIFT 0xd 779#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14__SHIFT 0xe 780#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15__SHIFT 0xf 781#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0_MASK 0x00000001L 782#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1_MASK 0x00000002L 783#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2_MASK 0x00000004L 784#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3_MASK 0x00000008L 785#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4_MASK 0x00000010L 786#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5_MASK 0x00000020L 787#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6_MASK 0x00000040L 788#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7_MASK 0x00000080L 789#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8_MASK 0x00000100L 790#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9_MASK 0x00000200L 791#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10_MASK 0x00000400L 792#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11_MASK 0x00000800L 793#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12_MASK 0x00001000L 794#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13_MASK 0x00002000L 795#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14_MASK 0x00004000L 796#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15_MASK 0x00008000L 797 798 799// addressBlock: athub_xpbdec 800//XPB_RTR_SRC_APRTR0 801#define XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 802#define XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL 803//XPB_RTR_SRC_APRTR1 804#define XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 805#define XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL 806//XPB_RTR_SRC_APRTR2 807#define XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 808#define XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL 809//XPB_RTR_SRC_APRTR3 810#define XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 811#define XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL 812//XPB_RTR_SRC_APRTR4 813#define XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0 814#define XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x7FFFFFFFL 815//XPB_RTR_SRC_APRTR5 816#define XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0 817#define XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x7FFFFFFFL 818//XPB_RTR_SRC_APRTR6 819#define XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0 820#define XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x7FFFFFFFL 821//XPB_RTR_SRC_APRTR7 822#define XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0 823#define XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x7FFFFFFFL 824//XPB_RTR_SRC_APRTR8 825#define XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0 826#define XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x7FFFFFFFL 827//XPB_RTR_SRC_APRTR9 828#define XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0 829#define XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x7FFFFFFFL 830//XPB_XDMA_RTR_SRC_APRTR0 831#define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 832#define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL 833//XPB_XDMA_RTR_SRC_APRTR1 834#define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 835#define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL 836//XPB_XDMA_RTR_SRC_APRTR2 837#define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 838#define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL 839//XPB_XDMA_RTR_SRC_APRTR3 840#define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 841#define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL 842//XPB_RTR_DEST_MAP0 843#define XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0 844#define XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 845#define XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 846#define XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 847#define XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a 848#define XPB_RTR_DEST_MAP0__NMR_MASK 0x00000001L 849#define XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL 850#define XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L 851#define XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L 852#define XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L 853//XPB_RTR_DEST_MAP1 854#define XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0 855#define XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 856#define XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 857#define XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 858#define XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a 859#define XPB_RTR_DEST_MAP1__NMR_MASK 0x00000001L 860#define XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL 861#define XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L 862#define XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L 863#define XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L 864//XPB_RTR_DEST_MAP2 865#define XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0 866#define XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 867#define XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 868#define XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 869#define XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a 870#define XPB_RTR_DEST_MAP2__NMR_MASK 0x00000001L 871#define XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL 872#define XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L 873#define XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L 874#define XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L 875//XPB_RTR_DEST_MAP3 876#define XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0 877#define XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 878#define XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 879#define XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 880#define XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a 881#define XPB_RTR_DEST_MAP3__NMR_MASK 0x00000001L 882#define XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL 883#define XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L 884#define XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L 885#define XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L 886//XPB_RTR_DEST_MAP4 887#define XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0 888#define XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1 889#define XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14 890#define XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18 891#define XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a 892#define XPB_RTR_DEST_MAP4__NMR_MASK 0x00000001L 893#define XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0x000FFFFEL 894#define XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0x00F00000L 895#define XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x01000000L 896#define XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7C000000L 897//XPB_RTR_DEST_MAP5 898#define XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0 899#define XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1 900#define XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14 901#define XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18 902#define XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a 903#define XPB_RTR_DEST_MAP5__NMR_MASK 0x00000001L 904#define XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0x000FFFFEL 905#define XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0x00F00000L 906#define XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x01000000L 907#define XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7C000000L 908//XPB_RTR_DEST_MAP6 909#define XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0 910#define XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1 911#define XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14 912#define XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18 913#define XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a 914#define XPB_RTR_DEST_MAP6__NMR_MASK 0x00000001L 915#define XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0x000FFFFEL 916#define XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0x00F00000L 917#define XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x01000000L 918#define XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7C000000L 919//XPB_RTR_DEST_MAP7 920#define XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0 921#define XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1 922#define XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14 923#define XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18 924#define XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a 925#define XPB_RTR_DEST_MAP7__NMR_MASK 0x00000001L 926#define XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0x000FFFFEL 927#define XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0x00F00000L 928#define XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x01000000L 929#define XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7C000000L 930//XPB_RTR_DEST_MAP8 931#define XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0 932#define XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1 933#define XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14 934#define XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18 935#define XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a 936#define XPB_RTR_DEST_MAP8__NMR_MASK 0x00000001L 937#define XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0x000FFFFEL 938#define XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0x00F00000L 939#define XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x01000000L 940#define XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7C000000L 941//XPB_RTR_DEST_MAP9 942#define XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0 943#define XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1 944#define XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14 945#define XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18 946#define XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a 947#define XPB_RTR_DEST_MAP9__NMR_MASK 0x00000001L 948#define XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0x000FFFFEL 949#define XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0x00F00000L 950#define XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x01000000L 951#define XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7C000000L 952//XPB_XDMA_RTR_DEST_MAP0 953#define XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0 954#define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 955#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 956#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 957#define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a 958#define XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x00000001L 959#define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL 960#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L 961#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L 962#define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L 963//XPB_XDMA_RTR_DEST_MAP1 964#define XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0 965#define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 966#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 967#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 968#define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a 969#define XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x00000001L 970#define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL 971#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L 972#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L 973#define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L 974//XPB_XDMA_RTR_DEST_MAP2 975#define XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0 976#define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 977#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 978#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 979#define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a 980#define XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x00000001L 981#define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL 982#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L 983#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L 984#define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L 985//XPB_XDMA_RTR_DEST_MAP3 986#define XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0 987#define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 988#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 989#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 990#define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a 991#define XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x00000001L 992#define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL 993#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L 994#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L 995#define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L 996//XPB_CLG_CFG0 997#define XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0 998#define XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7 999#define XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa 1000#define XPB_CLG_CFG0__WCB_NUM_MASK 0x0000000FL 1001#define XPB_CLG_CFG0__P2P_BAR_MASK 0x00000380L 1002#define XPB_CLG_CFG0__HOST_FLUSH_MASK 0x00003C00L 1003//XPB_CLG_CFG1 1004#define XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0 1005#define XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7 1006#define XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa 1007#define XPB_CLG_CFG1__WCB_NUM_MASK 0x0000000FL 1008#define XPB_CLG_CFG1__P2P_BAR_MASK 0x00000380L 1009#define XPB_CLG_CFG1__HOST_FLUSH_MASK 0x00003C00L 1010//XPB_CLG_CFG2 1011#define XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0 1012#define XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7 1013#define XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa 1014#define XPB_CLG_CFG2__WCB_NUM_MASK 0x0000000FL 1015#define XPB_CLG_CFG2__P2P_BAR_MASK 0x00000380L 1016#define XPB_CLG_CFG2__HOST_FLUSH_MASK 0x00003C00L 1017//XPB_CLG_CFG3 1018#define XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0 1019#define XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7 1020#define XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa 1021#define XPB_CLG_CFG3__WCB_NUM_MASK 0x0000000FL 1022#define XPB_CLG_CFG3__P2P_BAR_MASK 0x00000380L 1023#define XPB_CLG_CFG3__HOST_FLUSH_MASK 0x00003C00L 1024//XPB_CLG_CFG4 1025#define XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0 1026#define XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7 1027#define XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa 1028#define XPB_CLG_CFG4__WCB_NUM_MASK 0x0000000FL 1029#define XPB_CLG_CFG4__P2P_BAR_MASK 0x00000380L 1030#define XPB_CLG_CFG4__HOST_FLUSH_MASK 0x00003C00L 1031//XPB_CLG_CFG5 1032#define XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0 1033#define XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7 1034#define XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa 1035#define XPB_CLG_CFG5__WCB_NUM_MASK 0x0000000FL 1036#define XPB_CLG_CFG5__P2P_BAR_MASK 0x00000380L 1037#define XPB_CLG_CFG5__HOST_FLUSH_MASK 0x00003C00L 1038//XPB_CLG_CFG6 1039#define XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0 1040#define XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7 1041#define XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa 1042#define XPB_CLG_CFG6__WCB_NUM_MASK 0x0000000FL 1043#define XPB_CLG_CFG6__P2P_BAR_MASK 0x00000380L 1044#define XPB_CLG_CFG6__HOST_FLUSH_MASK 0x00003C00L 1045//XPB_CLG_CFG7 1046#define XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0 1047#define XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7 1048#define XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa 1049#define XPB_CLG_CFG7__WCB_NUM_MASK 0x0000000FL 1050#define XPB_CLG_CFG7__P2P_BAR_MASK 0x00000380L 1051#define XPB_CLG_CFG7__HOST_FLUSH_MASK 0x00003C00L 1052//XPB_CLG_EXTRA 1053#define XPB_CLG_EXTRA__CMP0_HIGH__SHIFT 0x0 1054#define XPB_CLG_EXTRA__CMP0_LOW__SHIFT 0x6 1055#define XPB_CLG_EXTRA__VLD0__SHIFT 0xb 1056#define XPB_CLG_EXTRA__CLG0_NUM__SHIFT 0xc 1057#define XPB_CLG_EXTRA__CMP1_HIGH__SHIFT 0xf 1058#define XPB_CLG_EXTRA__CMP1_LOW__SHIFT 0x15 1059#define XPB_CLG_EXTRA__VLD1__SHIFT 0x1a 1060#define XPB_CLG_EXTRA__CLG1_NUM__SHIFT 0x1b 1061#define XPB_CLG_EXTRA__CMP0_HIGH_MASK 0x0000003FL 1062#define XPB_CLG_EXTRA__CMP0_LOW_MASK 0x000007C0L 1063#define XPB_CLG_EXTRA__VLD0_MASK 0x00000800L 1064#define XPB_CLG_EXTRA__CLG0_NUM_MASK 0x00007000L 1065#define XPB_CLG_EXTRA__CMP1_HIGH_MASK 0x001F8000L 1066#define XPB_CLG_EXTRA__CMP1_LOW_MASK 0x03E00000L 1067#define XPB_CLG_EXTRA__VLD1_MASK 0x04000000L 1068#define XPB_CLG_EXTRA__CLG1_NUM_MASK 0x38000000L 1069//XPB_CLG_EXTRA_MSK 1070#define XPB_CLG_EXTRA_MSK__MSK0_HIGH__SHIFT 0x0 1071#define XPB_CLG_EXTRA_MSK__MSK0_LOW__SHIFT 0x6 1072#define XPB_CLG_EXTRA_MSK__MSK1_HIGH__SHIFT 0xb 1073#define XPB_CLG_EXTRA_MSK__MSK1_LOW__SHIFT 0x11 1074#define XPB_CLG_EXTRA_MSK__MSK0_HIGH_MASK 0x0000003FL 1075#define XPB_CLG_EXTRA_MSK__MSK0_LOW_MASK 0x000007C0L 1076#define XPB_CLG_EXTRA_MSK__MSK1_HIGH_MASK 0x0001F800L 1077#define XPB_CLG_EXTRA_MSK__MSK1_LOW_MASK 0x003E0000L 1078//XPB_LB_ADDR 1079#define XPB_LB_ADDR__CMP0__SHIFT 0x0 1080#define XPB_LB_ADDR__MASK0__SHIFT 0xa 1081#define XPB_LB_ADDR__CMP1__SHIFT 0x14 1082#define XPB_LB_ADDR__MASK1__SHIFT 0x1a 1083#define XPB_LB_ADDR__CMP0_MASK 0x000003FFL 1084#define XPB_LB_ADDR__MASK0_MASK 0x000FFC00L 1085#define XPB_LB_ADDR__CMP1_MASK 0x03F00000L 1086#define XPB_LB_ADDR__MASK1_MASK 0xFC000000L 1087//XPB_WCB_STS 1088#define XPB_WCB_STS__PBUF_VLD__SHIFT 0x0 1089#define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10 1090#define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17 1091#define XPB_WCB_STS__PBUF_VLD_MASK 0x0000FFFFL 1092#define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x007F0000L 1093#define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3F800000L 1094//XPB_HST_CFG 1095#define XPB_HST_CFG__BAR_UP_WR_CMD__SHIFT 0x0 1096#define XPB_HST_CFG__BAR_UP_WR_CMD_MASK 0x00000001L 1097//XPB_P2P_BAR_CFG 1098#define XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0 1099#define XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4 1100#define XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6 1101#define XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7 1102#define XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8 1103#define XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9 1104#define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa 1105#define XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb 1106#define XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc 1107#define XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0x0000000FL 1108#define XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x00000030L 1109#define XPB_P2P_BAR_CFG__SNOOP_MASK 0x00000040L 1110#define XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x00000080L 1111#define XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x00000100L 1112#define XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x00000200L 1113#define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x00000400L 1114#define XPB_P2P_BAR_CFG__RD_EN_MASK 0x00000800L 1115#define XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x00001000L 1116//XPB_P2P_BAR0 1117#define XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0 1118#define XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4 1119#define XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8 1120#define XPB_P2P_BAR0__VALID__SHIFT 0xc 1121#define XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd 1122#define XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe 1123#define XPB_P2P_BAR0__RESERVED__SHIFT 0xf 1124#define XPB_P2P_BAR0__ADDRESS__SHIFT 0x10 1125#define XPB_P2P_BAR0__HOST_FLUSH_MASK 0x0000000FL 1126#define XPB_P2P_BAR0__REG_SYS_BAR_MASK 0x000000F0L 1127#define XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0x00000F00L 1128#define XPB_P2P_BAR0__VALID_MASK 0x00001000L 1129#define XPB_P2P_BAR0__SEND_DIS_MASK 0x00002000L 1130#define XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x00004000L 1131#define XPB_P2P_BAR0__RESERVED_MASK 0x00008000L 1132#define XPB_P2P_BAR0__ADDRESS_MASK 0xFFFF0000L 1133//XPB_P2P_BAR1 1134#define XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0 1135#define XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4 1136#define XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8 1137#define XPB_P2P_BAR1__VALID__SHIFT 0xc 1138#define XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd 1139#define XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe 1140#define XPB_P2P_BAR1__RESERVED__SHIFT 0xf 1141#define XPB_P2P_BAR1__ADDRESS__SHIFT 0x10 1142#define XPB_P2P_BAR1__HOST_FLUSH_MASK 0x0000000FL 1143#define XPB_P2P_BAR1__REG_SYS_BAR_MASK 0x000000F0L 1144#define XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0x00000F00L 1145#define XPB_P2P_BAR1__VALID_MASK 0x00001000L 1146#define XPB_P2P_BAR1__SEND_DIS_MASK 0x00002000L 1147#define XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x00004000L 1148#define XPB_P2P_BAR1__RESERVED_MASK 0x00008000L 1149#define XPB_P2P_BAR1__ADDRESS_MASK 0xFFFF0000L 1150//XPB_P2P_BAR2 1151#define XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0 1152#define XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4 1153#define XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8 1154#define XPB_P2P_BAR2__VALID__SHIFT 0xc 1155#define XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd 1156#define XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe 1157#define XPB_P2P_BAR2__RESERVED__SHIFT 0xf 1158#define XPB_P2P_BAR2__ADDRESS__SHIFT 0x10 1159#define XPB_P2P_BAR2__HOST_FLUSH_MASK 0x0000000FL 1160#define XPB_P2P_BAR2__REG_SYS_BAR_MASK 0x000000F0L 1161#define XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0x00000F00L 1162#define XPB_P2P_BAR2__VALID_MASK 0x00001000L 1163#define XPB_P2P_BAR2__SEND_DIS_MASK 0x00002000L 1164#define XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x00004000L 1165#define XPB_P2P_BAR2__RESERVED_MASK 0x00008000L 1166#define XPB_P2P_BAR2__ADDRESS_MASK 0xFFFF0000L 1167//XPB_P2P_BAR3 1168#define XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0 1169#define XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4 1170#define XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8 1171#define XPB_P2P_BAR3__VALID__SHIFT 0xc 1172#define XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd 1173#define XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe 1174#define XPB_P2P_BAR3__RESERVED__SHIFT 0xf 1175#define XPB_P2P_BAR3__ADDRESS__SHIFT 0x10 1176#define XPB_P2P_BAR3__HOST_FLUSH_MASK 0x0000000FL 1177#define XPB_P2P_BAR3__REG_SYS_BAR_MASK 0x000000F0L 1178#define XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0x00000F00L 1179#define XPB_P2P_BAR3__VALID_MASK 0x00001000L 1180#define XPB_P2P_BAR3__SEND_DIS_MASK 0x00002000L 1181#define XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x00004000L 1182#define XPB_P2P_BAR3__RESERVED_MASK 0x00008000L 1183#define XPB_P2P_BAR3__ADDRESS_MASK 0xFFFF0000L 1184//XPB_P2P_BAR4 1185#define XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0 1186#define XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4 1187#define XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8 1188#define XPB_P2P_BAR4__VALID__SHIFT 0xc 1189#define XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd 1190#define XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe 1191#define XPB_P2P_BAR4__RESERVED__SHIFT 0xf 1192#define XPB_P2P_BAR4__ADDRESS__SHIFT 0x10 1193#define XPB_P2P_BAR4__HOST_FLUSH_MASK 0x0000000FL 1194#define XPB_P2P_BAR4__REG_SYS_BAR_MASK 0x000000F0L 1195#define XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0x00000F00L 1196#define XPB_P2P_BAR4__VALID_MASK 0x00001000L 1197#define XPB_P2P_BAR4__SEND_DIS_MASK 0x00002000L 1198#define XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x00004000L 1199#define XPB_P2P_BAR4__RESERVED_MASK 0x00008000L 1200#define XPB_P2P_BAR4__ADDRESS_MASK 0xFFFF0000L 1201//XPB_P2P_BAR5 1202#define XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0 1203#define XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4 1204#define XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8 1205#define XPB_P2P_BAR5__VALID__SHIFT 0xc 1206#define XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd 1207#define XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe 1208#define XPB_P2P_BAR5__RESERVED__SHIFT 0xf 1209#define XPB_P2P_BAR5__ADDRESS__SHIFT 0x10 1210#define XPB_P2P_BAR5__HOST_FLUSH_MASK 0x0000000FL 1211#define XPB_P2P_BAR5__REG_SYS_BAR_MASK 0x000000F0L 1212#define XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0x00000F00L 1213#define XPB_P2P_BAR5__VALID_MASK 0x00001000L 1214#define XPB_P2P_BAR5__SEND_DIS_MASK 0x00002000L 1215#define XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x00004000L 1216#define XPB_P2P_BAR5__RESERVED_MASK 0x00008000L 1217#define XPB_P2P_BAR5__ADDRESS_MASK 0xFFFF0000L 1218//XPB_P2P_BAR6 1219#define XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0 1220#define XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4 1221#define XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8 1222#define XPB_P2P_BAR6__VALID__SHIFT 0xc 1223#define XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd 1224#define XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe 1225#define XPB_P2P_BAR6__RESERVED__SHIFT 0xf 1226#define XPB_P2P_BAR6__ADDRESS__SHIFT 0x10 1227#define XPB_P2P_BAR6__HOST_FLUSH_MASK 0x0000000FL 1228#define XPB_P2P_BAR6__REG_SYS_BAR_MASK 0x000000F0L 1229#define XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0x00000F00L 1230#define XPB_P2P_BAR6__VALID_MASK 0x00001000L 1231#define XPB_P2P_BAR6__SEND_DIS_MASK 0x00002000L 1232#define XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x00004000L 1233#define XPB_P2P_BAR6__RESERVED_MASK 0x00008000L 1234#define XPB_P2P_BAR6__ADDRESS_MASK 0xFFFF0000L 1235//XPB_P2P_BAR7 1236#define XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0 1237#define XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4 1238#define XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8 1239#define XPB_P2P_BAR7__VALID__SHIFT 0xc 1240#define XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd 1241#define XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe 1242#define XPB_P2P_BAR7__RESERVED__SHIFT 0xf 1243#define XPB_P2P_BAR7__ADDRESS__SHIFT 0x10 1244#define XPB_P2P_BAR7__HOST_FLUSH_MASK 0x0000000FL 1245#define XPB_P2P_BAR7__REG_SYS_BAR_MASK 0x000000F0L 1246#define XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0x00000F00L 1247#define XPB_P2P_BAR7__VALID_MASK 0x00001000L 1248#define XPB_P2P_BAR7__SEND_DIS_MASK 0x00002000L 1249#define XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x00004000L 1250#define XPB_P2P_BAR7__RESERVED_MASK 0x00008000L 1251#define XPB_P2P_BAR7__ADDRESS_MASK 0xFFFF0000L 1252//XPB_P2P_BAR_SETUP 1253#define XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0 1254#define XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8 1255#define XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc 1256#define XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd 1257#define XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe 1258#define XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf 1259#define XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10 1260#define XPB_P2P_BAR_SETUP__SEL_MASK 0x000000FFL 1261#define XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0x00000F00L 1262#define XPB_P2P_BAR_SETUP__VALID_MASK 0x00001000L 1263#define XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x00002000L 1264#define XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x00004000L 1265#define XPB_P2P_BAR_SETUP__RESERVED_MASK 0x00008000L 1266#define XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xFFFF0000L 1267//XPB_P2P_BAR_DELTA_ABOVE 1268#define XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0 1269#define XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8 1270#define XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0x000000FFL 1271#define XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0x0FFFFF00L 1272//XPB_P2P_BAR_DELTA_BELOW 1273#define XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0 1274#define XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8 1275#define XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0x000000FFL 1276#define XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0x0FFFFF00L 1277//XPB_PEER_SYS_BAR0 1278#define XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0 1279#define XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x1 1280#define XPB_PEER_SYS_BAR0__VALID_MASK 0x00000001L 1281#define XPB_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL 1282//XPB_PEER_SYS_BAR1 1283#define XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0 1284#define XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x1 1285#define XPB_PEER_SYS_BAR1__VALID_MASK 0x00000001L 1286#define XPB_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL 1287//XPB_PEER_SYS_BAR2 1288#define XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0 1289#define XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x1 1290#define XPB_PEER_SYS_BAR2__VALID_MASK 0x00000001L 1291#define XPB_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL 1292//XPB_PEER_SYS_BAR3 1293#define XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0 1294#define XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x1 1295#define XPB_PEER_SYS_BAR3__VALID_MASK 0x00000001L 1296#define XPB_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL 1297//XPB_PEER_SYS_BAR4 1298#define XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0 1299#define XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x1 1300#define XPB_PEER_SYS_BAR4__VALID_MASK 0x00000001L 1301#define XPB_PEER_SYS_BAR4__ADDR_MASK 0xFFFFFFFEL 1302//XPB_PEER_SYS_BAR5 1303#define XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0 1304#define XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x1 1305#define XPB_PEER_SYS_BAR5__VALID_MASK 0x00000001L 1306#define XPB_PEER_SYS_BAR5__ADDR_MASK 0xFFFFFFFEL 1307//XPB_PEER_SYS_BAR6 1308#define XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0 1309#define XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x1 1310#define XPB_PEER_SYS_BAR6__VALID_MASK 0x00000001L 1311#define XPB_PEER_SYS_BAR6__ADDR_MASK 0xFFFFFFFEL 1312//XPB_PEER_SYS_BAR7 1313#define XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0 1314#define XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x1 1315#define XPB_PEER_SYS_BAR7__VALID_MASK 0x00000001L 1316#define XPB_PEER_SYS_BAR7__ADDR_MASK 0xFFFFFFFEL 1317//XPB_PEER_SYS_BAR8 1318#define XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0 1319#define XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x1 1320#define XPB_PEER_SYS_BAR8__VALID_MASK 0x00000001L 1321#define XPB_PEER_SYS_BAR8__ADDR_MASK 0xFFFFFFFEL 1322//XPB_PEER_SYS_BAR9 1323#define XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0 1324#define XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x1 1325#define XPB_PEER_SYS_BAR9__VALID_MASK 0x00000001L 1326#define XPB_PEER_SYS_BAR9__ADDR_MASK 0xFFFFFFFEL 1327//XPB_XDMA_PEER_SYS_BAR0 1328#define XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0 1329#define XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x1 1330#define XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x00000001L 1331#define XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL 1332//XPB_XDMA_PEER_SYS_BAR1 1333#define XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0 1334#define XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x1 1335#define XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x00000001L 1336#define XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL 1337//XPB_XDMA_PEER_SYS_BAR2 1338#define XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0 1339#define XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x1 1340#define XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x00000001L 1341#define XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL 1342//XPB_XDMA_PEER_SYS_BAR3 1343#define XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0 1344#define XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x1 1345#define XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x00000001L 1346#define XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL 1347//XPB_CLK_GAT 1348#define XPB_CLK_GAT__ONDLY__SHIFT 0x0 1349#define XPB_CLK_GAT__OFFDLY__SHIFT 0x6 1350#define XPB_CLK_GAT__RDYDLY__SHIFT 0xc 1351#define XPB_CLK_GAT__ENABLE__SHIFT 0x12 1352#define XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13 1353#define XPB_CLK_GAT__ONDLY_MASK 0x0000003FL 1354#define XPB_CLK_GAT__OFFDLY_MASK 0x00000FC0L 1355#define XPB_CLK_GAT__RDYDLY_MASK 0x0003F000L 1356#define XPB_CLK_GAT__ENABLE_MASK 0x00040000L 1357#define XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x00080000L 1358//XPB_INTF_CFG 1359#define XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0 1360#define XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8 1361#define XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10 1362#define XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17 1363#define XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18 1364#define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19 1365#define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a 1366#define XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b 1367#define XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d 1368#define XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e 1369#define XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f 1370#define XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0x000000FFL 1371#define XPB_INTF_CFG__MC_WRRET_ASK_MASK 0x0000FF00L 1372#define XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x007F0000L 1373#define XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x00800000L 1374#define XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x01000000L 1375#define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x02000000L 1376#define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x04000000L 1377#define XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000L 1378#define XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000L 1379#define XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000L 1380#define XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000L 1381//XPB_INTF_STS 1382#define XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0 1383#define XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8 1384#define XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf 1385#define XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10 1386#define XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11 1387#define XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12 1388#define XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13 1389#define XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0x000000FFL 1390#define XPB_INTF_STS__XSP_REQ_CRD_MASK 0x00007F00L 1391#define XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x00008000L 1392#define XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x00010000L 1393#define XPB_INTF_STS__CNS_BUF_FULL_MASK 0x00020000L 1394#define XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x00040000L 1395#define XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x07F80000L 1396//XPB_PIPE_STS 1397#define XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0 1398#define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1 1399#define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8 1400#define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf 1401#define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10 1402#define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11 1403#define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12 1404#define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13 1405#define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14 1406#define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15 1407#define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16 1408#define XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17 1409#define XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18 1410#define XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x00000001L 1411#define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0x000000FEL 1412#define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x00007F00L 1413#define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x00008000L 1414#define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x00010000L 1415#define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x00020000L 1416#define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x00040000L 1417#define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x00080000L 1418#define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x00100000L 1419#define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x00200000L 1420#define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x00400000L 1421#define XPB_PIPE_STS__RET_BUF_FULL_MASK 0x00800000L 1422#define XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xFF000000L 1423//XPB_SUB_CTRL 1424#define XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0 1425#define XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1 1426#define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2 1427#define XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3 1428#define XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4 1429#define XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5 1430#define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6 1431#define XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7 1432#define XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8 1433#define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9 1434#define XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa 1435#define XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb 1436#define XPB_SUB_CTRL__RESET_RET__SHIFT 0xc 1437#define XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd 1438#define XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe 1439#define XPB_SUB_CTRL__RESET_HST__SHIFT 0xf 1440#define XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10 1441#define XPB_SUB_CTRL__RESET_SID__SHIFT 0x11 1442#define XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12 1443#define XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13 1444#define XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x00000001L 1445#define XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x00000002L 1446#define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x00000004L 1447#define XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x00000008L 1448#define XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x00000010L 1449#define XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x00000020L 1450#define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x00000040L 1451#define XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x00000080L 1452#define XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x00000100L 1453#define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x00000200L 1454#define XPB_SUB_CTRL__RESET_CNS_MASK 0x00000400L 1455#define XPB_SUB_CTRL__RESET_RTR_MASK 0x00000800L 1456#define XPB_SUB_CTRL__RESET_RET_MASK 0x00001000L 1457#define XPB_SUB_CTRL__RESET_MAP_MASK 0x00002000L 1458#define XPB_SUB_CTRL__RESET_WCB_MASK 0x00004000L 1459#define XPB_SUB_CTRL__RESET_HST_MASK 0x00008000L 1460#define XPB_SUB_CTRL__RESET_HOP_MASK 0x00010000L 1461#define XPB_SUB_CTRL__RESET_SID_MASK 0x00020000L 1462#define XPB_SUB_CTRL__RESET_SRB_MASK 0x00040000L 1463#define XPB_SUB_CTRL__RESET_CGR_MASK 0x00080000L 1464//XPB_MAP_INVERT_FLUSH_NUM_LSB 1465#define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0 1466#define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0x0000FFFFL 1467//XPB_PERF_KNOBS 1468#define XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0 1469#define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6 1470#define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc 1471#define XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x0000003FL 1472#define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0x00000FC0L 1473#define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x0003F000L 1474//XPB_STICKY 1475#define XPB_STICKY__BITS__SHIFT 0x0 1476#define XPB_STICKY__BITS_MASK 0xFFFFFFFFL 1477//XPB_STICKY_W1C 1478#define XPB_STICKY_W1C__BITS__SHIFT 0x0 1479#define XPB_STICKY_W1C__BITS_MASK 0xFFFFFFFFL 1480//XPB_MISC_CFG 1481#define XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0 1482#define XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8 1483#define XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10 1484#define XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18 1485#define XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f 1486#define XPB_MISC_CFG__FIELDNAME0_MASK 0x000000FFL 1487#define XPB_MISC_CFG__FIELDNAME1_MASK 0x0000FF00L 1488#define XPB_MISC_CFG__FIELDNAME2_MASK 0x00FF0000L 1489#define XPB_MISC_CFG__FIELDNAME3_MASK 0x7F000000L 1490#define XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000L 1491//XPB_INTF_CFG2 1492#define XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0 1493#define XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0x000000FFL 1494//XPB_CLG_EXTRA_RD 1495#define XPB_CLG_EXTRA_RD__CMP0_HIGH__SHIFT 0x0 1496#define XPB_CLG_EXTRA_RD__CMP0_LOW__SHIFT 0x6 1497#define XPB_CLG_EXTRA_RD__VLD0__SHIFT 0xb 1498#define XPB_CLG_EXTRA_RD__CLG0_NUM__SHIFT 0xc 1499#define XPB_CLG_EXTRA_RD__CMP1_HIGH__SHIFT 0xf 1500#define XPB_CLG_EXTRA_RD__CMP1_LOW__SHIFT 0x15 1501#define XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x1a 1502#define XPB_CLG_EXTRA_RD__CLG1_NUM__SHIFT 0x1b 1503#define XPB_CLG_EXTRA_RD__CMP0_HIGH_MASK 0x0000003FL 1504#define XPB_CLG_EXTRA_RD__CMP0_LOW_MASK 0x000007C0L 1505#define XPB_CLG_EXTRA_RD__VLD0_MASK 0x00000800L 1506#define XPB_CLG_EXTRA_RD__CLG0_NUM_MASK 0x00007000L 1507#define XPB_CLG_EXTRA_RD__CMP1_HIGH_MASK 0x001F8000L 1508#define XPB_CLG_EXTRA_RD__CMP1_LOW_MASK 0x03E00000L 1509#define XPB_CLG_EXTRA_RD__VLD1_MASK 0x04000000L 1510#define XPB_CLG_EXTRA_RD__CLG1_NUM_MASK 0x38000000L 1511//XPB_CLG_EXTRA_MSK_RD 1512#define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH__SHIFT 0x0 1513#define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW__SHIFT 0x6 1514#define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH__SHIFT 0xb 1515#define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW__SHIFT 0x11 1516#define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH_MASK 0x0000003FL 1517#define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW_MASK 0x000007C0L 1518#define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH_MASK 0x0001F800L 1519#define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW_MASK 0x003E0000L 1520//XPB_CLG_GFX_MATCH 1521#define XPB_CLG_GFX_MATCH__FARBIRC0_ID__SHIFT 0x0 1522#define XPB_CLG_GFX_MATCH__FARBIRC1_ID__SHIFT 0x6 1523#define XPB_CLG_GFX_MATCH__FARBIRC2_ID__SHIFT 0xc 1524#define XPB_CLG_GFX_MATCH__FARBIRC3_ID__SHIFT 0x12 1525#define XPB_CLG_GFX_MATCH__FARBIRC0_VLD__SHIFT 0x18 1526#define XPB_CLG_GFX_MATCH__FARBIRC1_VLD__SHIFT 0x19 1527#define XPB_CLG_GFX_MATCH__FARBIRC2_VLD__SHIFT 0x1a 1528#define XPB_CLG_GFX_MATCH__FARBIRC3_VLD__SHIFT 0x1b 1529#define XPB_CLG_GFX_MATCH__FARBIRC0_ID_MASK 0x0000003FL 1530#define XPB_CLG_GFX_MATCH__FARBIRC1_ID_MASK 0x00000FC0L 1531#define XPB_CLG_GFX_MATCH__FARBIRC2_ID_MASK 0x0003F000L 1532#define XPB_CLG_GFX_MATCH__FARBIRC3_ID_MASK 0x00FC0000L 1533#define XPB_CLG_GFX_MATCH__FARBIRC0_VLD_MASK 0x01000000L 1534#define XPB_CLG_GFX_MATCH__FARBIRC1_VLD_MASK 0x02000000L 1535#define XPB_CLG_GFX_MATCH__FARBIRC2_VLD_MASK 0x04000000L 1536#define XPB_CLG_GFX_MATCH__FARBIRC3_VLD_MASK 0x08000000L 1537//XPB_CLG_GFX_MATCH_MSK 1538#define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 1539#define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6 1540#define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0xc 1541#define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x12 1542#define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL 1543#define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L 1544#define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003F000L 1545#define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00FC0000L 1546//XPB_CLG_MM_MATCH 1547#define XPB_CLG_MM_MATCH__FARBIRC0_ID__SHIFT 0x0 1548#define XPB_CLG_MM_MATCH__FARBIRC1_ID__SHIFT 0x6 1549#define XPB_CLG_MM_MATCH__FARBIRC2_ID__SHIFT 0xc 1550#define XPB_CLG_MM_MATCH__FARBIRC3_ID__SHIFT 0x12 1551#define XPB_CLG_MM_MATCH__FARBIRC0_VLD__SHIFT 0x18 1552#define XPB_CLG_MM_MATCH__FARBIRC1_VLD__SHIFT 0x19 1553#define XPB_CLG_MM_MATCH__FARBIRC2_VLD__SHIFT 0x1a 1554#define XPB_CLG_MM_MATCH__FARBIRC3_VLD__SHIFT 0x1b 1555#define XPB_CLG_MM_MATCH__FARBIRC0_ID_MASK 0x0000003FL 1556#define XPB_CLG_MM_MATCH__FARBIRC1_ID_MASK 0x00000FC0L 1557#define XPB_CLG_MM_MATCH__FARBIRC2_ID_MASK 0x0003F000L 1558#define XPB_CLG_MM_MATCH__FARBIRC3_ID_MASK 0x00FC0000L 1559#define XPB_CLG_MM_MATCH__FARBIRC0_VLD_MASK 0x01000000L 1560#define XPB_CLG_MM_MATCH__FARBIRC1_VLD_MASK 0x02000000L 1561#define XPB_CLG_MM_MATCH__FARBIRC2_VLD_MASK 0x04000000L 1562#define XPB_CLG_MM_MATCH__FARBIRC3_VLD_MASK 0x08000000L 1563//XPB_CLG_MM_MATCH_MSK 1564#define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 1565#define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6 1566#define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0xc 1567#define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x12 1568#define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL 1569#define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L 1570#define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003F000L 1571#define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00FC0000L 1572//XPB_CLG_GFX_UNITID_MAPPING0 1573#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0 1574#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5 1575#define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6 1576#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL 1577#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L 1578#define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L 1579//XPB_CLG_GFX_UNITID_MAPPING1 1580#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0 1581#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5 1582#define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6 1583#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL 1584#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L 1585#define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L 1586//XPB_CLG_GFX_UNITID_MAPPING2 1587#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0 1588#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5 1589#define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6 1590#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL 1591#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L 1592#define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L 1593//XPB_CLG_GFX_UNITID_MAPPING3 1594#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0 1595#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5 1596#define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6 1597#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL 1598#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L 1599#define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L 1600//XPB_CLG_GFX_UNITID_MAPPING4 1601#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW__SHIFT 0x0 1602#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD__SHIFT 0x5 1603#define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM__SHIFT 0x6 1604#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW_MASK 0x0000001FL 1605#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD_MASK 0x00000020L 1606#define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM_MASK 0x000001C0L 1607//XPB_CLG_GFX_UNITID_MAPPING5 1608#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW__SHIFT 0x0 1609#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD__SHIFT 0x5 1610#define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM__SHIFT 0x6 1611#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW_MASK 0x0000001FL 1612#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD_MASK 0x00000020L 1613#define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM_MASK 0x000001C0L 1614//XPB_CLG_GFX_UNITID_MAPPING6 1615#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW__SHIFT 0x0 1616#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD__SHIFT 0x5 1617#define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM__SHIFT 0x6 1618#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW_MASK 0x0000001FL 1619#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD_MASK 0x00000020L 1620#define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM_MASK 0x000001C0L 1621//XPB_CLG_GFX_UNITID_MAPPING7 1622#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW__SHIFT 0x0 1623#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD__SHIFT 0x5 1624#define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM__SHIFT 0x6 1625#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW_MASK 0x0000001FL 1626#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD_MASK 0x00000020L 1627#define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM_MASK 0x000001C0L 1628//XPB_CLG_MM_UNITID_MAPPING0 1629#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0 1630#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5 1631#define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6 1632#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL 1633#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L 1634#define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L 1635//XPB_CLG_MM_UNITID_MAPPING1 1636#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0 1637#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5 1638#define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6 1639#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL 1640#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L 1641#define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L 1642//XPB_CLG_MM_UNITID_MAPPING2 1643#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0 1644#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5 1645#define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6 1646#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL 1647#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L 1648#define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L 1649//XPB_CLG_MM_UNITID_MAPPING3 1650#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0 1651#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5 1652#define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6 1653#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL 1654#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L 1655#define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L 1656 1657 1658// addressBlock: athub_rpbdec 1659//RPB_PASSPW_CONF 1660#define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE__SHIFT 0x0 1661#define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE__SHIFT 0x1 1662#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE__SHIFT 0x2 1663#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE__SHIFT 0x3 1664#define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE__SHIFT 0x4 1665#define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE__SHIFT 0x5 1666#define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE__SHIFT 0x6 1667#define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE__SHIFT 0x7 1668#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE__SHIFT 0x8 1669#define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE__SHIFT 0x9 1670#define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE__SHIFT 0xa 1671#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN__SHIFT 0xb 1672#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN__SHIFT 0xc 1673#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN__SHIFT 0xd 1674#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE__SHIFT 0xe 1675#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN__SHIFT 0xf 1676#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE__SHIFT 0x10 1677#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN__SHIFT 0x11 1678#define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE_MASK 0x00000001L 1679#define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE_MASK 0x00000002L 1680#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_MASK 0x00000004L 1681#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_MASK 0x00000008L 1682#define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE_MASK 0x00000010L 1683#define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE_MASK 0x00000020L 1684#define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE_MASK 0x00000040L 1685#define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE_MASK 0x00000080L 1686#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_MASK 0x00000100L 1687#define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE_MASK 0x00000200L 1688#define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE_MASK 0x00000400L 1689#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN_MASK 0x00000800L 1690#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN_MASK 0x00001000L 1691#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN_MASK 0x00002000L 1692#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_MASK 0x00004000L 1693#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN_MASK 0x00008000L 1694#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_MASK 0x00010000L 1695#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN_MASK 0x00020000L 1696//RPB_BLOCKLEVEL_CONF 1697#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE__SHIFT 0x0 1698#define RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL__SHIFT 0x2 1699#define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL__SHIFT 0x4 1700#define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL__SHIFT 0x6 1701#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE__SHIFT 0x8 1702#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE__SHIFT 0xa 1703#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE__SHIFT 0xc 1704#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xe 1705#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xf 1706#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x10 1707#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x11 1708#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_MASK 0x00000003L 1709#define RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL_MASK 0x0000000CL 1710#define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL_MASK 0x00000030L 1711#define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL_MASK 0x000000C0L 1712#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_MASK 0x00000300L 1713#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_MASK 0x00000C00L 1714#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_MASK 0x00003000L 1715#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00004000L 1716#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00008000L 1717#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00010000L 1718#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00020000L 1719//RPB_TAG_CONF 1720#define RPB_TAG_CONF__RPB_ATS_TR__SHIFT 0x0 1721#define RPB_TAG_CONF__RPB_IO_WR__SHIFT 0x8 1722#define RPB_TAG_CONF__RPB_ATS_PR__SHIFT 0x10 1723#define RPB_TAG_CONF__RPB_ATS_TR_MASK 0x000000FFL 1724#define RPB_TAG_CONF__RPB_IO_WR_MASK 0x0000FF00L 1725#define RPB_TAG_CONF__RPB_ATS_PR_MASK 0x00FF0000L 1726//RPB_EFF_CNTL 1727#define RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0 1728#define RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8 1729#define RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0x000000FFL 1730#define RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0x0000FF00L 1731//RPB_ARB_CNTL 1732#define RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x0 1733#define RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x8 1734#define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM__SHIFT 0x10 1735#define RPB_ARB_CNTL__ARB_MODE__SHIFT 0x18 1736#define RPB_ARB_CNTL__SWITCH_NUM_MODE__SHIFT 0x19 1737#define RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0x000000FFL 1738#define RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0x0000FF00L 1739#define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM_MASK 0x00FF0000L 1740#define RPB_ARB_CNTL__ARB_MODE_MASK 0x01000000L 1741#define RPB_ARB_CNTL__SWITCH_NUM_MODE_MASK 0x02000000L 1742//RPB_ARB_CNTL2 1743#define RPB_ARB_CNTL2__P2P_SWITCH_NUM__SHIFT 0x0 1744#define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM__SHIFT 0x8 1745#define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM__SHIFT 0x10 1746#define RPB_ARB_CNTL2__P2P_SWITCH_NUM_MASK 0x000000FFL 1747#define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM_MASK 0x0000FF00L 1748#define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM_MASK 0x00FF0000L 1749//RPB_BIF_CNTL 1750#define RPB_BIF_CNTL__VC0_SWITCH_NUM__SHIFT 0x0 1751#define RPB_BIF_CNTL__VC1_SWITCH_NUM__SHIFT 0x8 1752#define RPB_BIF_CNTL__ARB_MODE__SHIFT 0x10 1753#define RPB_BIF_CNTL__DRAIN_VC_NUM__SHIFT 0x11 1754#define RPB_BIF_CNTL__SWITCH_ENABLE__SHIFT 0x12 1755#define RPB_BIF_CNTL__SWITCH_THRESHOLD__SHIFT 0x13 1756#define RPB_BIF_CNTL__PAGE_PRI_EN__SHIFT 0x1b 1757#define RPB_BIF_CNTL__TR_PRI_EN__SHIFT 0x1c 1758#define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE__SHIFT 0x1d 1759#define RPB_BIF_CNTL__PARITY_CHECK_EN__SHIFT 0x1e 1760#define RPB_BIF_CNTL__VC0_SWITCH_NUM_MASK 0x000000FFL 1761#define RPB_BIF_CNTL__VC1_SWITCH_NUM_MASK 0x0000FF00L 1762#define RPB_BIF_CNTL__ARB_MODE_MASK 0x00010000L 1763#define RPB_BIF_CNTL__DRAIN_VC_NUM_MASK 0x00020000L 1764#define RPB_BIF_CNTL__SWITCH_ENABLE_MASK 0x00040000L 1765#define RPB_BIF_CNTL__SWITCH_THRESHOLD_MASK 0x07F80000L 1766#define RPB_BIF_CNTL__PAGE_PRI_EN_MASK 0x08000000L 1767#define RPB_BIF_CNTL__TR_PRI_EN_MASK 0x10000000L 1768#define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE_MASK 0x20000000L 1769#define RPB_BIF_CNTL__PARITY_CHECK_EN_MASK 0x40000000L 1770//RPB_WR_SWITCH_CNTL 1771#define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 1772#define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x7 1773#define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0xe 1774#define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x15 1775#define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x1c 1776#define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007FL 1777#define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003F80L 1778#define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001FC000L 1779#define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0FE00000L 1780#define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L 1781//RPB_RD_SWITCH_CNTL 1782#define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 1783#define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x7 1784#define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0xe 1785#define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x15 1786#define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x1c 1787#define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007FL 1788#define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003F80L 1789#define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001FC000L 1790#define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0FE00000L 1791#define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L 1792//RPB_CID_QUEUE_WR 1793#define RPB_CID_QUEUE_WR__CLIENT_ID_LOW__SHIFT 0x0 1794#define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH__SHIFT 0x5 1795#define RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0xb 1796#define RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0xc 1797#define RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xf 1798#define RPB_CID_QUEUE_WR__UPDATE__SHIFT 0x12 1799#define RPB_CID_QUEUE_WR__CLIENT_ID_LOW_MASK 0x0000001FL 1800#define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH_MASK 0x000007E0L 1801#define RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x00000800L 1802#define RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x00007000L 1803#define RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x00038000L 1804#define RPB_CID_QUEUE_WR__UPDATE_MASK 0x00040000L 1805//RPB_CID_QUEUE_RD 1806#define RPB_CID_QUEUE_RD__CLIENT_ID_LOW__SHIFT 0x0 1807#define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH__SHIFT 0x5 1808#define RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0xb 1809#define RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xe 1810#define RPB_CID_QUEUE_RD__CLIENT_ID_LOW_MASK 0x0000001FL 1811#define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH_MASK 0x000007E0L 1812#define RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x00003800L 1813#define RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0x0001C000L 1814//RPB_CID_QUEUE_EX 1815#define RPB_CID_QUEUE_EX__START__SHIFT 0x0 1816#define RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1 1817#define RPB_CID_QUEUE_EX__START_MASK 0x00000001L 1818#define RPB_CID_QUEUE_EX__OFFSET_MASK 0x000001FEL 1819//RPB_CID_QUEUE_EX_DATA 1820#define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0 1821#define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10 1822#define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0x0000FFFFL 1823#define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xFFFF0000L 1824//RPB_SWITCH_CNTL2 1825#define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM__SHIFT 0x0 1826#define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM__SHIFT 0x7 1827#define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM__SHIFT 0xe 1828#define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM__SHIFT 0x15 1829#define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM_MASK 0x0000007FL 1830#define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM_MASK 0x00003F80L 1831#define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM_MASK 0x001FC000L 1832#define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM_MASK 0x0FE00000L 1833//RPB_DEINTRLV_COMBINE_CNTL 1834#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER__SHIFT 0x0 1835#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN__SHIFT 0x4 1836#define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE__SHIFT 0x5 1837#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER_MASK 0x0000000FL 1838#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN_MASK 0x00000010L 1839#define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE_MASK 0x00000020L 1840//RPB_VC_SWITCH_RDWR 1841#define RPB_VC_SWITCH_RDWR__MODE__SHIFT 0x0 1842#define RPB_VC_SWITCH_RDWR__NUM_RD__SHIFT 0x2 1843#define RPB_VC_SWITCH_RDWR__NUM_WR__SHIFT 0xa 1844#define RPB_VC_SWITCH_RDWR__MODE_MASK 0x00000003L 1845#define RPB_VC_SWITCH_RDWR__NUM_RD_MASK 0x000003FCL 1846#define RPB_VC_SWITCH_RDWR__NUM_WR_MASK 0x0003FC00L 1847//RPB_PERFCOUNTER_LO 1848#define RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 1849#define RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 1850//RPB_PERFCOUNTER_HI 1851#define RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 1852#define RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 1853#define RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 1854#define RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 1855//RPB_PERFCOUNTER0_CFG 1856#define RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 1857#define RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 1858#define RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 1859#define RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 1860#define RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 1861#define RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 1862#define RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 1863#define RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 1864#define RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 1865#define RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 1866//RPB_PERFCOUNTER1_CFG 1867#define RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 1868#define RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 1869#define RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 1870#define RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 1871#define RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 1872#define RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 1873#define RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 1874#define RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 1875#define RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 1876#define RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 1877//RPB_PERFCOUNTER2_CFG 1878#define RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 1879#define RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 1880#define RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 1881#define RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 1882#define RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 1883#define RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 1884#define RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 1885#define RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 1886#define RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 1887#define RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 1888//RPB_PERFCOUNTER3_CFG 1889#define RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 1890#define RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 1891#define RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 1892#define RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 1893#define RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 1894#define RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 1895#define RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 1896#define RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 1897#define RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 1898#define RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 1899//RPB_PERFCOUNTER_RSLT_CNTL 1900#define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 1901#define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 1902#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 1903#define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 1904#define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 1905#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 1906#define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 1907#define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 1908#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 1909#define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 1910#define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 1911#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 1912//RPB_RD_QUEUE_CNTL 1913#define RPB_RD_QUEUE_CNTL__ARB_MODE__SHIFT 0x0 1914#define RPB_RD_QUEUE_CNTL__Q4_SHARED__SHIFT 0x1 1915#define RPB_RD_QUEUE_CNTL__Q5_SHARED__SHIFT 0x2 1916#define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x3 1917#define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x4 1918#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x5 1919#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0xa 1920#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x10 1921#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x15 1922#define RPB_RD_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L 1923#define RPB_RD_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L 1924#define RPB_RD_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L 1925#define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L 1926#define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L 1927#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003E0L 1928#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000FC00L 1929#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001F0000L 1930#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07E00000L 1931//RPB_RD_QUEUE_CNTL2 1932#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x0 1933#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x5 1934#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0xb 1935#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x10 1936#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001FL 1937#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007E0L 1938#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000F800L 1939#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003F0000L 1940//RPB_WR_QUEUE_CNTL 1941#define RPB_WR_QUEUE_CNTL__ARB_MODE__SHIFT 0x0 1942#define RPB_WR_QUEUE_CNTL__Q4_SHARED__SHIFT 0x1 1943#define RPB_WR_QUEUE_CNTL__Q5_SHARED__SHIFT 0x2 1944#define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x3 1945#define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x4 1946#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x5 1947#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0xa 1948#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x10 1949#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x15 1950#define RPB_WR_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L 1951#define RPB_WR_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L 1952#define RPB_WR_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L 1953#define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L 1954#define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L 1955#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003E0L 1956#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000FC00L 1957#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001F0000L 1958#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07E00000L 1959//RPB_WR_QUEUE_CNTL2 1960#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x0 1961#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x5 1962#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0xb 1963#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x10 1964#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001FL 1965#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007E0L 1966#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000F800L 1967#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003F0000L 1968//RPB_EA_QUEUE_WR 1969#define RPB_EA_QUEUE_WR__EA_NUMBER__SHIFT 0x0 1970#define RPB_EA_QUEUE_WR__WRITE_QUEUE__SHIFT 0x5 1971#define RPB_EA_QUEUE_WR__READ_QUEUE__SHIFT 0x8 1972#define RPB_EA_QUEUE_WR__UPDATE__SHIFT 0xb 1973#define RPB_EA_QUEUE_WR__EA_NUMBER_MASK 0x0000001FL 1974#define RPB_EA_QUEUE_WR__WRITE_QUEUE_MASK 0x000000E0L 1975#define RPB_EA_QUEUE_WR__READ_QUEUE_MASK 0x00000700L 1976#define RPB_EA_QUEUE_WR__UPDATE_MASK 0x00000800L 1977//RPB_ATS_CNTL 1978#define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE__SHIFT 0x0 1979#define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE__SHIFT 0x1 1980#define RPB_ATS_CNTL__SWITCH_THRESHOLD__SHIFT 0x2 1981#define RPB_ATS_CNTL__TIME_SLICE__SHIFT 0x7 1982#define RPB_ATS_CNTL__ATCTR_SWITCH_NUM__SHIFT 0xf 1983#define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM__SHIFT 0x13 1984#define RPB_ATS_CNTL__WR_AT__SHIFT 0x17 1985#define RPB_ATS_CNTL__INVAL_COM_CMD__SHIFT 0x19 1986#define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE_MASK 0x00000001L 1987#define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE_MASK 0x00000002L 1988#define RPB_ATS_CNTL__SWITCH_THRESHOLD_MASK 0x0000007CL 1989#define RPB_ATS_CNTL__TIME_SLICE_MASK 0x00007F80L 1990#define RPB_ATS_CNTL__ATCTR_SWITCH_NUM_MASK 0x00078000L 1991#define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM_MASK 0x00780000L 1992#define RPB_ATS_CNTL__WR_AT_MASK 0x01800000L 1993#define RPB_ATS_CNTL__INVAL_COM_CMD_MASK 0x7E000000L 1994//RPB_ATS_CNTL2 1995#define RPB_ATS_CNTL2__TRANS_CMD__SHIFT 0x0 1996#define RPB_ATS_CNTL2__PAGE_REQ_CMD__SHIFT 0x6 1997#define RPB_ATS_CNTL2__PAGE_ROUTING_CODE__SHIFT 0xc 1998#define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE__SHIFT 0xf 1999#define RPB_ATS_CNTL2__VENDOR_ID__SHIFT 0x12 2000#define RPB_ATS_CNTL2__TRANS_CMD_MASK 0x0000003FL 2001#define RPB_ATS_CNTL2__PAGE_REQ_CMD_MASK 0x00000FC0L 2002#define RPB_ATS_CNTL2__PAGE_ROUTING_CODE_MASK 0x00007000L 2003#define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE_MASK 0x00038000L 2004#define RPB_ATS_CNTL2__VENDOR_ID_MASK 0x000C0000L 2005//RPB_SDPPORT_CNTL 2006#define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE__SHIFT 0x0 2007#define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE__SHIFT 0x1 2008#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT__SHIFT 0x3 2009#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER__SHIFT 0x4 2010#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS__SHIFT 0x5 2011#define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD__SHIFT 0x6 2012#define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE__SHIFT 0xa 2013#define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE__SHIFT 0xb 2014#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT__SHIFT 0xd 2015#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER__SHIFT 0xe 2016#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS__SHIFT 0xf 2017#define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD__SHIFT 0x10 2018#define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE__SHIFT 0x14 2019#define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK__SHIFT 0x15 2020#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN__SHIFT 0x16 2021#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV__SHIFT 0x17 2022#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN__SHIFT 0x18 2023#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x19 2024#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN__SHIFT 0x1a 2025#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV__SHIFT 0x1b 2026#define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE_MASK 0x00000001L 2027#define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE_MASK 0x00000006L 2028#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT_MASK 0x00000008L 2029#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER_MASK 0x00000010L 2030#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS_MASK 0x00000020L 2031#define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD_MASK 0x000003C0L 2032#define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE_MASK 0x00000400L 2033#define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE_MASK 0x00001800L 2034#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT_MASK 0x00002000L 2035#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER_MASK 0x00004000L 2036#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS_MASK 0x00008000L 2037#define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD_MASK 0x000F0000L 2038#define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE_MASK 0x00100000L 2039#define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK_MASK 0x00200000L 2040#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN_MASK 0x00400000L 2041#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV_MASK 0x00800000L 2042#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN_MASK 0x01000000L 2043#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV_MASK 0x02000000L 2044#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN_MASK 0x04000000L 2045#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV_MASK 0x08000000L 2046 2047#endif 2048