1/* $NetBSD: amdgpu_hw_gpio.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */ 2 3/* 4 * Copyright 2012-15 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28#include <sys/cdefs.h> 29__KERNEL_RCSID(0, "$NetBSD: amdgpu_hw_gpio.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $"); 30 31#include "dm_services.h" 32#include "include/gpio_types.h" 33#include "hw_gpio.h" 34 35#include "reg_helper.h" 36#include "gpio_regs.h" 37 38#undef FN 39#define FN(reg_name, field_name) \ 40 gpio->regs->field_name ## _shift, gpio->regs->field_name ## _mask 41 42#define CTX \ 43 gpio->base.ctx 44#define REG(reg)\ 45 (gpio->regs->reg) 46 47static void store_registers( 48 struct hw_gpio *gpio) 49{ 50 REG_GET(MASK_reg, MASK, &gpio->store.mask); 51 REG_GET(A_reg, A, &gpio->store.a); 52 REG_GET(EN_reg, EN, &gpio->store.en); 53 /* TODO store GPIO_MUX_CONTROL if we ever use it */ 54} 55 56static void restore_registers( 57 struct hw_gpio *gpio) 58{ 59 REG_UPDATE(MASK_reg, MASK, gpio->store.mask); 60 REG_UPDATE(A_reg, A, gpio->store.a); 61 REG_UPDATE(EN_reg, EN, gpio->store.en); 62 /* TODO restore GPIO_MUX_CONTROL if we ever use it */ 63} 64 65bool dal_hw_gpio_open( 66 struct hw_gpio_pin *ptr, 67 enum gpio_mode mode) 68{ 69 struct hw_gpio *pin = FROM_HW_GPIO_PIN(ptr); 70 71 store_registers(pin); 72 73 ptr->opened = (dal_hw_gpio_config_mode(pin, mode) == GPIO_RESULT_OK); 74 75 return ptr->opened; 76} 77 78enum gpio_result dal_hw_gpio_get_value( 79 const struct hw_gpio_pin *ptr, 80 uint32_t *value) 81{ 82 const struct hw_gpio *gpio = const_container_of(ptr, struct hw_gpio, base); 83 84 enum gpio_result result = GPIO_RESULT_OK; 85 86 switch (ptr->mode) { 87 case GPIO_MODE_INPUT: 88 case GPIO_MODE_OUTPUT: 89 case GPIO_MODE_HARDWARE: 90 case GPIO_MODE_FAST_OUTPUT: 91 REG_GET(Y_reg, Y, value); 92 break; 93 default: 94 result = GPIO_RESULT_NON_SPECIFIC_ERROR; 95 } 96 97 return result; 98} 99 100enum gpio_result dal_hw_gpio_set_value( 101 const struct hw_gpio_pin *ptr, 102 uint32_t value) 103{ 104 const struct hw_gpio *gpio = const_container_of(ptr, struct hw_gpio, base); 105 106 /* This is the public interface 107 * where the input comes from client, not shifted yet 108 * (because client does not know the shifts). */ 109 110 switch (ptr->mode) { 111 case GPIO_MODE_OUTPUT: 112 REG_UPDATE(A_reg, A, value); 113 return GPIO_RESULT_OK; 114 case GPIO_MODE_FAST_OUTPUT: 115 /* We use (EN) to faster switch (used in DDC GPIO). 116 * So (A) is grounded, output is driven by (EN = 0) 117 * to pull the line down (output == 0) and (EN=1) 118 * then output is tri-state */ 119 REG_UPDATE(EN_reg, EN, ~value); 120 return GPIO_RESULT_OK; 121 default: 122 return GPIO_RESULT_NON_SPECIFIC_ERROR; 123 } 124} 125 126enum gpio_result dal_hw_gpio_change_mode( 127 struct hw_gpio_pin *ptr, 128 enum gpio_mode mode) 129{ 130 struct hw_gpio *pin = FROM_HW_GPIO_PIN(ptr); 131 132 return dal_hw_gpio_config_mode(pin, mode); 133} 134 135void dal_hw_gpio_close( 136 struct hw_gpio_pin *ptr) 137{ 138 struct hw_gpio *pin = FROM_HW_GPIO_PIN(ptr); 139 140 restore_registers(pin); 141 142 ptr->mode = GPIO_MODE_UNKNOWN; 143 ptr->opened = false; 144} 145 146enum gpio_result dal_hw_gpio_config_mode( 147 struct hw_gpio *gpio, 148 enum gpio_mode mode) 149{ 150 gpio->base.mode = mode; 151 152 switch (mode) { 153 case GPIO_MODE_INPUT: 154 /* turn off output enable, act as input pin; 155 * program the pin as GPIO, mask out signal driven by HW */ 156 REG_UPDATE(EN_reg, EN, 0); 157 REG_UPDATE(MASK_reg, MASK, 1); 158 return GPIO_RESULT_OK; 159 case GPIO_MODE_OUTPUT: 160 /* turn on output enable, act as output pin; 161 * program the pin as GPIO, mask out signal driven by HW */ 162 REG_UPDATE(A_reg, A, 0); 163 REG_UPDATE(MASK_reg, MASK, 1); 164 return GPIO_RESULT_OK; 165 case GPIO_MODE_FAST_OUTPUT: 166 /* grounding the A register then use the EN register bit 167 * will have faster effect on the rise time */ 168 REG_UPDATE(A_reg, A, 0); 169 REG_UPDATE(MASK_reg, MASK, 1); 170 return GPIO_RESULT_OK; 171 case GPIO_MODE_HARDWARE: 172 /* program the pin as tri-state, pin is driven by HW */ 173 REG_UPDATE(MASK_reg, MASK, 0); 174 return GPIO_RESULT_OK; 175 case GPIO_MODE_INTERRUPT: 176 /* Interrupt mode supported only by HPD (IrqGpio) pins. */ 177 REG_UPDATE(MASK_reg, MASK, 0); 178 return GPIO_RESULT_OK; 179 default: 180 return GPIO_RESULT_NON_SPECIFIC_ERROR; 181 } 182} 183 184void dal_hw_gpio_construct( 185 struct hw_gpio *pin, 186 enum gpio_id id, 187 uint32_t en, 188 struct dc_context *ctx) 189{ 190 pin->base.ctx = ctx; 191 pin->base.id = id; 192 pin->base.en = en; 193 pin->base.mode = GPIO_MODE_UNKNOWN; 194 pin->base.opened = false; 195 196 pin->store.mask = 0; 197 pin->store.a = 0; 198 pin->store.en = 0; 199 pin->store.mux = 0; 200 201 pin->mux_supported = false; 202} 203 204void dal_hw_gpio_destruct( 205 struct hw_gpio *pin) 206{ 207 ASSERT(!pin->base.opened); 208} 209