1/*	$NetBSD: amdgpu_hw_factory.c,v 1.2 2021/12/18 23:45:04 riastradh Exp $	*/
2
3/*
4 * Copyright 2012-15 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27
28#include <sys/cdefs.h>
29__KERNEL_RCSID(0, "$NetBSD: amdgpu_hw_factory.c,v 1.2 2021/12/18 23:45:04 riastradh Exp $");
30
31#include <linux/slab.h>
32
33#include "dm_services.h"
34
35/*
36 * Pre-requisites: headers required by header of this unit
37 */
38#include "include/gpio_types.h"
39
40/*
41 * Header of this unit
42 */
43
44#include "hw_factory.h"
45
46/*
47 * Post-requisites: headers required by this unit
48 */
49
50#include "dce80/hw_factory_dce80.h"
51#include "dce110/hw_factory_dce110.h"
52#include "dce120/hw_factory_dce120.h"
53#if defined(CONFIG_DRM_AMD_DC_DCN)
54#include "dcn10/hw_factory_dcn10.h"
55#endif
56#include "dcn20/hw_factory_dcn20.h"
57#include "dcn21/hw_factory_dcn21.h"
58
59#include "diagnostics/hw_factory_diag.h"
60
61/*
62 * This unit
63 */
64
65bool dal_hw_factory_init(
66	struct hw_factory *factory,
67	enum dce_version dce_version,
68	enum dce_environment dce_environment)
69{
70	if (IS_FPGA_MAXIMUS_DC(dce_environment)) {
71		dal_hw_factory_diag_fpga_init(factory);
72		return true;
73	}
74
75	switch (dce_version) {
76	case DCE_VERSION_8_0:
77	case DCE_VERSION_8_1:
78	case DCE_VERSION_8_3:
79		dal_hw_factory_dce80_init(factory);
80		return true;
81
82	case DCE_VERSION_10_0:
83		dal_hw_factory_dce110_init(factory);
84		return true;
85	case DCE_VERSION_11_0:
86	case DCE_VERSION_11_2:
87	case DCE_VERSION_11_22:
88		dal_hw_factory_dce110_init(factory);
89		return true;
90	case DCE_VERSION_12_0:
91	case DCE_VERSION_12_1:
92		dal_hw_factory_dce120_init(factory);
93		return true;
94#if defined(CONFIG_DRM_AMD_DC_DCN)
95	case DCN_VERSION_1_0:
96	case DCN_VERSION_1_01:
97		dal_hw_factory_dcn10_init(factory);
98		return true;
99
100	case DCN_VERSION_2_0:
101		dal_hw_factory_dcn20_init(factory);
102		return true;
103	case DCN_VERSION_2_1:
104		dal_hw_factory_dcn21_init(factory);
105		return true;
106#endif
107
108	default:
109		ASSERT_CRITICAL(false);
110		return false;
111	}
112}
113
114void dal_hw_factory_destroy(
115	struct dc_context *ctx,
116	struct hw_factory **factory)
117{
118	if (!factory || !*factory) {
119		BREAK_TO_DEBUGGER();
120		return;
121	}
122
123	kfree(*factory);
124
125	*factory = NULL;
126}
127