1/*	$NetBSD: amdgpu_dce112_hw_sequencer.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $	*/
2
3/*
4 * Copyright 2015 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27
28#include <sys/cdefs.h>
29__KERNEL_RCSID(0, "$NetBSD: amdgpu_dce112_hw_sequencer.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $");
30
31#include "dm_services.h"
32#include "dc.h"
33#include "core_types.h"
34#include "dce112_hw_sequencer.h"
35
36#include "dce110/dce110_hw_sequencer.h"
37
38/* include DCE11.2 register header files */
39#include "dce/dce_11_2_d.h"
40#include "dce/dce_11_2_sh_mask.h"
41
42struct dce112_hw_seq_reg_offsets {
43	uint32_t crtc;
44};
45
46
47static const struct dce112_hw_seq_reg_offsets reg_offsets[] = {
48{
49	.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
50},
51{
52	.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
53},
54{
55	.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
56},
57{
58	.crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
59},
60{
61	.crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
62},
63{
64	.crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
65}
66};
67#define HW_REG_CRTC(reg, id)\
68	(reg + reg_offsets[id].crtc)
69
70/*******************************************************************************
71 * Private definitions
72 ******************************************************************************/
73
74static void dce112_init_pte(struct dc_context *ctx)
75{
76	uint32_t addr;
77	uint32_t value = 0;
78	uint32_t chunk_int = 0;
79	uint32_t chunk_mul = 0;
80
81	addr = mmDVMM_PTE_REQ;
82	value = dm_read_reg(ctx, addr);
83
84	chunk_int = get_reg_field_value(
85		value,
86		DVMM_PTE_REQ,
87		HFLIP_PTEREQ_PER_CHUNK_INT);
88
89	chunk_mul = get_reg_field_value(
90		value,
91		DVMM_PTE_REQ,
92		HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
93
94	if (chunk_int != 0x4 || chunk_mul != 0x4) {
95
96		set_reg_field_value(
97			value,
98			255,
99			DVMM_PTE_REQ,
100			MAX_PTEREQ_TO_ISSUE);
101
102		set_reg_field_value(
103			value,
104			4,
105			DVMM_PTE_REQ,
106			HFLIP_PTEREQ_PER_CHUNK_INT);
107
108		set_reg_field_value(
109			value,
110			4,
111			DVMM_PTE_REQ,
112			HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
113
114		dm_write_reg(ctx, addr, value);
115	}
116}
117
118static bool dce112_enable_display_power_gating(
119	struct dc *dc,
120	uint8_t controller_id,
121	struct dc_bios *dcb,
122	enum pipe_gating_control power_gating)
123{
124	enum bp_result bp_result = BP_RESULT_OK;
125	enum bp_pipe_control_action cntl;
126	struct dc_context *ctx = dc->ctx;
127
128	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
129		return true;
130
131	if (power_gating == PIPE_GATING_CONTROL_INIT)
132		cntl = ASIC_PIPE_INIT;
133	else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
134		cntl = ASIC_PIPE_ENABLE;
135	else
136		cntl = ASIC_PIPE_DISABLE;
137
138	if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
139
140		bp_result = dcb->funcs->enable_disp_power_gating(
141						dcb, controller_id + 1, cntl);
142
143		/* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
144		 * by default when command table is called
145		 */
146		dm_write_reg(ctx,
147			HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
148			0);
149	}
150
151	if (power_gating != PIPE_GATING_CONTROL_ENABLE)
152		dce112_init_pte(ctx);
153
154	if (bp_result == BP_RESULT_OK)
155		return true;
156	else
157		return false;
158}
159
160void dce112_hw_sequencer_construct(struct dc *dc)
161{
162	/* All registers used by dce11.2 match those in dce11 in offset and
163	 * structure
164	 */
165	dce110_hw_sequencer_construct(dc);
166	dc->hwseq->funcs.enable_display_power_gating = dce112_enable_display_power_gating;
167}
168
169