1/* $NetBSD: dmub_psr.c,v 1.2 2021/12/18 23:45:02 riastradh Exp $ */ 2 3/* 4 * Copyright 2019 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28#include <sys/cdefs.h> 29__KERNEL_RCSID(0, "$NetBSD: dmub_psr.c,v 1.2 2021/12/18 23:45:02 riastradh Exp $"); 30 31#include "dmub_psr.h" 32#include "dc.h" 33#include "dc_dmub_srv.h" 34#include "../../dmub/inc/dmub_srv.h" 35#include "dmub_fw_state.h" 36#include "core_types.h" 37#include "ipp.h" 38 39#define MAX_PIPES 6 40 41/** 42 * Get PSR state from firmware. 43 */ 44static void dmub_get_psr_state(uint32_t *psr_state) 45{ 46 // Not yet implemented 47 // Trigger GPINT interrupt from firmware 48} 49 50/** 51 * Enable/Disable PSR. 52 */ 53static void dmub_set_psr_enable(struct dmub_psr *dmub, bool enable) 54{ 55 union dmub_rb_cmd cmd; 56 struct dc_context *dc = dmub->ctx; 57 58 cmd.psr_enable.header.type = DMUB_CMD__PSR; 59 60 if (enable) 61 cmd.psr_enable.header.sub_type = DMUB_CMD__PSR_ENABLE; 62 else 63 cmd.psr_enable.header.sub_type = DMUB_CMD__PSR_DISABLE; 64 65 cmd.psr_enable.header.payload_bytes = 0; // Send header only 66 67 dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd.psr_enable.header); 68 dc_dmub_srv_cmd_execute(dc->dmub_srv); 69 dc_dmub_srv_wait_idle(dc->dmub_srv); 70} 71 72/** 73 * Set PSR level. 74 */ 75static void dmub_set_psr_level(struct dmub_psr *dmub, uint16_t psr_level) 76{ 77 union dmub_rb_cmd cmd; 78 uint32_t psr_state = 0; 79 struct dc_context *dc = dmub->ctx; 80 81 dmub_get_psr_state(&psr_state); 82 83 if (psr_state == 0) 84 return; 85 86 cmd.psr_set_level.header.type = DMUB_CMD__PSR; 87 cmd.psr_set_level.header.sub_type = DMUB_CMD__PSR_SET_LEVEL; 88 cmd.psr_set_level.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_level_data); 89 cmd.psr_set_level.psr_set_level_data.psr_level = psr_level; 90 91 dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd.psr_set_level.header); 92 dc_dmub_srv_cmd_execute(dc->dmub_srv); 93 dc_dmub_srv_wait_idle(dc->dmub_srv); 94} 95 96/** 97 * Setup PSR by programming phy registers and sending psr hw context values to firmware. 98 */ 99static bool dmub_setup_psr(struct dmub_psr *dmub, 100 struct dc_link *link, 101 struct psr_context *psr_context) 102{ 103 union dmub_rb_cmd cmd; 104 struct dc_context *dc = dmub->ctx; 105 struct dmub_cmd_psr_copy_settings_data *copy_settings_data 106 = &cmd.psr_copy_settings.psr_copy_settings_data; 107 struct pipe_ctx *pipe_ctx = NULL; 108 struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx; 109 110 for (int i = 0; i < MAX_PIPES; i++) { 111 if (res_ctx && 112 res_ctx->pipe_ctx[i].stream && 113 res_ctx->pipe_ctx[i].stream->link && 114 res_ctx->pipe_ctx[i].stream->link == link && 115 res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) { 116 pipe_ctx = &res_ctx->pipe_ctx[i]; 117 break; 118 } 119 } 120 121 if (!pipe_ctx || 122 !&pipe_ctx->plane_res || 123 !&pipe_ctx->stream_res) 124 return false; 125 126 // Program DP DPHY fast training registers 127 link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, 128 psr_context->psrExitLinkTrainingRequired); 129 130 // Program DP_SEC_CNTL1 register to set transmission GPS0 line num and priority to high 131 link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, 132 psr_context->sdpTransmitLineNumDeadline); 133 134 cmd.psr_copy_settings.header.type = DMUB_CMD__PSR; 135 cmd.psr_copy_settings.header.sub_type = DMUB_CMD__PSR_COPY_SETTINGS; 136 cmd.psr_copy_settings.header.payload_bytes = sizeof(struct dmub_cmd_psr_copy_settings_data); 137 138 // Hw insts 139 copy_settings_data->dpphy_inst = psr_context->phyType; 140 copy_settings_data->aux_inst = psr_context->channel; 141 copy_settings_data->digfe_inst = psr_context->engineId; 142 copy_settings_data->digbe_inst = psr_context->transmitterId; 143 144 copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst; 145 146 if (pipe_ctx->plane_res.hubp) 147 copy_settings_data->hubp_inst = pipe_ctx->plane_res.hubp->inst; 148 else 149 copy_settings_data->hubp_inst = 0; 150 if (pipe_ctx->plane_res.dpp) 151 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; 152 else 153 copy_settings_data->dpp_inst = 0; 154 if (pipe_ctx->stream_res.opp) 155 copy_settings_data->opp_inst = pipe_ctx->stream_res.opp->inst; 156 else 157 copy_settings_data->opp_inst = 0; 158 if (pipe_ctx->stream_res.tg) 159 copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst; 160 else 161 copy_settings_data->otg_inst = 0; 162 163 // Misc 164 copy_settings_data->psr_level = psr_context->psr_level.u32all; 165 copy_settings_data->hyst_frames = psr_context->timehyst_frames; 166 copy_settings_data->hyst_lines = psr_context->hyst_lines; 167 copy_settings_data->phy_type = psr_context->phyType; 168 copy_settings_data->aux_repeat = psr_context->aux_repeats; 169 copy_settings_data->smu_optimizations_en = psr_context->allow_smu_optimizations; 170 copy_settings_data->skip_wait_for_pll_lock = psr_context->skipPsrWaitForPllLock; 171 copy_settings_data->frame_delay = psr_context->frame_delay; 172 copy_settings_data->smu_phy_id = psr_context->smuPhyId; 173 copy_settings_data->num_of_controllers = psr_context->numberOfControllers; 174 copy_settings_data->frame_cap_ind = psr_context->psrFrameCaptureIndicationReq; 175 copy_settings_data->phy_num = psr_context->frame_delay & 0x7; 176 copy_settings_data->link_rate = psr_context->frame_delay & 0xF; 177 178 dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd.psr_copy_settings.header); 179 dc_dmub_srv_cmd_execute(dc->dmub_srv); 180 dc_dmub_srv_wait_idle(dc->dmub_srv); 181 182 return true; 183} 184 185static const struct dmub_psr_funcs psr_funcs = { 186 .set_psr_enable = dmub_set_psr_enable, 187 .setup_psr = dmub_setup_psr, 188 .get_psr_state = dmub_get_psr_state, 189 .set_psr_level = dmub_set_psr_level, 190}; 191 192/** 193 * Construct PSR object. 194 */ 195static void dmub_psr_construct(struct dmub_psr *psr, struct dc_context *ctx) 196{ 197 psr->ctx = ctx; 198 psr->funcs = &psr_funcs; 199} 200 201/** 202 * Allocate and initialize PSR object. 203 */ 204struct dmub_psr *dmub_psr_create(struct dc_context *ctx) 205{ 206 struct dmub_psr *psr = kzalloc(sizeof(struct dmub_psr), GFP_KERNEL); 207 208 if (psr == NULL) { 209 BREAK_TO_DEBUGGER(); 210 return NULL; 211 } 212 213 dmub_psr_construct(psr, ctx); 214 215 return psr; 216} 217 218/** 219 * Deallocate PSR object. 220 */ 221void dmub_psr_destroy(struct dmub_psr **dmub) 222{ 223 kfree(dmub); 224 *dmub = NULL; 225} 226