1/* $NetBSD: si_enums.h,v 1.2 2021/12/18 23:44:59 riastradh Exp $ */ 2 3/* 4 * Copyright 2016 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25#ifndef SI_ENUMS_H 26#define SI_ENUMS_H 27 28#define VBLANK_INT_MASK (1 << 0) 29#define DC_HPDx_INT_EN (1 << 16) 30#define VBLANK_ACK (1 << 4) 31#define VLINE_ACK (1 << 4) 32 33#define CURSOR_WIDTH 64 34#define CURSOR_HEIGHT 64 35 36#define VGA_VSTATUS_CNTL 0xFFFCFFFF 37#define PRIORITY_MARK_MASK 0x7fff 38#define PRIORITY_OFF (1 << 16) 39#define PRIORITY_ALWAYS_ON (1 << 20) 40#define INTERLEAVE_EN (1 << 0) 41 42#define LATENCY_WATERMARK_MASK(x) ((x) << 16) 43#define DC_LB_MEMORY_CONFIG(x) ((x) << 20) 44#define ICON_DEGAMMA_MODE(x) (((x) & 0x3) << 8) 45 46#define GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) 47#define GRPH_ENDIAN_NONE 0 48#define GRPH_ENDIAN_8IN16 1 49#define GRPH_ENDIAN_8IN32 2 50#define GRPH_ENDIAN_8IN64 3 51#define GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4) 52#define GRPH_RED_SEL_R 0 53#define GRPH_RED_SEL_G 1 54#define GRPH_RED_SEL_B 2 55#define GRPH_RED_SEL_A 3 56#define GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6) 57#define GRPH_GREEN_SEL_G 0 58#define GRPH_GREEN_SEL_B 1 59#define GRPH_GREEN_SEL_A 2 60#define GRPH_GREEN_SEL_R 3 61#define GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8) 62#define GRPH_BLUE_SEL_B 0 63#define GRPH_BLUE_SEL_A 1 64#define GRPH_BLUE_SEL_R 2 65#define GRPH_BLUE_SEL_G 3 66#define GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10) 67#define GRPH_ALPHA_SEL_A 0 68#define GRPH_ALPHA_SEL_R 1 69#define GRPH_ALPHA_SEL_G 2 70#define GRPH_ALPHA_SEL_B 3 71 72#define GRPH_DEPTH(x) (((x) & 0x3) << 0) 73#define GRPH_DEPTH_8BPP 0 74#define GRPH_DEPTH_16BPP 1 75#define GRPH_DEPTH_32BPP 2 76 77#define GRPH_FORMAT(x) (((x) & 0x7) << 8) 78#define GRPH_FORMAT_INDEXED 0 79#define GRPH_FORMAT_ARGB1555 0 80#define GRPH_FORMAT_ARGB565 1 81#define GRPH_FORMAT_ARGB4444 2 82#define GRPH_FORMAT_AI88 3 83#define GRPH_FORMAT_MONO16 4 84#define GRPH_FORMAT_BGRA5551 5 85#define GRPH_FORMAT_ARGB8888 0 86#define GRPH_FORMAT_ARGB2101010 1 87#define GRPH_FORMAT_32BPP_DIG 2 88#define GRPH_FORMAT_8B_ARGB2101010 3 89#define GRPH_FORMAT_BGRA1010102 4 90#define GRPH_FORMAT_8B_BGRA1010102 5 91#define GRPH_FORMAT_RGB111110 6 92#define GRPH_FORMAT_BGR101111 7 93 94#define GRPH_NUM_BANKS(x) (((x) & 0x3) << 2) 95#define GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20) 96#define GRPH_ARRAY_LINEAR_GENERAL 0 97#define GRPH_ARRAY_LINEAR_ALIGNED 1 98#define GRPH_ARRAY_1D_TILED_THIN1 2 99#define GRPH_ARRAY_2D_TILED_THIN1 4 100#define GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13) 101#define GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6) 102#define GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11) 103#define GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18) 104#define GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20) 105#define GRPH_PIPE_CONFIG(x) (((x) & 0x1f) << 24) 106 107#define CURSOR_EN (1 << 0) 108#define CURSOR_MODE(x) (((x) & 0x3) << 8) 109#define CURSOR_MONO 0 110#define CURSOR_24_1 1 111#define CURSOR_24_8_PRE_MULT 2 112#define CURSOR_24_8_UNPRE_MULT 3 113#define CURSOR_2X_MAGNIFY (1 << 16) 114#define CURSOR_FORCE_MC_ON (1 << 20) 115#define CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24) 116#define CURSOR_URGENT_ALWAYS 0 117#define CURSOR_URGENT_1_8 1 118#define CURSOR_URGENT_1_4 2 119#define CURSOR_URGENT_3_8 3 120#define CURSOR_URGENT_1_2 4 121#define CURSOR_UPDATE_PENDING (1 << 0) 122#define CURSOR_UPDATE_TAKEN (1 << 1) 123#define CURSOR_UPDATE_LOCK (1 << 16) 124#define CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24) 125 126#define AMDGPU_NUM_OF_VMIDS 8 127#define SI_CRTC0_REGISTER_OFFSET 0 128#define SI_CRTC1_REGISTER_OFFSET 0x300 129#define SI_CRTC2_REGISTER_OFFSET 0x2600 130#define SI_CRTC3_REGISTER_OFFSET 0x2900 131#define SI_CRTC4_REGISTER_OFFSET 0x2c00 132#define SI_CRTC5_REGISTER_OFFSET 0x2f00 133 134#define DMA0_REGISTER_OFFSET 0x000 135#define DMA1_REGISTER_OFFSET 0x200 136#define ES_AND_GS_AUTO 3 137#define RADEON_PACKET_TYPE3 3 138#define CE_PARTITION_BASE 3 139#define BUF_SWAP_32BIT (2 << 16) 140 141#define GFX_POWER_STATUS (1 << 1) 142#define GFX_CLOCK_STATUS (1 << 2) 143#define GFX_LS_STATUS (1 << 3) 144#define RLC_BUSY_STATUS (1 << 0) 145 146#define RLC_PUD(x) ((x) << 0) 147#define RLC_PUD_MASK (0xff << 0) 148#define RLC_PDD(x) ((x) << 8) 149#define RLC_PDD_MASK (0xff << 8) 150#define RLC_TTPD(x) ((x) << 16) 151#define RLC_TTPD_MASK (0xff << 16) 152#define RLC_MSD(x) ((x) << 24) 153#define RLC_MSD_MASK (0xff << 24) 154#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 155#define WRITE_DATA_DST_SEL(x) ((x) << 8) 156#define EVENT_TYPE(x) ((x) << 0) 157#define EVENT_INDEX(x) ((x) << 8) 158#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 159#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 160#define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 161 162#define GFX6_NUM_GFX_RINGS 1 163#define GFX6_NUM_COMPUTE_RINGS 2 164#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90 165#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D 166 167#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 168#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x02010002 169#define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 170 171#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 172 (((op) & 0xFF) << 8) | \ 173 ((n) & 0x3FFF) << 16) 174#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 175#define PACKET3_NOP 0x10 176#define PACKET3_SET_BASE 0x11 177#define PACKET3_BASE_INDEX(x) ((x) << 0) 178#define PACKET3_CLEAR_STATE 0x12 179#define PACKET3_INDEX_BUFFER_SIZE 0x13 180#define PACKET3_DISPATCH_DIRECT 0x15 181#define PACKET3_DISPATCH_INDIRECT 0x16 182#define PACKET3_ALLOC_GDS 0x1B 183#define PACKET3_WRITE_GDS_RAM 0x1C 184#define PACKET3_ATOMIC_GDS 0x1D 185#define PACKET3_ATOMIC 0x1E 186#define PACKET3_OCCLUSION_QUERY 0x1F 187#define PACKET3_SET_PREDICATION 0x20 188#define PACKET3_REG_RMW 0x21 189#define PACKET3_COND_EXEC 0x22 190#define PACKET3_PRED_EXEC 0x23 191#define PACKET3_DRAW_INDIRECT 0x24 192#define PACKET3_DRAW_INDEX_INDIRECT 0x25 193#define PACKET3_INDEX_BASE 0x26 194#define PACKET3_DRAW_INDEX_2 0x27 195#define PACKET3_CONTEXT_CONTROL 0x28 196#define PACKET3_INDEX_TYPE 0x2A 197#define PACKET3_DRAW_INDIRECT_MULTI 0x2C 198#define PACKET3_DRAW_INDEX_AUTO 0x2D 199#define PACKET3_DRAW_INDEX_IMMD 0x2E 200#define PACKET3_NUM_INSTANCES 0x2F 201#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 202#define PACKET3_INDIRECT_BUFFER_CONST 0x31 203#define PACKET3_INDIRECT_BUFFER 0x3F 204#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 205#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 206#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 207#define PACKET3_WRITE_DATA 0x37 208#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 209#define PACKET3_MEM_SEMAPHORE 0x39 210#define PACKET3_MPEG_INDEX 0x3A 211#define PACKET3_COPY_DW 0x3B 212#define PACKET3_WAIT_REG_MEM 0x3C 213#define PACKET3_MEM_WRITE 0x3D 214#define PACKET3_COPY_DATA 0x40 215#define PACKET3_CP_DMA 0x41 216# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) 217# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) 218# define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) 219# define PACKET3_CP_DMA_CP_SYNC (1 << 31) 220# define PACKET3_CP_DMA_DIS_WC (1 << 21) 221# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) 222# define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) 223# define PACKET3_CP_DMA_CMD_SAS (1 << 26) 224# define PACKET3_CP_DMA_CMD_DAS (1 << 27) 225# define PACKET3_CP_DMA_CMD_SAIC (1 << 28) 226# define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 227# define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30) 228#define PACKET3_PFP_SYNC_ME 0x42 229#define PACKET3_SURFACE_SYNC 0x43 230# define PACKET3_DEST_BASE_0_ENA (1 << 0) 231# define PACKET3_DEST_BASE_1_ENA (1 << 1) 232# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 233# define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 234# define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 235# define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 236# define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 237# define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 238# define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 239# define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 240# define PACKET3_DB_DEST_BASE_ENA (1 << 14) 241# define PACKET3_DEST_BASE_2_ENA (1 << 19) 242# define PACKET3_DEST_BASE_3_ENA (1 << 21) 243# define PACKET3_TCL1_ACTION_ENA (1 << 22) 244# define PACKET3_TC_ACTION_ENA (1 << 23) 245# define PACKET3_CB_ACTION_ENA (1 << 25) 246# define PACKET3_DB_ACTION_ENA (1 << 26) 247# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 248# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 249#define PACKET3_ME_INITIALIZE 0x44 250#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 251#define PACKET3_COND_WRITE 0x45 252#define PACKET3_EVENT_WRITE 0x46 253#define PACKET3_EVENT_WRITE_EOP 0x47 254#define PACKET3_EVENT_WRITE_EOS 0x48 255#define PACKET3_PREAMBLE_CNTL 0x4A 256# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 257# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 258#define PACKET3_ONE_REG_WRITE 0x57 259#define PACKET3_LOAD_CONFIG_REG 0x5F 260#define PACKET3_LOAD_CONTEXT_REG 0x60 261#define PACKET3_LOAD_SH_REG 0x61 262#define PACKET3_SET_CONFIG_REG 0x68 263#define PACKET3_SET_CONFIG_REG_START 0x00002000 264#define PACKET3_SET_CONFIG_REG_END 0x00002c00 265#define PACKET3_SET_CONTEXT_REG 0x69 266#define PACKET3_SET_CONTEXT_REG_START 0x000a000 267#define PACKET3_SET_CONTEXT_REG_END 0x000a400 268#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 269#define PACKET3_SET_RESOURCE_INDIRECT 0x74 270#define PACKET3_SET_SH_REG 0x76 271#define PACKET3_SET_SH_REG_START 0x00002c00 272#define PACKET3_SET_SH_REG_END 0x00003000 273#define PACKET3_SET_SH_REG_OFFSET 0x77 274#define PACKET3_ME_WRITE 0x7A 275#define PACKET3_SCRATCH_RAM_WRITE 0x7D 276#define PACKET3_SCRATCH_RAM_READ 0x7E 277#define PACKET3_CE_WRITE 0x7F 278#define PACKET3_LOAD_CONST_RAM 0x80 279#define PACKET3_WRITE_CONST_RAM 0x81 280#define PACKET3_WRITE_CONST_RAM_OFFSET 0x82 281#define PACKET3_DUMP_CONST_RAM 0x83 282#define PACKET3_INCREMENT_CE_COUNTER 0x84 283#define PACKET3_INCREMENT_DE_COUNTER 0x85 284#define PACKET3_WAIT_ON_CE_COUNTER 0x86 285#define PACKET3_WAIT_ON_DE_COUNTER 0x87 286#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 287#define PACKET3_SET_CE_DE_COUNTERS 0x89 288#define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A 289#define PACKET3_SWITCH_BUFFER 0x8B 290#define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12) 291#define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 292#define PACKET3_SEM_SEL_WAIT (0x7 << 29) 293 294#endif 295