1/* $NetBSD: amdgpu_ucode.h,v 1.3 2021/12/18 23:44:58 riastradh Exp $ */ 2 3/* 4 * Copyright 2012 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25#ifndef __AMDGPU_UCODE_H__ 26#define __AMDGPU_UCODE_H__ 27 28#include "amdgpu_socbb.h" 29 30struct common_firmware_header { 31 uint32_t size_bytes; /* size of the entire header+image(s) in bytes */ 32 uint32_t header_size_bytes; /* size of just the header in bytes */ 33 uint16_t header_version_major; /* header version */ 34 uint16_t header_version_minor; /* header version */ 35 uint16_t ip_version_major; /* IP version */ 36 uint16_t ip_version_minor; /* IP version */ 37 uint32_t ucode_version; 38 uint32_t ucode_size_bytes; /* size of ucode in bytes */ 39 uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */ 40 uint32_t crc32; /* crc32 checksum of the payload */ 41}; 42 43/* version_major=1, version_minor=0 */ 44struct mc_firmware_header_v1_0 { 45 struct common_firmware_header header; 46 uint32_t io_debug_size_bytes; /* size of debug array in dwords */ 47 uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */ 48}; 49 50/* version_major=1, version_minor=0 */ 51struct smc_firmware_header_v1_0 { 52 struct common_firmware_header header; 53 uint32_t ucode_start_addr; 54}; 55 56/* version_major=2, version_minor=0 */ 57struct smc_firmware_header_v2_0 { 58 struct smc_firmware_header_v1_0 v1_0; 59 uint32_t ppt_offset_bytes; /* soft pptable offset */ 60 uint32_t ppt_size_bytes; /* soft pptable size */ 61}; 62 63struct smc_soft_pptable_entry { 64 uint32_t id; 65 uint32_t ppt_offset_bytes; 66 uint32_t ppt_size_bytes; 67}; 68 69/* version_major=2, version_minor=1 */ 70struct smc_firmware_header_v2_1 { 71 struct smc_firmware_header_v1_0 v1_0; 72 uint32_t pptable_count; 73 uint32_t pptable_entry_offset; 74}; 75 76/* version_major=1, version_minor=0 */ 77struct psp_firmware_header_v1_0 { 78 struct common_firmware_header header; 79 uint32_t ucode_feature_version; 80 uint32_t sos_offset_bytes; 81 uint32_t sos_size_bytes; 82}; 83 84/* version_major=1, version_minor=1 */ 85struct psp_firmware_header_v1_1 { 86 struct psp_firmware_header_v1_0 v1_0; 87 uint32_t toc_header_version; 88 uint32_t toc_offset_bytes; 89 uint32_t toc_size_bytes; 90 uint32_t kdb_header_version; 91 uint32_t kdb_offset_bytes; 92 uint32_t kdb_size_bytes; 93}; 94 95/* version_major=1, version_minor=2 */ 96struct psp_firmware_header_v1_2 { 97 struct psp_firmware_header_v1_0 v1_0; 98 uint32_t reserve[3]; 99 uint32_t kdb_header_version; 100 uint32_t kdb_offset_bytes; 101 uint32_t kdb_size_bytes; 102}; 103 104/* version_major=1, version_minor=0 */ 105struct ta_firmware_header_v1_0 { 106 struct common_firmware_header header; 107 uint32_t ta_xgmi_ucode_version; 108 uint32_t ta_xgmi_offset_bytes; 109 uint32_t ta_xgmi_size_bytes; 110 uint32_t ta_ras_ucode_version; 111 uint32_t ta_ras_offset_bytes; 112 uint32_t ta_ras_size_bytes; 113 uint32_t ta_hdcp_ucode_version; 114 uint32_t ta_hdcp_offset_bytes; 115 uint32_t ta_hdcp_size_bytes; 116 uint32_t ta_dtm_ucode_version; 117 uint32_t ta_dtm_offset_bytes; 118 uint32_t ta_dtm_size_bytes; 119}; 120 121/* version_major=1, version_minor=0 */ 122struct gfx_firmware_header_v1_0 { 123 struct common_firmware_header header; 124 uint32_t ucode_feature_version; 125 uint32_t jt_offset; /* jt location */ 126 uint32_t jt_size; /* size of jt */ 127}; 128 129/* version_major=1, version_minor=0 */ 130struct mes_firmware_header_v1_0 { 131 struct common_firmware_header header; 132 uint32_t mes_ucode_version; 133 uint32_t mes_ucode_size_bytes; 134 uint32_t mes_ucode_offset_bytes; 135 uint32_t mes_ucode_data_version; 136 uint32_t mes_ucode_data_size_bytes; 137 uint32_t mes_ucode_data_offset_bytes; 138 uint32_t mes_uc_start_addr_lo; 139 uint32_t mes_uc_start_addr_hi; 140 uint32_t mes_data_start_addr_lo; 141 uint32_t mes_data_start_addr_hi; 142}; 143 144/* version_major=1, version_minor=0 */ 145struct rlc_firmware_header_v1_0 { 146 struct common_firmware_header header; 147 uint32_t ucode_feature_version; 148 uint32_t save_and_restore_offset; 149 uint32_t clear_state_descriptor_offset; 150 uint32_t avail_scratch_ram_locations; 151 uint32_t master_pkt_description_offset; 152}; 153 154/* version_major=2, version_minor=0 */ 155struct rlc_firmware_header_v2_0 { 156 struct common_firmware_header header; 157 uint32_t ucode_feature_version; 158 uint32_t jt_offset; /* jt location */ 159 uint32_t jt_size; /* size of jt */ 160 uint32_t save_and_restore_offset; 161 uint32_t clear_state_descriptor_offset; 162 uint32_t avail_scratch_ram_locations; 163 uint32_t reg_restore_list_size; 164 uint32_t reg_list_format_start; 165 uint32_t reg_list_format_separate_start; 166 uint32_t starting_offsets_start; 167 uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */ 168 uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */ 169 uint32_t reg_list_size_bytes; /* size of reg list array in bytes */ 170 uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */ 171 uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */ 172 uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */ 173 uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */ 174 uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */ 175}; 176 177/* version_major=2, version_minor=1 */ 178struct rlc_firmware_header_v2_1 { 179 struct rlc_firmware_header_v2_0 v2_0; 180 uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */ 181 uint32_t save_restore_list_cntl_ucode_ver; 182 uint32_t save_restore_list_cntl_feature_ver; 183 uint32_t save_restore_list_cntl_size_bytes; 184 uint32_t save_restore_list_cntl_offset_bytes; 185 uint32_t save_restore_list_gpm_ucode_ver; 186 uint32_t save_restore_list_gpm_feature_ver; 187 uint32_t save_restore_list_gpm_size_bytes; 188 uint32_t save_restore_list_gpm_offset_bytes; 189 uint32_t save_restore_list_srm_ucode_ver; 190 uint32_t save_restore_list_srm_feature_ver; 191 uint32_t save_restore_list_srm_size_bytes; 192 uint32_t save_restore_list_srm_offset_bytes; 193}; 194 195/* version_major=1, version_minor=0 */ 196struct sdma_firmware_header_v1_0 { 197 struct common_firmware_header header; 198 uint32_t ucode_feature_version; 199 uint32_t ucode_change_version; 200 uint32_t jt_offset; /* jt location */ 201 uint32_t jt_size; /* size of jt */ 202}; 203 204/* version_major=1, version_minor=1 */ 205struct sdma_firmware_header_v1_1 { 206 struct sdma_firmware_header_v1_0 v1_0; 207 uint32_t digest_size; 208}; 209 210/* gpu info payload */ 211struct gpu_info_firmware_v1_0 { 212 uint32_t gc_num_se; 213 uint32_t gc_num_cu_per_sh; 214 uint32_t gc_num_sh_per_se; 215 uint32_t gc_num_rb_per_se; 216 uint32_t gc_num_tccs; 217 uint32_t gc_num_gprs; 218 uint32_t gc_num_max_gs_thds; 219 uint32_t gc_gs_table_depth; 220 uint32_t gc_gsprim_buff_depth; 221 uint32_t gc_parameter_cache_depth; 222 uint32_t gc_double_offchip_lds_buffer; 223 uint32_t gc_wave_size; 224 uint32_t gc_max_waves_per_simd; 225 uint32_t gc_max_scratch_slots_per_cu; 226 uint32_t gc_lds_size; 227}; 228 229struct gpu_info_firmware_v1_1 { 230 struct gpu_info_firmware_v1_0 v1_0; 231 uint32_t num_sc_per_sh; 232 uint32_t num_packer_per_sc; 233}; 234 235/* gpu info payload 236 * version_major=1, version_minor=1 */ 237struct gpu_info_firmware_v1_2 { 238 struct gpu_info_firmware_v1_1 v1_1; 239 struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box; 240}; 241 242/* version_major=1, version_minor=0 */ 243struct gpu_info_firmware_header_v1_0 { 244 struct common_firmware_header header; 245 uint16_t version_major; /* version */ 246 uint16_t version_minor; /* version */ 247}; 248 249/* version_major=1, version_minor=0 */ 250struct dmcu_firmware_header_v1_0 { 251 struct common_firmware_header header; 252 uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */ 253 uint32_t intv_size_bytes; /* size of interrupt vectors, in bytes */ 254}; 255 256/* version_major=1, version_minor=0 */ 257struct dmcub_firmware_header_v1_0 { 258 struct common_firmware_header header; 259 uint32_t inst_const_bytes; /* size of instruction region, in bytes */ 260 uint32_t bss_data_bytes; /* size of bss/data region, in bytes */ 261}; 262 263/* header is fixed size */ 264union amdgpu_firmware_header { 265 struct common_firmware_header common; 266 struct mc_firmware_header_v1_0 mc; 267 struct smc_firmware_header_v1_0 smc; 268 struct smc_firmware_header_v2_0 smc_v2_0; 269 struct psp_firmware_header_v1_0 psp; 270 struct psp_firmware_header_v1_1 psp_v1_1; 271 struct ta_firmware_header_v1_0 ta; 272 struct gfx_firmware_header_v1_0 gfx; 273 struct rlc_firmware_header_v1_0 rlc; 274 struct rlc_firmware_header_v2_0 rlc_v2_0; 275 struct rlc_firmware_header_v2_1 rlc_v2_1; 276 struct sdma_firmware_header_v1_0 sdma; 277 struct sdma_firmware_header_v1_1 sdma_v1_1; 278 struct gpu_info_firmware_header_v1_0 gpu_info; 279 struct dmcu_firmware_header_v1_0 dmcu; 280 struct dmcub_firmware_header_v1_0 dmcub; 281 uint8_t raw[0x100]; 282}; 283 284/* 285 * fw loading support 286 */ 287enum AMDGPU_UCODE_ID { 288 AMDGPU_UCODE_ID_SDMA0 = 0, 289 AMDGPU_UCODE_ID_SDMA1, 290 AMDGPU_UCODE_ID_SDMA2, 291 AMDGPU_UCODE_ID_SDMA3, 292 AMDGPU_UCODE_ID_SDMA4, 293 AMDGPU_UCODE_ID_SDMA5, 294 AMDGPU_UCODE_ID_SDMA6, 295 AMDGPU_UCODE_ID_SDMA7, 296 AMDGPU_UCODE_ID_CP_CE, 297 AMDGPU_UCODE_ID_CP_PFP, 298 AMDGPU_UCODE_ID_CP_ME, 299 AMDGPU_UCODE_ID_CP_MEC1, 300 AMDGPU_UCODE_ID_CP_MEC1_JT, 301 AMDGPU_UCODE_ID_CP_MEC2, 302 AMDGPU_UCODE_ID_CP_MEC2_JT, 303 AMDGPU_UCODE_ID_CP_MES, 304 AMDGPU_UCODE_ID_CP_MES_DATA, 305 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL, 306 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM, 307 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM, 308 AMDGPU_UCODE_ID_RLC_G, 309 AMDGPU_UCODE_ID_STORAGE, 310 AMDGPU_UCODE_ID_SMC, 311 AMDGPU_UCODE_ID_UVD, 312 AMDGPU_UCODE_ID_UVD1, 313 AMDGPU_UCODE_ID_VCE, 314 AMDGPU_UCODE_ID_VCN, 315 AMDGPU_UCODE_ID_VCN1, 316 AMDGPU_UCODE_ID_DMCU_ERAM, 317 AMDGPU_UCODE_ID_DMCU_INTV, 318 AMDGPU_UCODE_ID_VCN0_RAM, 319 AMDGPU_UCODE_ID_VCN1_RAM, 320 AMDGPU_UCODE_ID_DMCUB, 321 AMDGPU_UCODE_ID_MAXIMUM, 322}; 323 324/* engine firmware status */ 325enum AMDGPU_UCODE_STATUS { 326 AMDGPU_UCODE_STATUS_INVALID, 327 AMDGPU_UCODE_STATUS_NOT_LOADED, 328 AMDGPU_UCODE_STATUS_LOADED, 329}; 330 331enum amdgpu_firmware_load_type { 332 AMDGPU_FW_LOAD_DIRECT = 0, 333 AMDGPU_FW_LOAD_SMU, 334 AMDGPU_FW_LOAD_PSP, 335 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO, 336}; 337 338/* conform to smu_ucode_xfer_cz.h */ 339#define AMDGPU_SDMA0_UCODE_LOADED 0x00000001 340#define AMDGPU_SDMA1_UCODE_LOADED 0x00000002 341#define AMDGPU_CPCE_UCODE_LOADED 0x00000004 342#define AMDGPU_CPPFP_UCODE_LOADED 0x00000008 343#define AMDGPU_CPME_UCODE_LOADED 0x00000010 344#define AMDGPU_CPMEC1_UCODE_LOADED 0x00000020 345#define AMDGPU_CPMEC2_UCODE_LOADED 0x00000040 346#define AMDGPU_CPRLC_UCODE_LOADED 0x00000100 347 348/* amdgpu firmware info */ 349struct amdgpu_firmware_info { 350 /* ucode ID */ 351 enum AMDGPU_UCODE_ID ucode_id; 352 /* request_firmware */ 353 const struct firmware *fw; 354 /* starting mc address */ 355 uint64_t mc_addr; 356 /* kernel linear address */ 357 void *kaddr; 358 /* ucode_size_bytes */ 359 uint32_t ucode_size; 360 /* starting tmr mc address */ 361 uint32_t tmr_mc_addr_lo; 362 uint32_t tmr_mc_addr_hi; 363}; 364 365struct amdgpu_firmware { 366 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 367 enum amdgpu_firmware_load_type load_type; 368 struct amdgpu_bo *fw_buf; 369 unsigned int fw_size; 370 unsigned int max_ucodes; 371 /* firmwares are loaded by psp instead of smu from vega10 */ 372 const struct amdgpu_psp_funcs *funcs; 373 struct amdgpu_bo *rbuf; 374 struct mutex mutex; 375 376 /* gpu info firmware data pointer */ 377 const struct firmware *gpu_info_fw; 378 379 void *fw_buf_ptr; 380 uint64_t fw_buf_mc; 381}; 382 383void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr); 384void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr); 385void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr); 386void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr); 387void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr); 388void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr); 389void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr); 390int amdgpu_ucode_validate(const struct firmware *fw); 391bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, 392 uint16_t hdr_major, uint16_t hdr_minor); 393 394int amdgpu_ucode_init_bo(struct amdgpu_device *adev); 395int amdgpu_ucode_create_bo(struct amdgpu_device *adev); 396int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev); 397void amdgpu_ucode_free_bo(struct amdgpu_device *adev); 398void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev); 399 400enum amdgpu_firmware_load_type 401amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type); 402 403#endif 404