1/*	$NetBSD: amdgpu_rlc.h,v 1.3 2021/12/19 12:02:39 riastradh Exp $	*/
2
3/*
4 * Copyright 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26#ifndef __AMDGPU_RLC_H__
27#define __AMDGPU_RLC_H__
28
29#include "clearstate_defs.h"
30
31/* firmware ID used in rlc toc */
32typedef enum _FIRMWARE_ID_ {
33	FIRMWARE_ID_INVALID					= 0,
34	FIRMWARE_ID_RLC_G_UCODE					= 1,
35	FIRMWARE_ID_RLC_TOC					= 2,
36	FIRMWARE_ID_RLCG_SCRATCH                                = 3,
37	FIRMWARE_ID_RLC_SRM_ARAM                                = 4,
38	FIRMWARE_ID_RLC_SRM_INDEX_ADDR                          = 5,
39	FIRMWARE_ID_RLC_SRM_INDEX_DATA                          = 6,
40	FIRMWARE_ID_RLC_P_UCODE                                 = 7,
41	FIRMWARE_ID_RLC_V_UCODE                                 = 8,
42	FIRMWARE_ID_RLX6_UCODE                                  = 9,
43	FIRMWARE_ID_RLX6_DRAM_BOOT                              = 10,
44	FIRMWARE_ID_GLOBAL_TAP_DELAYS                           = 11,
45	FIRMWARE_ID_SE0_TAP_DELAYS                              = 12,
46	FIRMWARE_ID_SE1_TAP_DELAYS                              = 13,
47	FIRMWARE_ID_GLOBAL_SE0_SE1_SKEW_DELAYS                  = 14,
48	FIRMWARE_ID_SDMA0_UCODE                                 = 15,
49	FIRMWARE_ID_SDMA0_JT                                    = 16,
50	FIRMWARE_ID_SDMA1_UCODE                                 = 17,
51	FIRMWARE_ID_SDMA1_JT                                    = 18,
52	FIRMWARE_ID_CP_CE                                       = 19,
53	FIRMWARE_ID_CP_PFP                                      = 20,
54	FIRMWARE_ID_CP_ME                                       = 21,
55	FIRMWARE_ID_CP_MEC                                      = 22,
56	FIRMWARE_ID_CP_MES                                      = 23,
57	FIRMWARE_ID_MES_STACK                                   = 24,
58	FIRMWARE_ID_RLC_SRM_DRAM_SR                             = 25,
59	FIRMWARE_ID_RLCG_SCRATCH_SR                             = 26,
60	FIRMWARE_ID_RLCP_SCRATCH_SR                             = 27,
61	FIRMWARE_ID_RLCV_SCRATCH_SR                             = 28,
62	FIRMWARE_ID_RLX6_DRAM_SR                                = 29,
63	FIRMWARE_ID_SDMA0_PG_CONTEXT                            = 30,
64	FIRMWARE_ID_SDMA1_PG_CONTEXT                            = 31,
65	FIRMWARE_ID_GLOBAL_MUX_SELECT_RAM                       = 32,
66	FIRMWARE_ID_SE0_MUX_SELECT_RAM                          = 33,
67	FIRMWARE_ID_SE1_MUX_SELECT_RAM                          = 34,
68	FIRMWARE_ID_ACCUM_CTRL_RAM                              = 35,
69	FIRMWARE_ID_RLCP_CAM                                    = 36,
70	FIRMWARE_ID_RLC_SPP_CAM_EXT                             = 37,
71	FIRMWARE_ID_MAX                                         = 38,
72} FIRMWARE_ID;
73
74typedef struct _RLC_TABLE_OF_CONTENT {
75	union {
76		unsigned int	DW0;
77		struct {
78			unsigned int	offset		: 25;
79			unsigned int	id		: 7;
80		};
81	};
82
83	union {
84		unsigned int	DW1;
85		struct {
86			unsigned int	load_at_boot		: 1;
87			unsigned int	load_at_vddgfx		: 1;
88			unsigned int	load_at_reset		: 1;
89			unsigned int	memory_destination	: 2;
90			unsigned int	vfflr_image_code	: 4;
91			unsigned int	load_mode_direct	: 1;
92			unsigned int	save_for_vddgfx		: 1;
93			unsigned int	save_for_vfflr		: 1;
94			unsigned int	reserved		: 1;
95			unsigned int	signed_source		: 1;
96			unsigned int	size			: 18;
97		};
98	};
99
100	union {
101		unsigned int	DW2;
102		struct {
103			unsigned int	indirect_addr_reg	: 16;
104			unsigned int	index			: 16;
105		};
106	};
107
108	union {
109		unsigned int	DW3;
110		struct {
111			unsigned int	indirect_data_reg	: 16;
112			unsigned int	indirect_start_offset	: 16;
113		};
114	};
115} RLC_TABLE_OF_CONTENT;
116
117#define RLC_TOC_MAX_SIZE		64
118
119struct amdgpu_rlc_funcs {
120	bool (*is_rlc_enabled)(struct amdgpu_device *adev);
121	void (*set_safe_mode)(struct amdgpu_device *adev);
122	void (*unset_safe_mode)(struct amdgpu_device *adev);
123	int  (*init)(struct amdgpu_device *adev);
124	u32  (*get_csb_size)(struct amdgpu_device *adev);
125	void (*get_csb_buffer)(struct amdgpu_device *adev, volatile u32 *buffer);
126	int  (*get_cp_table_num)(struct amdgpu_device *adev);
127	int  (*resume)(struct amdgpu_device *adev);
128	void (*stop)(struct amdgpu_device *adev);
129	void (*reset)(struct amdgpu_device *adev);
130	void (*start)(struct amdgpu_device *adev);
131};
132
133struct amdgpu_rlc {
134	/* for power gating */
135	struct amdgpu_bo        *save_restore_obj;
136	uint64_t                save_restore_gpu_addr;
137	volatile uint32_t       *sr_ptr;
138	const u32               *reg_list;
139	u32                     reg_list_size;
140	/* for clear state */
141	struct amdgpu_bo        *clear_state_obj;
142	uint64_t                clear_state_gpu_addr;
143	volatile uint32_t       *cs_ptr;
144	const struct cs_section_def   *cs_data;
145	u32                     clear_state_size;
146	/* for cp tables */
147	struct amdgpu_bo        *cp_table_obj;
148	uint64_t                cp_table_gpu_addr;
149	volatile uint32_t       *cp_table_ptr;
150	u32                     cp_table_size;
151
152	/* safe mode for updating CG/PG state */
153	bool in_safe_mode;
154	const struct amdgpu_rlc_funcs *funcs;
155
156	/* for firmware data */
157	u32 save_and_restore_offset;
158	u32 clear_state_descriptor_offset;
159	u32 avail_scratch_ram_locations;
160	u32 reg_restore_list_size;
161	u32 reg_list_format_start;
162	u32 reg_list_format_separate_start;
163	u32 starting_offsets_start;
164	u32 reg_list_format_size_bytes;
165	u32 reg_list_size_bytes;
166	u32 reg_list_format_direct_reg_list_length;
167	u32 save_restore_list_cntl_size_bytes;
168	u32 save_restore_list_gpm_size_bytes;
169	u32 save_restore_list_srm_size_bytes;
170
171	u32 *register_list_format;
172	u32 *register_restore;
173	const u8 *save_restore_list_cntl;
174	const u8 *save_restore_list_gpm;
175	const u8 *save_restore_list_srm;
176
177	bool is_rlc_v2_1;
178
179	/* for rlc autoload */
180	struct amdgpu_bo	*rlc_autoload_bo;
181	u64			rlc_autoload_gpu_addr;
182	void			*rlc_autoload_ptr;
183
184	/* rlc toc buffer */
185	struct amdgpu_bo	*rlc_toc_bo;
186	uint64_t		rlc_toc_gpu_addr;
187	void			*rlc_toc_buf;
188};
189
190void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev);
191void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev);
192int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev, u32 dws);
193int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev);
194int amdgpu_gfx_rlc_init_cpt(struct amdgpu_device *adev);
195void amdgpu_gfx_rlc_setup_cp_table(struct amdgpu_device *adev);
196void amdgpu_gfx_rlc_fini(struct amdgpu_device *adev);
197
198#endif
199