1/* $NetBSD: amdgpu_fence.c,v 1.11 2023/07/20 18:02:45 mrg Exp $ */ 2 3/* 4 * Copyright 2009 Jerome Glisse. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * The above copyright notice and this permission notice (including the 24 * next paragraph) shall be included in all copies or substantial portions 25 * of the Software. 26 * 27 */ 28/* 29 * Authors: 30 * Jerome Glisse <glisse@freedesktop.org> 31 * Dave Airlie 32 */ 33#include <sys/cdefs.h> 34__KERNEL_RCSID(0, "$NetBSD: amdgpu_fence.c,v 1.11 2023/07/20 18:02:45 mrg Exp $"); 35 36#include <linux/seq_file.h> 37#include <linux/atomic.h> 38#include <linux/wait.h> 39#include <linux/kref.h> 40#include <linux/slab.h> 41#include <linux/firmware.h> 42#include <linux/pm_runtime.h> 43 44#include <drm/drm_debugfs.h> 45 46#include "amdgpu.h" 47#include "amdgpu_trace.h" 48 49#include <linux/nbsd-namespace.h> 50 51/* 52 * Fences 53 * Fences mark an event in the GPUs pipeline and are used 54 * for GPU/CPU synchronization. When the fence is written, 55 * it is expected that all buffers associated with that fence 56 * are no longer in use by the associated ring on the GPU and 57 * that the the relevant GPU caches have been flushed. 58 */ 59 60struct amdgpu_fence { 61 struct dma_fence base; 62 63 /* RB, DMA, etc. */ 64 struct amdgpu_ring *ring; 65}; 66 67static struct kmem_cache *amdgpu_fence_slab; 68 69int amdgpu_fence_slab_init(void) 70{ 71 amdgpu_fence_slab = kmem_cache_create( 72 "amdgpu_fence", sizeof(struct amdgpu_fence), 0, 73 SLAB_HWCACHE_ALIGN, NULL); 74 if (!amdgpu_fence_slab) 75 return -ENOMEM; 76 return 0; 77} 78 79void amdgpu_fence_slab_fini(void) 80{ 81 rcu_barrier(); 82 kmem_cache_destroy(amdgpu_fence_slab); 83} 84/* 85 * Cast helper 86 */ 87static const struct dma_fence_ops amdgpu_fence_ops; 88static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence *f) 89{ 90 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); 91 92 if (__f->base.ops == &amdgpu_fence_ops) 93 return __f; 94 95 return NULL; 96} 97 98/** 99 * amdgpu_fence_write - write a fence value 100 * 101 * @ring: ring the fence is associated with 102 * @seq: sequence number to write 103 * 104 * Writes a fence value to memory (all asics). 105 */ 106static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq) 107{ 108 struct amdgpu_fence_driver *drv = &ring->fence_drv; 109 110 if (drv->cpu_addr) 111 *drv->cpu_addr = cpu_to_le32(seq); 112} 113 114/** 115 * amdgpu_fence_read - read a fence value 116 * 117 * @ring: ring the fence is associated with 118 * 119 * Reads a fence value from memory (all asics). 120 * Returns the value of the fence read from memory. 121 */ 122static u32 amdgpu_fence_read(struct amdgpu_ring *ring) 123{ 124 struct amdgpu_fence_driver *drv = &ring->fence_drv; 125 u32 seq = 0; 126 127 if (drv->cpu_addr) 128 seq = le32_to_cpu(*drv->cpu_addr); 129 else 130 seq = atomic_read(&drv->last_seq); 131 132 return seq; 133} 134 135/** 136 * amdgpu_fence_emit - emit a fence on the requested ring 137 * 138 * @ring: ring the fence is associated with 139 * @f: resulting fence object 140 * 141 * Emits a fence command on the requested ring (all asics). 142 * Returns 0 on success, -ENOMEM on failure. 143 */ 144int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, 145 unsigned flags) 146{ 147 struct amdgpu_device *adev = ring->adev; 148 struct amdgpu_fence *fence; 149 struct dma_fence __rcu **ptr; 150 uint32_t seq; 151 int r; 152 153 fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL); 154 if (fence == NULL) 155 return -ENOMEM; 156 157 seq = ++ring->fence_drv.sync_seq; 158 fence->ring = ring; 159 dma_fence_init(&fence->base, &amdgpu_fence_ops, 160 &ring->fence_drv.lock, 161 adev->fence_context + ring->idx, 162 seq); 163 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, 164 seq, flags | AMDGPU_FENCE_FLAG_INT); 165 pm_runtime_get_noresume(adev->ddev->dev); 166 ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask]; 167 if (unlikely(rcu_dereference_protected(*ptr, 1))) { 168 struct dma_fence *old; 169 170 rcu_read_lock(); 171 old = dma_fence_get_rcu_safe(ptr); 172 rcu_read_unlock(); 173 174 if (old) { 175 r = dma_fence_wait(old, false); 176 dma_fence_put(old); 177 if (r) 178 return r; 179 } 180 } 181 182 /* This function can't be called concurrently anyway, otherwise 183 * emitting the fence would mess up the hardware ring buffer. 184 */ 185 rcu_assign_pointer(*ptr, dma_fence_get(&fence->base)); 186 187 *f = &fence->base; 188 189 return 0; 190} 191 192/** 193 * amdgpu_fence_emit_polling - emit a fence on the requeste ring 194 * 195 * @ring: ring the fence is associated with 196 * @s: resulting sequence number 197 * 198 * Emits a fence command on the requested ring (all asics). 199 * Used For polling fence. 200 * Returns 0 on success, -ENOMEM on failure. 201 */ 202int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s) 203{ 204 uint32_t seq; 205 206 if (!s) 207 return -EINVAL; 208 209 seq = ++ring->fence_drv.sync_seq; 210 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, 211 seq, 0); 212 213 *s = seq; 214 215 return 0; 216} 217 218/** 219 * amdgpu_fence_schedule_fallback - schedule fallback check 220 * 221 * @ring: pointer to struct amdgpu_ring 222 * 223 * Start a timer as fallback to our interrupts. 224 */ 225static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring) 226{ 227 mod_timer(&ring->fence_drv.fallback_timer, 228 jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT); 229} 230 231/** 232 * amdgpu_fence_process - check for fence activity 233 * 234 * @ring: pointer to struct amdgpu_ring 235 * 236 * Checks the current fence value and calculates the last 237 * signalled fence value. Wakes the fence queue if the 238 * sequence number has increased. 239 * 240 * Returns true if fence was processed 241 */ 242bool amdgpu_fence_process(struct amdgpu_ring *ring) 243{ 244 struct amdgpu_fence_driver *drv = &ring->fence_drv; 245 struct amdgpu_device *adev = ring->adev; 246 uint32_t seq, last_seq; 247 int r; 248 249 do { 250 last_seq = atomic_read(&ring->fence_drv.last_seq); 251 seq = amdgpu_fence_read(ring); 252 253 } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq); 254 255 if (del_timer(&ring->fence_drv.fallback_timer) && 256 seq != ring->fence_drv.sync_seq) 257 amdgpu_fence_schedule_fallback(ring); 258 259 if (unlikely(seq == last_seq)) 260 return false; 261 262 last_seq &= drv->num_fences_mask; 263 seq &= drv->num_fences_mask; 264 265 do { 266 struct dma_fence *fence, **ptr; 267 268 ++last_seq; 269 last_seq &= drv->num_fences_mask; 270 ptr = &drv->fences[last_seq]; 271 272 /* There is always exactly one thread signaling this fence slot */ 273 fence = rcu_dereference_protected(*ptr, 1); 274 RCU_INIT_POINTER(*ptr, NULL); 275 276 if (!fence) 277 continue; 278 279 r = dma_fence_signal(fence); 280 if (!r) 281 DMA_FENCE_TRACE(fence, "signaled from irq context\n"); 282 else 283 BUG(); 284 285 dma_fence_put(fence); 286 pm_runtime_mark_last_busy(adev->ddev->dev); 287 pm_runtime_put_autosuspend(adev->ddev->dev); 288 } while (last_seq != seq); 289 290 return true; 291} 292 293/** 294 * amdgpu_fence_fallback - fallback for hardware interrupts 295 * 296 * @work: delayed work item 297 * 298 * Checks for fence activity. 299 */ 300static void amdgpu_fence_fallback(struct timer_list *t) 301{ 302 struct amdgpu_ring *ring = from_timer(ring, t, 303 fence_drv.fallback_timer); 304 305 if (amdgpu_fence_process(ring)) 306 DRM_WARN("Fence fallback timer expired on ring %s\n", ring->name); 307} 308 309/** 310 * amdgpu_fence_wait_empty - wait for all fences to signal 311 * 312 * @adev: amdgpu device pointer 313 * @ring: ring index the fence is associated with 314 * 315 * Wait for all fences on the requested ring to signal (all asics). 316 * Returns 0 if the fences have passed, error for all other cases. 317 */ 318int amdgpu_fence_wait_empty(struct amdgpu_ring *ring) 319{ 320 uint64_t seq = READ_ONCE(ring->fence_drv.sync_seq); 321 struct dma_fence *fence, **ptr; 322 int r; 323 324 if (!seq) 325 return 0; 326 327 ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask]; 328 rcu_read_lock(); 329 fence = rcu_dereference(*ptr); 330 if (!fence || !dma_fence_get_rcu(fence)) { 331 rcu_read_unlock(); 332 return 0; 333 } 334 rcu_read_unlock(); 335 336 r = dma_fence_wait(fence, false); 337 dma_fence_put(fence); 338 return r; 339} 340 341/** 342 * amdgpu_fence_wait_polling - busy wait for givn sequence number 343 * 344 * @ring: ring index the fence is associated with 345 * @wait_seq: sequence number to wait 346 * @timeout: the timeout for waiting in usecs 347 * 348 * Wait for all fences on the requested ring to signal (all asics). 349 * Returns left time if no timeout, 0 or minus if timeout. 350 */ 351signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring, 352 uint32_t wait_seq, 353 signed long timeout) 354{ 355 uint32_t seq; 356 357 do { 358 seq = amdgpu_fence_read(ring); 359 udelay(5); 360 timeout -= 5; 361 } while ((int32_t)(wait_seq - seq) > 0 && timeout > 0); 362 363 return timeout > 0 ? timeout : 0; 364} 365/** 366 * amdgpu_fence_count_emitted - get the count of emitted fences 367 * 368 * @ring: ring the fence is associated with 369 * 370 * Get the number of fences emitted on the requested ring (all asics). 371 * Returns the number of emitted fences on the ring. Used by the 372 * dynpm code to ring track activity. 373 */ 374unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring) 375{ 376 uint64_t emitted; 377 378 /* We are not protected by ring lock when reading the last sequence 379 * but it's ok to report slightly wrong fence count here. 380 */ 381 amdgpu_fence_process(ring); 382 emitted = 0x100000000ull; 383 emitted -= atomic_read(&ring->fence_drv.last_seq); 384 emitted += READ_ONCE(ring->fence_drv.sync_seq); 385 return lower_32_bits(emitted); 386} 387 388/** 389 * amdgpu_fence_driver_start_ring - make the fence driver 390 * ready for use on the requested ring. 391 * 392 * @ring: ring to start the fence driver on 393 * @irq_src: interrupt source to use for this ring 394 * @irq_type: interrupt type to use for this ring 395 * 396 * Make the fence driver ready for processing (all asics). 397 * Not all asics have all rings, so each asic will only 398 * start the fence driver on the rings it has. 399 * Returns 0 for success, errors for failure. 400 */ 401int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 402 struct amdgpu_irq_src *irq_src, 403 unsigned irq_type) 404{ 405 struct amdgpu_device *adev = ring->adev; 406 uint64_t index; 407 408 if (ring->funcs->type != AMDGPU_RING_TYPE_UVD) { 409 ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs]; 410 ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4); 411 } else { 412 /* put fence directly behind firmware */ 413 index = ALIGN(adev->uvd.fw->size, 8); 414 ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index; 415 ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index; 416 } 417 amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq)); 418 amdgpu_irq_get(adev, irq_src, irq_type); 419 420 ring->fence_drv.irq_src = irq_src; 421 ring->fence_drv.irq_type = irq_type; 422 ring->fence_drv.initialized = true; 423 424 DRM_DEV_DEBUG(adev->dev, "fence driver on ring %s use gpu addr " 425 "0x%016"PRIx64", cpu addr 0x%p\n", ring->name, 426 ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr); 427 return 0; 428} 429 430/** 431 * amdgpu_fence_driver_init_ring - init the fence driver 432 * for the requested ring. 433 * 434 * @ring: ring to init the fence driver on 435 * @num_hw_submission: number of entries on the hardware queue 436 * 437 * Init the fence driver for the requested ring (all asics). 438 * Helper function for amdgpu_fence_driver_init(). 439 */ 440int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, 441 unsigned num_hw_submission) 442{ 443 struct amdgpu_device *adev = ring->adev; 444 long timeout; 445 int r; 446 447 if (!adev) 448 return -EINVAL; 449 450 /* Check that num_hw_submission is a power of two */ 451 if ((num_hw_submission & (num_hw_submission - 1)) != 0) 452 return -EINVAL; 453 454 ring->fence_drv.cpu_addr = NULL; 455 ring->fence_drv.gpu_addr = 0; 456 ring->fence_drv.sync_seq = 0; 457 atomic_set(&ring->fence_drv.last_seq, 0); 458 ring->fence_drv.initialized = false; 459 460 timer_setup(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 0); 461 462 ring->fence_drv.num_fences_mask = num_hw_submission * 2 - 1; 463 spin_lock_init(&ring->fence_drv.lock); 464 ring->fence_drv.fences = kcalloc(num_hw_submission * 2, sizeof(void *), 465 GFP_KERNEL); 466 if (!ring->fence_drv.fences) 467 return -ENOMEM; 468 469 /* No need to setup the GPU scheduler for KIQ ring */ 470 if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) { 471 switch (ring->funcs->type) { 472 case AMDGPU_RING_TYPE_GFX: 473 timeout = adev->gfx_timeout; 474 break; 475 case AMDGPU_RING_TYPE_COMPUTE: 476 timeout = adev->compute_timeout; 477 break; 478 case AMDGPU_RING_TYPE_SDMA: 479 timeout = adev->sdma_timeout; 480 break; 481 default: 482 timeout = adev->video_timeout; 483 break; 484 } 485 486 r = drm_sched_init(&ring->sched, &amdgpu_sched_ops, 487 num_hw_submission, amdgpu_job_hang_limit, 488 timeout, ring->name); 489 if (r) { 490 DRM_ERROR("Failed to create scheduler on ring %s.\n", 491 ring->name); 492 return r; 493 } 494 } 495 496 return 0; 497} 498 499/** 500 * amdgpu_fence_driver_init - init the fence driver 501 * for all possible rings. 502 * 503 * @adev: amdgpu device pointer 504 * 505 * Init the fence driver for all possible rings (all asics). 506 * Not all asics have all rings, so each asic will only 507 * start the fence driver on the rings it has using 508 * amdgpu_fence_driver_start_ring(). 509 * Returns 0 for success. 510 */ 511int amdgpu_fence_driver_init(struct amdgpu_device *adev) 512{ 513 if (amdgpu_debugfs_fence_init(adev)) 514 dev_err(adev->dev, "fence debugfs file creation failed\n"); 515 516 return 0; 517} 518 519/** 520 * amdgpu_fence_driver_fini - tear down the fence driver 521 * for all possible rings. 522 * 523 * @adev: amdgpu device pointer 524 * 525 * Tear down the fence driver for all possible rings (all asics). 526 */ 527void amdgpu_fence_driver_fini(struct amdgpu_device *adev) 528{ 529 unsigned i, j; 530 int r; 531 532 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 533 struct amdgpu_ring *ring = adev->rings[i]; 534 535 if (!ring || !ring->fence_drv.initialized) 536 continue; 537 r = amdgpu_fence_wait_empty(ring); 538 if (r) { 539 /* no need to trigger GPU reset as we are unloading */ 540 amdgpu_fence_driver_force_completion(ring); 541 } 542 amdgpu_irq_put(adev, ring->fence_drv.irq_src, 543 ring->fence_drv.irq_type); 544 if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) { 545 drm_sched_fini(&ring->sched); 546 } 547 del_timer_sync(&ring->fence_drv.fallback_timer); 548 for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j) 549 dma_fence_put(ring->fence_drv.fences[j]); 550 kfree(ring->fence_drv.fences); 551 ring->fence_drv.fences = NULL; 552 ring->fence_drv.initialized = false; 553 spin_lock_destroy(&ring->fence_drv.lock); 554 } 555} 556 557/** 558 * amdgpu_fence_driver_suspend - suspend the fence driver 559 * for all possible rings. 560 * 561 * @adev: amdgpu device pointer 562 * 563 * Suspend the fence driver for all possible rings (all asics). 564 */ 565void amdgpu_fence_driver_suspend(struct amdgpu_device *adev) 566{ 567 int i, r; 568 569 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 570 struct amdgpu_ring *ring = adev->rings[i]; 571 if (!ring || !ring->fence_drv.initialized) 572 continue; 573 574 /* wait for gpu to finish processing current batch */ 575 r = amdgpu_fence_wait_empty(ring); 576 if (r) { 577 /* delay GPU reset to resume */ 578 amdgpu_fence_driver_force_completion(ring); 579 } 580 581 /* disable the interrupt */ 582 amdgpu_irq_put(adev, ring->fence_drv.irq_src, 583 ring->fence_drv.irq_type); 584 } 585} 586 587/** 588 * amdgpu_fence_driver_resume - resume the fence driver 589 * for all possible rings. 590 * 591 * @adev: amdgpu device pointer 592 * 593 * Resume the fence driver for all possible rings (all asics). 594 * Not all asics have all rings, so each asic will only 595 * start the fence driver on the rings it has using 596 * amdgpu_fence_driver_start_ring(). 597 * Returns 0 for success. 598 */ 599void amdgpu_fence_driver_resume(struct amdgpu_device *adev) 600{ 601 int i; 602 603 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 604 struct amdgpu_ring *ring = adev->rings[i]; 605 if (!ring || !ring->fence_drv.initialized) 606 continue; 607 608 /* enable the interrupt */ 609 amdgpu_irq_get(adev, ring->fence_drv.irq_src, 610 ring->fence_drv.irq_type); 611 } 612} 613 614/** 615 * amdgpu_fence_driver_force_completion - force signal latest fence of ring 616 * 617 * @ring: fence of the ring to signal 618 * 619 */ 620void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring) 621{ 622 amdgpu_fence_write(ring, ring->fence_drv.sync_seq); 623 amdgpu_fence_process(ring); 624} 625 626/* 627 * Common fence implementation 628 */ 629 630static const char *amdgpu_fence_get_driver_name(struct dma_fence *fence) 631{ 632 return "amdgpu"; 633} 634 635static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f) 636{ 637 struct amdgpu_fence *fence = to_amdgpu_fence(f); 638 return (const char *)fence->ring->name; 639} 640 641/** 642 * amdgpu_fence_enable_signaling - enable signalling on fence 643 * @fence: fence 644 * 645 * This function is called with fence_queue lock held, and adds a callback 646 * to fence_queue that checks if this fence is signaled, and if so it 647 * signals the fence and removes itself. 648 */ 649static bool amdgpu_fence_enable_signaling(struct dma_fence *f) 650{ 651 struct amdgpu_fence *fence = to_amdgpu_fence(f); 652 struct amdgpu_ring *ring = fence->ring; 653 654 if (!timer_pending(&ring->fence_drv.fallback_timer)) 655 amdgpu_fence_schedule_fallback(ring); 656 657 DMA_FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx); 658 659 return true; 660} 661 662/** 663 * amdgpu_fence_free - free up the fence memory 664 * 665 * @rcu: RCU callback head 666 * 667 * Free up the fence memory after the RCU grace period. 668 */ 669static void amdgpu_fence_free(struct rcu_head *rcu) 670{ 671 struct dma_fence *f = container_of(rcu, struct dma_fence, rcu); 672 struct amdgpu_fence *fence = to_amdgpu_fence(f); 673 dma_fence_destroy(f); 674 kmem_cache_free(amdgpu_fence_slab, fence); 675} 676 677/** 678 * amdgpu_fence_release - callback that fence can be freed 679 * 680 * @fence: fence 681 * 682 * This function is called when the reference count becomes zero. 683 * It just RCU schedules freeing up the fence. 684 */ 685static void amdgpu_fence_release(struct dma_fence *f) 686{ 687 call_rcu(&f->rcu, amdgpu_fence_free); 688} 689 690static const struct dma_fence_ops amdgpu_fence_ops = { 691 .get_driver_name = amdgpu_fence_get_driver_name, 692 .get_timeline_name = amdgpu_fence_get_timeline_name, 693 .enable_signaling = amdgpu_fence_enable_signaling, 694 .release = amdgpu_fence_release, 695}; 696 697/* 698 * Fence debugfs 699 */ 700#if defined(CONFIG_DEBUG_FS) 701static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data) 702{ 703 struct drm_info_node *node = (struct drm_info_node *)m->private; 704 struct drm_device *dev = node->minor->dev; 705 struct amdgpu_device *adev = dev->dev_private; 706 int i; 707 708 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 709 struct amdgpu_ring *ring = adev->rings[i]; 710 if (!ring || !ring->fence_drv.initialized) 711 continue; 712 713 amdgpu_fence_process(ring); 714 715 seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name); 716 seq_printf(m, "Last signaled fence 0x%08x\n", 717 atomic_read(&ring->fence_drv.last_seq)); 718 seq_printf(m, "Last emitted 0x%08x\n", 719 ring->fence_drv.sync_seq); 720 721 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX || 722 ring->funcs->type == AMDGPU_RING_TYPE_SDMA) { 723 seq_printf(m, "Last signaled trailing fence 0x%08x\n", 724 le32_to_cpu(*ring->trail_fence_cpu_addr)); 725 seq_printf(m, "Last emitted 0x%08x\n", 726 ring->trail_seq); 727 } 728 729 if (ring->funcs->type != AMDGPU_RING_TYPE_GFX) 730 continue; 731 732 /* set in CP_VMID_PREEMPT and preemption occurred */ 733 seq_printf(m, "Last preempted 0x%08x\n", 734 le32_to_cpu(*(ring->fence_drv.cpu_addr + 2))); 735 /* set in CP_VMID_RESET and reset occurred */ 736 seq_printf(m, "Last reset 0x%08x\n", 737 le32_to_cpu(*(ring->fence_drv.cpu_addr + 4))); 738 /* Both preemption and reset occurred */ 739 seq_printf(m, "Last both 0x%08x\n", 740 le32_to_cpu(*(ring->fence_drv.cpu_addr + 6))); 741 } 742 return 0; 743} 744 745/** 746 * amdgpu_debugfs_gpu_recover - manually trigger a gpu reset & recover 747 * 748 * Manually trigger a gpu reset at the next fence wait. 749 */ 750static int amdgpu_debugfs_gpu_recover(struct seq_file *m, void *data) 751{ 752 struct drm_info_node *node = (struct drm_info_node *) m->private; 753 struct drm_device *dev = node->minor->dev; 754 struct amdgpu_device *adev = dev->dev_private; 755 int r; 756 757 r = pm_runtime_get_sync(dev->dev); 758 if (r < 0) 759 return 0; 760 761 seq_printf(m, "gpu recover\n"); 762 amdgpu_device_gpu_recover(adev, NULL); 763 764 pm_runtime_mark_last_busy(dev->dev); 765 pm_runtime_put_autosuspend(dev->dev); 766 767 return 0; 768} 769 770static const struct drm_info_list amdgpu_debugfs_fence_list[] = { 771 {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL}, 772 {"amdgpu_gpu_recover", &amdgpu_debugfs_gpu_recover, 0, NULL} 773}; 774 775static const struct drm_info_list amdgpu_debugfs_fence_list_sriov[] = { 776 {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL}, 777}; 778#endif 779 780int amdgpu_debugfs_fence_init(struct amdgpu_device *adev) 781{ 782#if defined(CONFIG_DEBUG_FS) 783 if (amdgpu_sriov_vf(adev)) 784 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list_sriov, 1); 785 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 2); 786#else 787 return 0; 788#endif 789} 790 791