1/* r128_drv.h -- Private header for r128 driver -*- linux-c -*- 2 * Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com 3 */ 4/* 5 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 6 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 7 * All rights reserved. 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a 10 * copy of this software and associated documentation files (the "Software"), 11 * to deal in the Software without restriction, including without limitation 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the 14 * Software is furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the next 17 * paragraph) shall be included in all copies or substantial portions of the 18 * Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 * 28 * Authors: 29 * Rickard E. (Rik) Faith <faith@valinux.com> 30 * Kevin E. Martin <martin@valinux.com> 31 * Gareth Hughes <gareth@valinux.com> 32 * Michel D���zer <daenzerm@student.ethz.ch> 33 */ 34 35#ifndef __R128_DRV_H__ 36#define __R128_DRV_H__ 37 38/* General customization: 39 */ 40#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc." 41 42#define DRIVER_NAME "r128" 43#define DRIVER_DESC "ATI Rage 128" 44#define DRIVER_DATE "20030725" 45 46/* Interface history: 47 * 48 * ?? - ?? 49 * 2.4 - Add support for ycbcr textures (no new ioctls) 50 * 2.5 - Add FLIP ioctl, disable FULLSCREEN. 51 */ 52#define DRIVER_MAJOR 2 53#define DRIVER_MINOR 5 54#define DRIVER_PATCHLEVEL 0 55 56#define GET_RING_HEAD(dev_priv) R128_READ( R128_PM4_BUFFER_DL_RPTR ) 57 58typedef struct drm_r128_freelist { 59 unsigned int age; 60 struct drm_buf *buf; 61 struct drm_r128_freelist *next; 62 struct drm_r128_freelist *prev; 63} drm_r128_freelist_t; 64 65typedef struct drm_r128_ring_buffer { 66 u32 *start; 67 u32 *end; 68 int size; 69 int size_l2qw; 70 71 u32 tail; 72 u32 tail_mask; 73 int space; 74 75 int high_mark; 76} drm_r128_ring_buffer_t; 77 78typedef struct drm_r128_private { 79 drm_r128_ring_buffer_t ring; 80 drm_r128_sarea_t *sarea_priv; 81 82 int cce_mode; 83 int cce_fifo_size; 84 int cce_running; 85 86 drm_r128_freelist_t *head; 87 drm_r128_freelist_t *tail; 88 89 int usec_timeout; 90 int is_pci; 91 unsigned long cce_buffers_offset; 92 93 atomic_t idle_count; 94 95 int page_flipping; 96 int current_page; 97 u32 crtc_offset; 98 u32 crtc_offset_cntl; 99 100 atomic_t vbl_received; 101 102 u32 color_fmt; 103 unsigned int front_offset; 104 unsigned int front_pitch; 105 unsigned int back_offset; 106 unsigned int back_pitch; 107 108 u32 depth_fmt; 109 unsigned int depth_offset; 110 unsigned int depth_pitch; 111 unsigned int span_offset; 112 113 u32 front_pitch_offset_c; 114 u32 back_pitch_offset_c; 115 u32 depth_pitch_offset_c; 116 u32 span_pitch_offset_c; 117 118 drm_local_map_t *sarea; 119 drm_local_map_t *mmio; 120 drm_local_map_t *cce_ring; 121 drm_local_map_t *ring_rptr; 122 drm_local_map_t *agp_textures; 123 struct drm_ati_pcigart_info gart_info; 124} drm_r128_private_t; 125 126typedef struct drm_r128_buf_priv { 127 u32 age; 128 int prim; 129 int discard; 130 int dispatched; 131 drm_r128_freelist_t *list_entry; 132} drm_r128_buf_priv_t; 133 134extern struct drm_ioctl_desc r128_ioctls[]; 135extern int r128_max_ioctl; 136 137 /* r128_cce.c */ 138extern int r128_cce_init(struct drm_device *dev, void *data, struct drm_file *file_priv); 139extern int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_priv); 140extern int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv); 141extern int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 142extern int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv); 143extern int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 144extern int r128_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv); 145extern int r128_cce_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); 146 147extern void r128_freelist_reset(struct drm_device * dev); 148 149extern int r128_wait_ring(drm_r128_private_t * dev_priv, int n); 150 151extern int r128_do_cce_idle(drm_r128_private_t * dev_priv); 152extern int r128_do_cleanup_cce(struct drm_device * dev); 153 154extern int r128_enable_vblank(struct drm_device *dev, unsigned int crtc); 155extern void r128_disable_vblank(struct drm_device *dev, unsigned int crtc); 156extern u32 r128_get_vblank_counter(struct drm_device *dev, unsigned int crtc); 157extern irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS); 158extern void r128_driver_irq_preinstall(struct drm_device * dev); 159extern int r128_driver_irq_postinstall(struct drm_device * dev); 160extern void r128_driver_irq_uninstall(struct drm_device * dev); 161extern void r128_driver_lastclose(struct drm_device * dev); 162extern int r128_driver_load(struct drm_device * dev, unsigned long flags); 163extern void r128_driver_preclose(struct drm_device * dev, 164 struct drm_file *file_priv); 165 166extern long r128_compat_ioctl(struct file *filp, unsigned int cmd, 167 unsigned long arg); 168 169/* Register definitions, register access macros and drmAddMap constants 170 * for Rage 128 kernel driver. 171 */ 172 173#define R128_AUX_SC_CNTL 0x1660 174# define R128_AUX1_SC_EN (1 << 0) 175# define R128_AUX1_SC_MODE_OR (0 << 1) 176# define R128_AUX1_SC_MODE_NAND (1 << 1) 177# define R128_AUX2_SC_EN (1 << 2) 178# define R128_AUX2_SC_MODE_OR (0 << 3) 179# define R128_AUX2_SC_MODE_NAND (1 << 3) 180# define R128_AUX3_SC_EN (1 << 4) 181# define R128_AUX3_SC_MODE_OR (0 << 5) 182# define R128_AUX3_SC_MODE_NAND (1 << 5) 183#define R128_AUX1_SC_LEFT 0x1664 184#define R128_AUX1_SC_RIGHT 0x1668 185#define R128_AUX1_SC_TOP 0x166c 186#define R128_AUX1_SC_BOTTOM 0x1670 187#define R128_AUX2_SC_LEFT 0x1674 188#define R128_AUX2_SC_RIGHT 0x1678 189#define R128_AUX2_SC_TOP 0x167c 190#define R128_AUX2_SC_BOTTOM 0x1680 191#define R128_AUX3_SC_LEFT 0x1684 192#define R128_AUX3_SC_RIGHT 0x1688 193#define R128_AUX3_SC_TOP 0x168c 194#define R128_AUX3_SC_BOTTOM 0x1690 195 196#define R128_BRUSH_DATA0 0x1480 197#define R128_BUS_CNTL 0x0030 198# define R128_BUS_MASTER_DIS (1 << 6) 199 200#define R128_CLOCK_CNTL_INDEX 0x0008 201#define R128_CLOCK_CNTL_DATA 0x000c 202# define R128_PLL_WR_EN (1 << 7) 203#define R128_CONSTANT_COLOR_C 0x1d34 204#define R128_CRTC_OFFSET 0x0224 205#define R128_CRTC_OFFSET_CNTL 0x0228 206# define R128_CRTC_OFFSET_FLIP_CNTL (1 << 16) 207 208#define R128_DP_GUI_MASTER_CNTL 0x146c 209# define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 210# define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 211# define R128_GMC_BRUSH_SOLID_COLOR (13 << 4) 212# define R128_GMC_BRUSH_NONE (15 << 4) 213# define R128_GMC_DST_16BPP (4 << 8) 214# define R128_GMC_DST_24BPP (5 << 8) 215# define R128_GMC_DST_32BPP (6 << 8) 216# define R128_GMC_DST_DATATYPE_SHIFT 8 217# define R128_GMC_SRC_DATATYPE_COLOR (3 << 12) 218# define R128_DP_SRC_SOURCE_MEMORY (2 << 24) 219# define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24) 220# define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28) 221# define R128_GMC_AUX_CLIP_DIS (1 << 29) 222# define R128_GMC_WR_MSK_DIS (1 << 30) 223# define R128_ROP3_S 0x00cc0000 224# define R128_ROP3_P 0x00f00000 225#define R128_DP_WRITE_MASK 0x16cc 226#define R128_DST_PITCH_OFFSET_C 0x1c80 227# define R128_DST_TILE (1 << 31) 228 229#define R128_GEN_INT_CNTL 0x0040 230# define R128_CRTC_VBLANK_INT_EN (1 << 0) 231#define R128_GEN_INT_STATUS 0x0044 232# define R128_CRTC_VBLANK_INT (1 << 0) 233# define R128_CRTC_VBLANK_INT_AK (1 << 0) 234#define R128_GEN_RESET_CNTL 0x00f0 235# define R128_SOFT_RESET_GUI (1 << 0) 236 237#define R128_GUI_SCRATCH_REG0 0x15e0 238#define R128_GUI_SCRATCH_REG1 0x15e4 239#define R128_GUI_SCRATCH_REG2 0x15e8 240#define R128_GUI_SCRATCH_REG3 0x15ec 241#define R128_GUI_SCRATCH_REG4 0x15f0 242#define R128_GUI_SCRATCH_REG5 0x15f4 243 244#define R128_GUI_STAT 0x1740 245# define R128_GUI_FIFOCNT_MASK 0x0fff 246# define R128_GUI_ACTIVE (1 << 31) 247 248#define R128_MCLK_CNTL 0x000f 249# define R128_FORCE_GCP (1 << 16) 250# define R128_FORCE_PIPE3D_CP (1 << 17) 251# define R128_FORCE_RCP (1 << 18) 252 253#define R128_PC_GUI_CTLSTAT 0x1748 254#define R128_PC_NGUI_CTLSTAT 0x0184 255# define R128_PC_FLUSH_GUI (3 << 0) 256# define R128_PC_RI_GUI (1 << 2) 257# define R128_PC_FLUSH_ALL 0x00ff 258# define R128_PC_BUSY (1 << 31) 259 260#define R128_PCI_GART_PAGE 0x017c 261#define R128_PRIM_TEX_CNTL_C 0x1cb0 262 263#define R128_SCALE_3D_CNTL 0x1a00 264#define R128_SEC_TEX_CNTL_C 0x1d00 265#define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c 266#define R128_SETUP_CNTL 0x1bc4 267#define R128_STEN_REF_MASK_C 0x1d40 268 269#define R128_TEX_CNTL_C 0x1c9c 270# define R128_TEX_CACHE_FLUSH (1 << 23) 271 272#define R128_WAIT_UNTIL 0x1720 273# define R128_EVENT_CRTC_OFFSET (1 << 0) 274#define R128_WINDOW_XY_OFFSET 0x1bcc 275 276/* CCE registers 277 */ 278#define R128_PM4_BUFFER_OFFSET 0x0700 279#define R128_PM4_BUFFER_CNTL 0x0704 280# define R128_PM4_MASK (15u << 28) 281# define R128_PM4_NONPM4 (0 << 28) 282# define R128_PM4_192PIO (1 << 28) 283# define R128_PM4_192BM (2 << 28) 284# define R128_PM4_128PIO_64INDBM (3 << 28) 285# define R128_PM4_128BM_64INDBM (4 << 28) 286# define R128_PM4_64PIO_128INDBM (5 << 28) 287# define R128_PM4_64BM_128INDBM (6 << 28) 288# define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28) 289# define R128_PM4_64BM_64VCBM_64INDBM (8u << 28) 290# define R128_PM4_64PIO_64VCPIO_64INDPIO (15u << 28) 291# define R128_PM4_BUFFER_CNTL_NOUPDATE (1 << 27) 292 293#define R128_PM4_BUFFER_WM_CNTL 0x0708 294# define R128_WMA_SHIFT 0 295# define R128_WMB_SHIFT 8 296# define R128_WMC_SHIFT 16 297# define R128_WB_WM_SHIFT 24 298 299#define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c 300#define R128_PM4_BUFFER_DL_RPTR 0x0710 301#define R128_PM4_BUFFER_DL_WPTR 0x0714 302# define R128_PM4_BUFFER_DL_DONE (1 << 31) 303 304#define R128_PM4_VC_FPU_SETUP 0x071c 305 306#define R128_PM4_IW_INDOFF 0x0738 307#define R128_PM4_IW_INDSIZE 0x073c 308 309#define R128_PM4_STAT 0x07b8 310# define R128_PM4_FIFOCNT_MASK 0x0fff 311# define R128_PM4_BUSY (1 << 16) 312# define R128_PM4_GUI_ACTIVE (1 << 31) 313 314#define R128_PM4_MICROCODE_ADDR 0x07d4 315#define R128_PM4_MICROCODE_RADDR 0x07d8 316#define R128_PM4_MICROCODE_DATAH 0x07dc 317#define R128_PM4_MICROCODE_DATAL 0x07e0 318 319#define R128_PM4_BUFFER_ADDR 0x07f0 320#define R128_PM4_MICRO_CNTL 0x07fc 321# define R128_PM4_MICRO_FREERUN (1 << 30) 322 323#define R128_PM4_FIFO_DATA_EVEN 0x1000 324#define R128_PM4_FIFO_DATA_ODD 0x1004 325 326/* CCE command packets 327 */ 328#define R128_CCE_PACKET0 0x00000000 329#define R128_CCE_PACKET1 0x40000000 330#define R128_CCE_PACKET2 0x80000000 331#define R128_CCE_PACKET3 0xC0000000 332# define R128_CNTL_HOSTDATA_BLT 0x00009400 333# define R128_CNTL_PAINT_MULTI 0x00009A00 334# define R128_CNTL_BITBLT_MULTI 0x00009B00 335# define R128_3D_RNDR_GEN_INDX_PRIM 0x00002300 336 337#define R128_CCE_PACKET_MASK 0xC0000000 338#define R128_CCE_PACKET_COUNT_MASK 0x3fff0000 339#define R128_CCE_PACKET0_REG_MASK 0x000007ff 340#define R128_CCE_PACKET1_REG0_MASK 0x000007ff 341#define R128_CCE_PACKET1_REG1_MASK 0x003ff800 342 343#define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000 344#define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001 345#define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002 346#define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003 347#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 348#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 349#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 350#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007 351#define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010 352#define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020 353#define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030 354#define R128_CCE_VC_CNTL_NUM_SHIFT 16 355 356#define R128_DATATYPE_VQ 0 357#define R128_DATATYPE_CI4 1 358#define R128_DATATYPE_CI8 2 359#define R128_DATATYPE_ARGB1555 3 360#define R128_DATATYPE_RGB565 4 361#define R128_DATATYPE_RGB888 5 362#define R128_DATATYPE_ARGB8888 6 363#define R128_DATATYPE_RGB332 7 364#define R128_DATATYPE_Y8 8 365#define R128_DATATYPE_RGB8 9 366#define R128_DATATYPE_CI16 10 367#define R128_DATATYPE_YVYU422 11 368#define R128_DATATYPE_VYUY422 12 369#define R128_DATATYPE_AYUV444 14 370#define R128_DATATYPE_ARGB4444 15 371 372/* Constants */ 373#define R128_AGP_OFFSET 0x02000000 374 375#define R128_WATERMARK_L 16 376#define R128_WATERMARK_M 8 377#define R128_WATERMARK_N 8 378#define R128_WATERMARK_K 128 379 380#define R128_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 381 382#define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0 383#define R128_LAST_DISPATCH_REG R128_GUI_SCRATCH_REG1 384#define R128_MAX_VB_AGE 0x7fffffff 385#define R128_MAX_VB_VERTS (0xffff) 386 387#define R128_RING_HIGH_MARK 128 388 389#define R128_PERFORMANCE_BOXES 0 390 391#define R128_PCIGART_TABLE_SIZE 32768 392 393#define R128_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) 394#define R128_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) 395#define R128_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 396#define R128_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) 397 398#define R128_WRITE_PLL(addr,val) \ 399do { \ 400 R128_WRITE8(R128_CLOCK_CNTL_INDEX, \ 401 ((addr) & 0x1f) | R128_PLL_WR_EN); \ 402 R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \ 403} while (0) 404 405#define CCE_PACKET0( reg, n ) (R128_CCE_PACKET0 | \ 406 ((n) << 16) | ((reg) >> 2)) 407#define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \ 408 (((reg1) >> 2) << 11) | ((reg0) >> 2)) 409#define CCE_PACKET2() (R128_CCE_PACKET2) 410#define CCE_PACKET3( pkt, n ) (R128_CCE_PACKET3 | \ 411 (pkt) | ((n) << 16)) 412 413static __inline__ void r128_update_ring_snapshot(drm_r128_private_t * dev_priv) 414{ 415 drm_r128_ring_buffer_t *ring = &dev_priv->ring; 416 ring->space = (GET_RING_HEAD(dev_priv) - ring->tail) * sizeof(u32); 417 if (ring->space <= 0) 418 ring->space += ring->size; 419} 420 421/* ================================================================ 422 * Misc helper macros 423 */ 424 425#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ 426do { \ 427 drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; \ 428 if ( ring->space < ring->high_mark ) { \ 429 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { \ 430 r128_update_ring_snapshot( dev_priv ); \ 431 if ( ring->space >= ring->high_mark ) \ 432 goto __ring_space_done; \ 433 DRM_UDELAY(1); \ 434 } \ 435 DRM_ERROR( "ring space check failed!\n" ); \ 436 return -EBUSY; \ 437 } \ 438 __ring_space_done: \ 439 ; \ 440} while (0) 441 442#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ 443do { \ 444 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; \ 445 if ( sarea_priv->last_dispatch >= R128_MAX_VB_AGE ) { \ 446 int __ret = r128_do_cce_idle( dev_priv ); \ 447 if ( __ret ) return __ret; \ 448 sarea_priv->last_dispatch = 0; \ 449 r128_freelist_reset( dev ); \ 450 } \ 451} while (0) 452 453#define R128_WAIT_UNTIL_PAGE_FLIPPED() do { \ 454 OUT_RING( CCE_PACKET0( R128_WAIT_UNTIL, 0 ) ); \ 455 OUT_RING( R128_EVENT_CRTC_OFFSET ); \ 456} while (0) 457 458/* ================================================================ 459 * Ring control 460 */ 461 462#define R128_VERBOSE 0 463 464#define RING_LOCALS \ 465 int write, _nr; unsigned int tail_mask; volatile u32 *ring; 466 467#define BEGIN_RING( n ) do { \ 468 if ( R128_VERBOSE ) { \ 469 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \ 470 } \ 471 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ 472 COMMIT_RING(); \ 473 r128_wait_ring( dev_priv, (n) * sizeof(u32) ); \ 474 } \ 475 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ 476 ring = dev_priv->ring.start; \ 477 write = dev_priv->ring.tail; \ 478 tail_mask = dev_priv->ring.tail_mask; \ 479} while (0) 480 481/* You can set this to zero if you want. If the card locks up, you'll 482 * need to keep this set. It works around a bug in early revs of the 483 * Rage 128 chipset, where the CCE would read 32 dwords past the end of 484 * the ring buffer before wrapping around. 485 */ 486#define R128_BROKEN_CCE 1 487 488#define ADVANCE_RING() do { \ 489 if ( R128_VERBOSE ) { \ 490 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ 491 write, dev_priv->ring.tail ); \ 492 } \ 493 if ( R128_BROKEN_CCE && write < 32 ) { \ 494 memcpy( dev_priv->ring.end, \ 495 dev_priv->ring.start, \ 496 write * sizeof(u32) ); \ 497 } \ 498 if (((dev_priv->ring.tail + _nr) & tail_mask) != write) { \ 499 DRM_ERROR( \ 500 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ 501 ((dev_priv->ring.tail + _nr) & tail_mask), \ 502 write, __LINE__); \ 503 } else \ 504 dev_priv->ring.tail = write; \ 505} while (0) 506 507#define COMMIT_RING() do { \ 508 if ( R128_VERBOSE ) { \ 509 DRM_INFO( "COMMIT_RING() tail=0x%06x\n", \ 510 dev_priv->ring.tail ); \ 511 } \ 512 DRM_MEMORYBARRIER(); \ 513 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, dev_priv->ring.tail ); \ 514 R128_READ( R128_PM4_BUFFER_DL_WPTR ); \ 515} while (0) 516 517#define OUT_RING( x ) do { \ 518 if ( R128_VERBOSE ) { \ 519 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ 520 (unsigned int)(x), write ); \ 521 } \ 522 ring[write++] = cpu_to_le32( x ); \ 523 write &= tail_mask; \ 524} while (0) 525 526#endif /* __R128_DRV_H__ */ 527