1/* $NetBSD: if_ure.c,v 1.60 2024/05/12 17:17:56 christos Exp $ */ 2/* $OpenBSD: if_ure.c,v 1.10 2018/11/02 21:32:30 jcs Exp $ */ 3 4/*- 5 * Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30/* RealTek RTL8152/RTL8153 10/100/Gigabit USB Ethernet device */ 31 32#include <sys/cdefs.h> 33__KERNEL_RCSID(0, "$NetBSD: if_ure.c,v 1.60 2024/05/12 17:17:56 christos Exp $"); 34 35#ifdef _KERNEL_OPT 36#include "opt_usb.h" 37#include "opt_inet.h" 38#endif 39 40#include <sys/param.h> 41#include <sys/cprng.h> 42 43#include <net/route.h> 44 45#include <dev/usb/usbnet.h> 46 47#include <netinet/in_offload.h> /* XXX for in_undefer_cksum() */ 48#ifdef INET6 49#include <netinet/in.h> 50#include <netinet6/in6_offload.h> /* XXX for in6_undefer_cksum() */ 51#endif 52 53#include <dev/ic/rtl81x9reg.h> /* XXX for RTK_GMEDIASTAT */ 54#include <dev/usb/if_urereg.h> 55#include <dev/usb/if_urevar.h> 56 57#define URE_PRINTF(un, fmt, args...) \ 58 device_printf((un)->un_dev, "%s: " fmt, __func__, ##args); 59 60#define URE_DEBUG 61#ifdef URE_DEBUG 62#define DPRINTF(x) do { if (uredebug) printf x; } while (0) 63#define DPRINTFN(n, x) do { if (uredebug >= (n)) printf x; } while (0) 64int uredebug = 0; 65#else 66#define DPRINTF(x) 67#define DPRINTFN(n, x) 68#endif 69 70#define ETHER_IS_ZERO(addr) \ 71 (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5])) 72 73static const struct usb_devno ure_devs[] = { 74 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152 }, 75 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8153 }, 76 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_UE300 }, 77}; 78 79#define URE_BUFSZ (16 * 1024) 80 81static void ure_reset(struct usbnet *); 82static uint32_t ure_txcsum(struct mbuf *); 83static int ure_rxcsum(struct ifnet *, struct ure_rxpkt *); 84static void ure_rtl8152_init(struct usbnet *); 85static void ure_rtl8153_init(struct usbnet *); 86static void ure_disable_teredo(struct usbnet *); 87static void ure_init_fifo(struct usbnet *); 88 89static void ure_uno_stop(struct ifnet *, int); 90static void ure_uno_mcast(struct ifnet *); 91static int ure_uno_mii_read_reg(struct usbnet *, int, int, uint16_t *); 92static int ure_uno_mii_write_reg(struct usbnet *, int, int, uint16_t); 93static void ure_uno_miibus_statchg(struct ifnet *); 94static unsigned ure_uno_tx_prepare(struct usbnet *, struct mbuf *, 95 struct usbnet_chain *); 96static void ure_uno_rx_loop(struct usbnet *, struct usbnet_chain *, 97 uint32_t); 98static int ure_uno_init(struct ifnet *); 99 100static int ure_match(device_t, cfdata_t, void *); 101static void ure_attach(device_t, device_t, void *); 102 103CFATTACH_DECL_NEW(ure, sizeof(struct usbnet), ure_match, ure_attach, 104 usbnet_detach, usbnet_activate); 105 106static const struct usbnet_ops ure_ops = { 107 .uno_stop = ure_uno_stop, 108 .uno_mcast = ure_uno_mcast, 109 .uno_read_reg = ure_uno_mii_read_reg, 110 .uno_write_reg = ure_uno_mii_write_reg, 111 .uno_statchg = ure_uno_miibus_statchg, 112 .uno_tx_prepare = ure_uno_tx_prepare, 113 .uno_rx_loop = ure_uno_rx_loop, 114 .uno_init = ure_uno_init, 115}; 116 117static int 118ure_ctl(struct usbnet *un, uint8_t rw, uint16_t val, uint16_t index, 119 void *buf, int len) 120{ 121 usb_device_request_t req; 122 usbd_status err; 123 124 if (usbnet_isdying(un)) 125 return 0; 126 127 if (rw == URE_CTL_WRITE) 128 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 129 else 130 req.bmRequestType = UT_READ_VENDOR_DEVICE; 131 req.bRequest = UR_SET_ADDRESS; 132 USETW(req.wValue, val); 133 USETW(req.wIndex, index); 134 USETW(req.wLength, len); 135 136 DPRINTFN(5, ("ure_ctl: rw %d, val %04hu, index %04hu, len %d\n", 137 rw, val, index, len)); 138 err = usbd_do_request(un->un_udev, &req, buf); 139 if (err) { 140 DPRINTF(("ure_ctl: error %d\n", err)); 141 if (rw == URE_CTL_READ) 142 memset(buf, 0, len); 143 return -1; 144 } 145 146 return 0; 147} 148 149static int 150ure_read_mem(struct usbnet *un, uint16_t addr, uint16_t index, 151 void *buf, int len) 152{ 153 return ure_ctl(un, URE_CTL_READ, addr, index, buf, len); 154} 155 156static int 157ure_write_mem(struct usbnet *un, uint16_t addr, uint16_t index, 158 void *buf, int len) 159{ 160 return ure_ctl(un, URE_CTL_WRITE, addr, index, buf, len); 161} 162 163static uint8_t 164ure_read_1(struct usbnet *un, uint16_t reg, uint16_t index) 165{ 166 uint32_t val; 167 uint8_t temp[4]; 168 uint8_t shift; 169 170 shift = (reg & 3) << 3; 171 reg &= ~3; 172 173 ure_read_mem(un, reg, index, &temp, 4); 174 val = UGETDW(temp); 175 val >>= shift; 176 177 return val & 0xff; 178} 179 180static uint16_t 181ure_read_2(struct usbnet *un, uint16_t reg, uint16_t index) 182{ 183 uint32_t val; 184 uint8_t temp[4]; 185 uint8_t shift; 186 187 shift = (reg & 2) << 3; 188 reg &= ~3; 189 190 ure_read_mem(un, reg, index, &temp, 4); 191 val = UGETDW(temp); 192 val >>= shift; 193 194 return val & 0xffff; 195} 196 197static uint32_t 198ure_read_4(struct usbnet *un, uint16_t reg, uint16_t index) 199{ 200 uint8_t temp[4]; 201 202 ure_read_mem(un, reg, index, &temp, 4); 203 return UGETDW(temp); 204} 205 206static int 207ure_write_1(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 208{ 209 uint16_t byen; 210 uint8_t temp[4]; 211 uint8_t shift; 212 213 byen = URE_BYTE_EN_BYTE; 214 shift = reg & 3; 215 val &= 0xff; 216 217 if (reg & 3) { 218 byen <<= shift; 219 val <<= (shift << 3); 220 reg &= ~3; 221 } 222 223 USETDW(temp, val); 224 return ure_write_mem(un, reg, index | byen, &temp, 4); 225} 226 227static int 228ure_write_2(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 229{ 230 uint16_t byen; 231 uint8_t temp[4]; 232 uint8_t shift; 233 234 byen = URE_BYTE_EN_WORD; 235 shift = reg & 2; 236 val &= 0xffff; 237 238 if (reg & 2) { 239 byen <<= shift; 240 val <<= (shift << 3); 241 reg &= ~3; 242 } 243 244 USETDW(temp, val); 245 return ure_write_mem(un, reg, index | byen, &temp, 4); 246} 247 248static int 249ure_write_4(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 250{ 251 uint8_t temp[4]; 252 253 USETDW(temp, val); 254 return ure_write_mem(un, reg, index | URE_BYTE_EN_DWORD, &temp, 4); 255} 256 257static uint16_t 258ure_ocp_reg_read(struct usbnet *un, uint16_t addr) 259{ 260 uint16_t reg; 261 262 ure_write_2(un, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 263 reg = (addr & 0x0fff) | 0xb000; 264 265 return ure_read_2(un, reg, URE_MCU_TYPE_PLA); 266} 267 268static void 269ure_ocp_reg_write(struct usbnet *un, uint16_t addr, uint16_t data) 270{ 271 uint16_t reg; 272 273 ure_write_2(un, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 274 reg = (addr & 0x0fff) | 0xb000; 275 276 ure_write_2(un, reg, URE_MCU_TYPE_PLA, data); 277} 278 279static int 280ure_uno_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val) 281{ 282 283 if (un->un_phyno != phy) { 284 *val = 0; 285 return EINVAL; 286 } 287 288 /* Let the rgephy driver read the URE_PLA_PHYSTATUS register. */ 289 if (reg == RTK_GMEDIASTAT) { 290 *val = ure_read_1(un, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA); 291 return USBD_NORMAL_COMPLETION; 292 } 293 294 *val = ure_ocp_reg_read(un, URE_OCP_BASE_MII + reg * 2); 295 296 return 0; 297} 298 299static int 300ure_uno_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val) 301{ 302 303 if (un->un_phyno != phy) 304 return EINVAL; 305 306 ure_ocp_reg_write(un, URE_OCP_BASE_MII + reg * 2, val); 307 308 return 0; 309} 310 311static void 312ure_uno_miibus_statchg(struct ifnet *ifp) 313{ 314 struct usbnet * const un = ifp->if_softc; 315 struct mii_data * const mii = usbnet_mii(un); 316 317 if (usbnet_isdying(un)) 318 return; 319 320 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 321 (IFM_ACTIVE | IFM_AVALID)) { 322 switch (IFM_SUBTYPE(mii->mii_media_active)) { 323 case IFM_10_T: 324 case IFM_100_TX: 325 usbnet_set_link(un, true); 326 break; 327 case IFM_1000_T: 328 if ((un->un_flags & URE_FLAG_8152) != 0) 329 break; 330 usbnet_set_link(un, true); 331 break; 332 default: 333 break; 334 } 335 } 336} 337 338static void 339ure_uno_mcast(struct ifnet *ifp) 340{ 341 struct usbnet *un = ifp->if_softc; 342 struct ethercom *ec = usbnet_ec(un); 343 struct ether_multi *enm; 344 struct ether_multistep step; 345 uint32_t mchash[2] = { 0, 0 }; 346 uint32_t h = 0, rxmode; 347 348 if (usbnet_isdying(un)) 349 return; 350 351 rxmode = ure_read_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA); 352 rxmode &= ~(URE_RCR_AAP | URE_RCR_AM); 353 /* continue to accept my own DA and bcast frames */ 354 355 ETHER_LOCK(ec); 356 if (usbnet_ispromisc(un)) { 357 ec->ec_flags |= ETHER_F_ALLMULTI; 358 ETHER_UNLOCK(ec); 359 /* run promisc. mode */ 360 rxmode |= URE_RCR_AM; /* ??? */ 361 rxmode |= URE_RCR_AAP; 362 mchash[0] = mchash[1] = 0xffffffff; 363 goto update; 364 } 365 ec->ec_flags &= ~ETHER_F_ALLMULTI; 366 ETHER_FIRST_MULTI(step, ec, enm); 367 while (enm != NULL) { 368 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 369 ec->ec_flags |= ETHER_F_ALLMULTI; 370 ETHER_UNLOCK(ec); 371 /* accept all mcast frames */ 372 rxmode |= URE_RCR_AM; 373 mchash[0] = mchash[1] = ~0U; /* necessary ?? */ 374 goto update; 375 } 376 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 377 mchash[h >> 31] |= 1U << ((h >> 26) & 0x1f); 378 ETHER_NEXT_MULTI(step, enm); 379 } 380 ETHER_UNLOCK(ec); 381 if (h != 0) { 382 rxmode |= URE_RCR_AM; /* activate mcast hash filter */ 383 h = bswap32(mchash[0]); 384 mchash[0] = bswap32(mchash[1]); 385 mchash[1] = h; 386 } 387 update: 388 ure_write_4(un, URE_PLA_MAR0, URE_MCU_TYPE_PLA, mchash[0]); 389 ure_write_4(un, URE_PLA_MAR4, URE_MCU_TYPE_PLA, mchash[1]); 390 ure_write_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 391} 392 393static void 394ure_reset(struct usbnet *un) 395{ 396 int i; 397 398 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 399 400 for (i = 0; i < URE_TIMEOUT; i++) { 401 if (usbnet_isdying(un)) 402 return; 403 if (!(ure_read_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA) & 404 URE_CR_RST)) 405 break; 406 usbd_delay_ms(un->un_udev, 10); 407 } 408 if (i == URE_TIMEOUT) 409 URE_PRINTF(un, "reset never completed\n"); 410} 411 412static int 413ure_uno_init(struct ifnet *ifp) 414{ 415 struct usbnet * const un = ifp->if_softc; 416 uint8_t eaddr[8]; 417 418 /* Set MAC address. */ 419 memset(eaddr, 0, sizeof(eaddr)); 420 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 421 ure_write_1(un, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 422 ure_write_mem(un, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 423 eaddr, 8); 424 ure_write_1(un, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 425 426 /* Reset the packet filter. */ 427 ure_write_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA, 428 ure_read_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA) & 429 ~URE_FMC_FCR_MCU_EN); 430 ure_write_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA, 431 ure_read_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA) | 432 URE_FMC_FCR_MCU_EN); 433 434 /* Enable transmit and receive. */ 435 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, 436 ure_read_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE | 437 URE_CR_TE); 438 439 ure_write_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 440 ure_read_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) & 441 ~URE_RXDY_GATED_EN); 442 443 return 0; 444} 445 446static void 447ure_uno_stop(struct ifnet *ifp, int disable __unused) 448{ 449 struct usbnet * const un = ifp->if_softc; 450 451 ure_reset(un); 452} 453 454static void 455ure_rtl8152_init(struct usbnet *un) 456{ 457 uint32_t pwrctrl; 458 459 /* Disable ALDPS. */ 460 ure_ocp_reg_write(un, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 461 URE_DIS_SDSAVE); 462 usbd_delay_ms(un->un_udev, 20); 463 464 if (un->un_flags & URE_FLAG_VER_4C00) { 465 ure_write_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 466 ure_read_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 467 ~URE_LED_MODE_MASK); 468 } 469 470 ure_write_2(un, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, 471 ure_read_2(un, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) & 472 ~URE_POWER_CUT); 473 ure_write_2(un, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 474 ure_read_2(un, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) & 475 ~URE_RESUME_INDICATE); 476 477 ure_write_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 478 ure_read_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 479 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 480 pwrctrl = ure_read_4(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 481 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 482 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 483 ure_write_4(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 484 ure_write_2(un, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 485 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 486 URE_SPDWN_LINKCHG_MSK); 487 488 /* Enable Rx aggregation. */ 489 ure_write_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 490 ure_read_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 491 ~URE_RX_AGG_DISABLE); 492 493 /* Disable ALDPS. */ 494 ure_ocp_reg_write(un, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 495 URE_DIS_SDSAVE); 496 usbd_delay_ms(un->un_udev, 20); 497 498 ure_init_fifo(un); 499 500 ure_write_1(un, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 501 URE_TX_AGG_MAX_THRESHOLD); 502 ure_write_4(un, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 503 ure_write_4(un, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 504 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 505} 506 507static void 508ure_rtl8153_init(struct usbnet *un) 509{ 510 uint16_t val; 511 uint8_t u1u2[8]; 512 int i; 513 514 /* Disable ALDPS. */ 515 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 516 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 517 usbd_delay_ms(un->un_udev, 20); 518 519 memset(u1u2, 0x00, sizeof(u1u2)); 520 ure_write_mem(un, URE_USB_TOLERANCE, 521 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 522 523 for (i = 0; i < URE_TIMEOUT; i++) { 524 if (usbnet_isdying(un)) 525 return; 526 if (ure_read_2(un, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 527 URE_AUTOLOAD_DONE) 528 break; 529 usbd_delay_ms(un->un_udev, 10); 530 } 531 if (i == URE_TIMEOUT) 532 URE_PRINTF(un, "timeout waiting for chip autoload\n"); 533 534 for (i = 0; i < URE_TIMEOUT; i++) { 535 if (usbnet_isdying(un)) 536 return; 537 val = ure_ocp_reg_read(un, URE_OCP_PHY_STATUS) & 538 URE_PHY_STAT_MASK; 539 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN) 540 break; 541 usbd_delay_ms(un->un_udev, 10); 542 } 543 if (i == URE_TIMEOUT) 544 URE_PRINTF(un, "timeout waiting for phy to stabilize\n"); 545 546 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 547 ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) & 548 ~URE_U2P3_ENABLE); 549 550 if (un->un_flags & URE_FLAG_VER_5C10) { 551 val = ure_read_2(un, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 552 val &= ~URE_PWD_DN_SCALE_MASK; 553 val |= URE_PWD_DN_SCALE(96); 554 ure_write_2(un, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val); 555 556 ure_write_1(un, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 557 ure_read_1(un, URE_USB_USB2PHY, URE_MCU_TYPE_USB) | 558 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 559 } else if (un->un_flags & URE_FLAG_VER_5C20) { 560 ure_write_1(un, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 561 ure_read_1(un, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) & 562 ~URE_ECM_ALDPS); 563 } 564 if (un->un_flags & (URE_FLAG_VER_5C20 | URE_FLAG_VER_5C30)) { 565 val = ure_read_1(un, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB); 566 if (ure_read_2(un, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) == 567 0) 568 val &= ~URE_DYNAMIC_BURST; 569 else 570 val |= URE_DYNAMIC_BURST; 571 ure_write_1(un, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val); 572 } 573 574 ure_write_1(un, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, 575 ure_read_1(un, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) | 576 URE_EP4_FULL_FC); 577 578 ure_write_2(un, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, 579 ure_read_2(un, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) & 580 ~URE_TIMER11_EN); 581 582 ure_write_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 583 ure_read_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 584 ~URE_LED_MODE_MASK); 585 586 if ((un->un_flags & URE_FLAG_VER_5C10) && 587 un->un_udev->ud_speed != USB_SPEED_SUPER) 588 val = URE_LPM_TIMER_500MS; 589 else 590 val = URE_LPM_TIMER_500US; 591 ure_write_1(un, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 592 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM); 593 594 val = ure_read_2(un, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 595 val &= ~URE_SEN_VAL_MASK; 596 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 597 ure_write_2(un, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val); 598 599 ure_write_2(un, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 600 601 ure_write_2(un, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 602 ure_read_2(un, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) & 603 ~(URE_PWR_EN | URE_PHASE2_EN)); 604 ure_write_2(un, URE_USB_MISC_0, URE_MCU_TYPE_USB, 605 ure_read_2(un, URE_USB_MISC_0, URE_MCU_TYPE_USB) & 606 ~URE_PCUT_STATUS); 607 608 memset(u1u2, 0xff, sizeof(u1u2)); 609 ure_write_mem(un, URE_USB_TOLERANCE, 610 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 611 612 ure_write_2(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 613 URE_ALDPS_SPDWN_RATIO); 614 ure_write_2(un, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 615 URE_EEE_SPDWN_RATIO); 616 ure_write_2(un, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 617 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN | 618 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN); 619 ure_write_2(un, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 620 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN | 621 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN | 622 URE_EEE_SPDWN_EN); 623 624 val = ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 625 if (!(un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10))) 626 val |= URE_U2P3_ENABLE; 627 else 628 val &= ~URE_U2P3_ENABLE; 629 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 630 631 memset(u1u2, 0x00, sizeof(u1u2)); 632 ure_write_mem(un, URE_USB_TOLERANCE, 633 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 634 635 /* Disable ALDPS. */ 636 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 637 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 638 usbd_delay_ms(un->un_udev, 20); 639 640 ure_init_fifo(un); 641 642 /* Enable Rx aggregation. */ 643 ure_write_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 644 ure_read_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 645 ~URE_RX_AGG_DISABLE); 646 647 val = ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 648 if (!(un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10))) 649 val |= URE_U2P3_ENABLE; 650 else 651 val &= ~URE_U2P3_ENABLE; 652 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 653 654 memset(u1u2, 0xff, sizeof(u1u2)); 655 ure_write_mem(un, URE_USB_TOLERANCE, 656 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 657} 658 659static void 660ure_disable_teredo(struct usbnet *un) 661{ 662 ure_write_4(un, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 663 ure_read_4(un, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) & 664 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 665 ure_write_2(un, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, 666 URE_WDT6_SET_MODE); 667 ure_write_2(un, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 668 ure_write_4(un, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 669} 670 671static void 672ure_init_fifo(struct usbnet *un) 673{ 674 uint32_t rxmode, rx_fifo1, rx_fifo2; 675 int i; 676 677 ure_write_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 678 ure_read_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) | 679 URE_RXDY_GATED_EN); 680 681 ure_disable_teredo(un); 682 683 rxmode = ure_read_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA); 684 rxmode &= ~URE_RCR_ACPT_ALL; 685 rxmode |= URE_RCR_APM | URE_RCR_AB; /* accept my own DA and bcast */ 686 ure_write_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 687 688 if (!(un->un_flags & URE_FLAG_8152)) { 689 if (un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10 | 690 URE_FLAG_VER_5C20)) 691 ure_ocp_reg_write(un, URE_OCP_ADC_CFG, 692 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 693 if (un->un_flags & URE_FLAG_VER_5C00) 694 ure_ocp_reg_write(un, URE_OCP_EEE_CFG, 695 ure_ocp_reg_read(un, URE_OCP_EEE_CFG) & 696 ~URE_CTAP_SHORT_EN); 697 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 698 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) | 699 URE_EEE_CLKDIV_EN); 700 ure_ocp_reg_write(un, URE_OCP_DOWN_SPEED, 701 ure_ocp_reg_read(un, URE_OCP_DOWN_SPEED) | 702 URE_EN_10M_BGOFF); 703 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 704 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) | 705 URE_EN_10M_PLLOFF); 706 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE); 707 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x0b13); 708 ure_write_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 709 ure_read_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 710 URE_PFM_PWM_SWITCH); 711 712 /* Enable LPF corner auto tune. */ 713 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG); 714 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0xf70f); 715 716 /* Adjust 10M amplitude. */ 717 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1); 718 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x00af); 719 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2); 720 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x0208); 721 } 722 723 ure_reset(un); 724 725 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 726 727 ure_write_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, 728 ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 729 ~URE_NOW_IS_OOB); 730 731 ure_write_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 732 ure_read_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) & 733 ~URE_MCU_BORW_EN); 734 for (i = 0; i < URE_TIMEOUT; i++) { 735 if (usbnet_isdying(un)) 736 return; 737 if (ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 738 URE_LINK_LIST_READY) 739 break; 740 usbd_delay_ms(un->un_udev, 10); 741 } 742 if (i == URE_TIMEOUT) 743 URE_PRINTF(un, "timeout waiting for OOB control\n"); 744 ure_write_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 745 ure_read_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) | 746 URE_RE_INIT_LL); 747 for (i = 0; i < URE_TIMEOUT; i++) { 748 if (usbnet_isdying(un)) 749 return; 750 if (ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 751 URE_LINK_LIST_READY) 752 break; 753 usbd_delay_ms(un->un_udev, 10); 754 } 755 if (i == URE_TIMEOUT) 756 URE_PRINTF(un, "timeout waiting for OOB control\n"); 757 758 ure_write_2(un, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 759 ure_read_2(un, URE_PLA_CPCR, URE_MCU_TYPE_PLA) & 760 ~URE_CPCR_RX_VLAN); 761 ure_write_2(un, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 762 ure_read_2(un, URE_PLA_TCR0, URE_MCU_TYPE_PLA) | 763 URE_TCR0_AUTO_FIFO); 764 765 /* Configure Rx FIFO threshold and coalescing. */ 766 ure_write_4(un, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 767 URE_RXFIFO_THR1_NORMAL); 768 if (un->un_udev->ud_speed == USB_SPEED_FULL) { 769 rx_fifo1 = URE_RXFIFO_THR2_FULL; 770 rx_fifo2 = URE_RXFIFO_THR3_FULL; 771 } else { 772 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 773 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 774 } 775 ure_write_4(un, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 776 ure_write_4(un, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 777 778 /* Configure Tx FIFO threshold. */ 779 ure_write_4(un, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 780 URE_TXFIFO_THR_NORMAL); 781} 782 783static int 784ure_match(device_t parent, cfdata_t match, void *aux) 785{ 786 struct usb_attach_arg *uaa = aux; 787 788 return usb_lookup(ure_devs, uaa->uaa_vendor, uaa->uaa_product) != NULL ? 789 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 790} 791 792static void 793ure_attach(device_t parent, device_t self, void *aux) 794{ 795 USBNET_MII_DECL_DEFAULT(unm); 796 struct usbnet * const un = device_private(self); 797 struct usb_attach_arg *uaa = aux; 798 struct usbd_device *dev = uaa->uaa_device; 799 usb_interface_descriptor_t *id; 800 usb_endpoint_descriptor_t *ed; 801 int error, i; 802 uint16_t ver; 803 uint8_t eaddr[8]; /* 2byte padded */ 804 char *devinfop; 805 uint32_t maclo, machi; 806 807 aprint_naive("\n"); 808 aprint_normal("\n"); 809 devinfop = usbd_devinfo_alloc(dev, 0); 810 aprint_normal_dev(self, "%s\n", devinfop); 811 usbd_devinfo_free(devinfop); 812 813 un->un_dev = self; 814 un->un_udev = dev; 815 un->un_sc = un; 816 un->un_ops = &ure_ops; 817 un->un_rx_xfer_flags = USBD_SHORT_XFER_OK; 818 un->un_tx_xfer_flags = USBD_FORCE_SHORT_XFER; 819 un->un_rx_list_cnt = URE_RX_LIST_CNT; 820 un->un_tx_list_cnt = URE_TX_LIST_CNT; 821 un->un_rx_bufsz = URE_BUFSZ; 822 un->un_tx_bufsz = URE_BUFSZ; 823 824#define URE_CONFIG_NO 1 /* XXX */ 825 error = usbd_set_config_no(dev, URE_CONFIG_NO, 1); 826 if (error) { 827 aprint_error_dev(self, "failed to set configuration: %s\n", 828 usbd_errstr(error)); 829 return; /* XXX */ 830 } 831 832 if (uaa->uaa_product == USB_PRODUCT_REALTEK_RTL8152) 833 un->un_flags |= URE_FLAG_8152; 834 835#define URE_IFACE_IDX 0 /* XXX */ 836 error = usbd_device2interface_handle(dev, URE_IFACE_IDX, &un->un_iface); 837 if (error) { 838 aprint_error_dev(self, "failed to get interface handle: %s\n", 839 usbd_errstr(error)); 840 return; /* XXX */ 841 } 842 843 id = usbd_get_interface_descriptor(un->un_iface); 844 for (i = 0; i < id->bNumEndpoints; i++) { 845 ed = usbd_interface2endpoint_descriptor(un->un_iface, i); 846 if (ed == NULL) { 847 aprint_error_dev(self, "couldn't get ep %d\n", i); 848 return; /* XXX */ 849 } 850 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 851 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 852 un->un_ed[USBNET_ENDPT_RX] = ed->bEndpointAddress; 853 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 854 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 855 un->un_ed[USBNET_ENDPT_TX] = ed->bEndpointAddress; 856 } 857 } 858 859 /* Set these up now for ure_ctl(). */ 860 usbnet_attach(un); 861 862 un->un_phyno = 0; 863 864 ver = ure_read_2(un, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 865 switch (ver) { 866 case 0x4c00: 867 un->un_flags |= URE_FLAG_VER_4C00; 868 break; 869 case 0x4c10: 870 un->un_flags |= URE_FLAG_VER_4C10; 871 break; 872 case 0x5c00: 873 un->un_flags |= URE_FLAG_VER_5C00; 874 break; 875 case 0x5c10: 876 un->un_flags |= URE_FLAG_VER_5C10; 877 break; 878 case 0x5c20: 879 un->un_flags |= URE_FLAG_VER_5C20; 880 break; 881 case 0x5c30: 882 un->un_flags |= URE_FLAG_VER_5C30; 883 break; 884 default: 885 /* fake addr? or just fail? */ 886 break; 887 } 888 aprint_normal_dev(self, "RTL%d %sver %04x\n", 889 (un->un_flags & URE_FLAG_8152) ? 8152 : 8153, 890 (un->un_flags != 0) ? "" : "unknown ", 891 ver); 892 893 if (un->un_flags & URE_FLAG_8152) 894 ure_rtl8152_init(un); 895 else 896 ure_rtl8153_init(un); 897 898 if ((un->un_flags & URE_FLAG_VER_4C00) || 899 (un->un_flags & URE_FLAG_VER_4C10)) 900 ure_read_mem(un, URE_PLA_IDR, URE_MCU_TYPE_PLA, eaddr, 901 sizeof(eaddr)); 902 else 903 ure_read_mem(un, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, eaddr, 904 sizeof(eaddr)); 905 if (ETHER_IS_ZERO(eaddr)) { 906 maclo = 0x00f2 | (cprng_strong32() & 0xffff0000); 907 machi = cprng_strong32() & 0xffff; 908 eaddr[0] = maclo & 0xff; 909 eaddr[1] = (maclo >> 8) & 0xff; 910 eaddr[2] = (maclo >> 16) & 0xff; 911 eaddr[3] = (maclo >> 24) & 0xff; 912 eaddr[4] = machi & 0xff; 913 eaddr[5] = (machi >> 8) & 0xff; 914 } 915 memcpy(un->un_eaddr, eaddr, sizeof(un->un_eaddr)); 916 917 struct ifnet *ifp = usbnet_ifp(un); 918 919 /* 920 * We don't support TSOv4 and v6 for now, that are required to 921 * be handled in software for some cases. 922 */ 923 ifp->if_capabilities = IFCAP_CSUM_IPv4_Tx | 924 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx; 925#ifdef INET6 926 ifp->if_capabilities |= IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx; 927#endif 928 if (un->un_flags & ~URE_FLAG_VER_4C00) { 929 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Rx | 930 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 931 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 932 } 933 struct ethercom *ec = usbnet_ec(un); 934 ec->ec_capabilities = ETHERCAP_VLAN_MTU; 935#ifdef notyet 936 ec->ec_capabilities |= ETHERCAP_JUMBO_MTU; 937#endif 938 939 unm.un_mii_phyloc = un->un_phyno; 940 usbnet_attach_ifp(un, IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST, 941 0, &unm); 942} 943 944static void 945ure_uno_rx_loop(struct usbnet *un, struct usbnet_chain *c, uint32_t total_len) 946{ 947 struct ifnet *ifp = usbnet_ifp(un); 948 uint8_t *buf = c->unc_buf; 949 uint16_t pkt_len = 0; 950 uint16_t pkt_count = 0; 951 struct ure_rxpkt rxhdr; 952 953 do { 954 if (total_len < sizeof(rxhdr)) { 955 DPRINTF(("too few bytes left for a packet header\n")); 956 if_statinc(ifp, if_ierrors); 957 return; 958 } 959 960 buf += roundup(pkt_len, 8); 961 962 memcpy(&rxhdr, buf, sizeof(rxhdr)); 963 total_len -= sizeof(rxhdr); 964 965 pkt_len = le32toh(rxhdr.ure_pktlen) & URE_RXPKT_LEN_MASK; 966 DPRINTFN(4, ("next packet is %d bytes\n", pkt_len)); 967 if (pkt_len > total_len) { 968 DPRINTF(("not enough bytes left for next packet\n")); 969 if_statinc(ifp, if_ierrors); 970 return; 971 } 972 973 total_len -= roundup(pkt_len, 8); 974 buf += sizeof(rxhdr); 975 976 usbnet_enqueue(un, buf, pkt_len - ETHER_CRC_LEN, 977 ure_rxcsum(ifp, &rxhdr), 0, 0); 978 979 pkt_count++; 980 981 } while (total_len > 0); 982 983 if (pkt_count) 984 rnd_add_uint32(usbnet_rndsrc(un), pkt_count); 985} 986 987static int 988ure_rxcsum(struct ifnet *ifp, struct ure_rxpkt *rp) 989{ 990 int enabled = ifp->if_csum_flags_rx, flags = 0; 991 uint32_t csum, misc; 992 993 if (enabled == 0) 994 return 0; 995 996 csum = le32toh(rp->ure_csum); 997 misc = le32toh(rp->ure_misc); 998 999 if (csum & URE_RXPKT_IPV4_CS) { 1000 flags |= M_CSUM_IPv4; 1001 if (csum & URE_RXPKT_TCP_CS) 1002 flags |= M_CSUM_TCPv4; 1003 if (csum & URE_RXPKT_UDP_CS) 1004 flags |= M_CSUM_UDPv4; 1005 } else if (csum & URE_RXPKT_IPV6_CS) { 1006 flags = 0; 1007 if (csum & URE_RXPKT_TCP_CS) 1008 flags |= M_CSUM_TCPv6; 1009 if (csum & URE_RXPKT_UDP_CS) 1010 flags |= M_CSUM_UDPv6; 1011 } 1012 1013 flags &= enabled; 1014 if (__predict_false((flags & M_CSUM_IPv4) && 1015 (misc & URE_RXPKT_IP_F))) 1016 flags |= M_CSUM_IPv4_BAD; 1017 if (__predict_false( 1018 ((flags & (M_CSUM_TCPv4 | M_CSUM_TCPv6)) && (misc & URE_RXPKT_TCP_F)) 1019 || ((flags & (M_CSUM_UDPv4 | M_CSUM_UDPv6)) && (misc & URE_RXPKT_UDP_F)) 1020 )) 1021 flags |= M_CSUM_TCP_UDP_BAD; 1022 1023 return flags; 1024} 1025 1026static unsigned 1027ure_uno_tx_prepare(struct usbnet *un, struct mbuf *m, struct usbnet_chain *c) 1028{ 1029 struct ure_txpkt txhdr; 1030 uint32_t frm_len = 0; 1031 uint8_t *buf = c->unc_buf; 1032 1033 if ((unsigned)m->m_pkthdr.len > un->un_tx_bufsz - sizeof(txhdr)) 1034 return 0; 1035 1036 /* header */ 1037 txhdr.ure_pktlen = htole32(m->m_pkthdr.len | URE_TXPKT_TX_FS | 1038 URE_TXPKT_TX_LS); 1039 txhdr.ure_csum = htole32(ure_txcsum(m)); 1040 memcpy(buf, &txhdr, sizeof(txhdr)); 1041 buf += sizeof(txhdr); 1042 frm_len = sizeof(txhdr); 1043 1044 /* packet */ 1045 m_copydata(m, 0, m->m_pkthdr.len, buf); 1046 frm_len += m->m_pkthdr.len; 1047 1048 DPRINTFN(2, ("tx %d bytes\n", frm_len)); 1049 1050 return frm_len; 1051} 1052 1053/* 1054 * We need to calculate L4 checksum in software, if the offset of 1055 * L4 header is larger than 0x7ff = 2047. 1056 */ 1057static uint32_t 1058ure_txcsum(struct mbuf *m) 1059{ 1060 struct ether_header *eh; 1061 int flags = m->m_pkthdr.csum_flags; 1062 uint32_t data = m->m_pkthdr.csum_data; 1063 uint32_t reg = 0; 1064 int l3off, l4off; 1065 uint16_t type; 1066 1067 if (flags == 0) 1068 return 0; 1069 1070 if (__predict_true(m->m_len >= (int)sizeof(*eh))) { 1071 eh = mtod(m, struct ether_header *); 1072 type = eh->ether_type; 1073 } else 1074 m_copydata(m, offsetof(struct ether_header, ether_type), 1075 sizeof(type), &type); 1076 switch (type = htons(type)) { 1077 case ETHERTYPE_IP: 1078 case ETHERTYPE_IPV6: 1079 l3off = ETHER_HDR_LEN; 1080 break; 1081 case ETHERTYPE_VLAN: 1082 l3off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1083 break; 1084 default: 1085 return 0; 1086 } 1087 1088 if (flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1089 l4off = l3off + M_CSUM_DATA_IPv4_IPHL(data); 1090 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1091 in_undefer_cksum(m, l3off, flags); 1092 return 0; 1093 } 1094 reg |= URE_TXPKT_IPV4_CS; 1095 if (flags & M_CSUM_TCPv4) 1096 reg |= URE_TXPKT_TCP_CS; 1097 else 1098 reg |= URE_TXPKT_UDP_CS; 1099 reg |= l4off << URE_L4_OFFSET_SHIFT; 1100 } 1101#ifdef INET6 1102 else if (flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) { 1103 l4off = l3off + M_CSUM_DATA_IPv6_IPHL(data); 1104 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1105 in6_undefer_cksum(m, l3off, flags); 1106 return 0; 1107 } 1108 reg |= URE_TXPKT_IPV6_CS; 1109 if (flags & M_CSUM_TCPv6) 1110 reg |= URE_TXPKT_TCP_CS; 1111 else 1112 reg |= URE_TXPKT_UDP_CS; 1113 reg |= l4off << URE_L4_OFFSET_SHIFT; 1114 } 1115#endif 1116 else if (flags & M_CSUM_IPv4) 1117 reg |= URE_TXPKT_IPV4_CS; 1118 1119 return reg; 1120} 1121 1122#ifdef _MODULE 1123#include "ioconf.c" 1124#endif 1125 1126USBNET_MODULE(ure) 1127