1/* $NetBSD: ehcireg.h,v 1.40 2024/03/08 07:05:02 mrg Exp $ */ 2 3/* 4 * Copyright (c) 2001, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart@augustsson.net). 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32/* 33 * The EHCI 0.96 spec can be found at 34 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf 35 * and the USB 2.0 spec at 36 * http://www.usb.org/developers/data/usb_20.zip 37 */ 38 39#ifndef _DEV_USB_EHCIREG_H_ 40#define _DEV_USB_EHCIREG_H_ 41 42/*** PCI config registers ***/ 43 44#define PCI_CBMEM 0x10 /* configuration base MEM */ 45 46#define PCI_INTERFACE_EHCI 0x20 47 48#define PCI_USBREV 0x60 /* RO USB protocol revision */ 49#define PCI_USBREV_MASK 0xff 50#define PCI_USBREV_PRE_1_0 0x00 51#define PCI_USBREV_1_0 0x10 52#define PCI_USBREV_1_1 0x11 53#define PCI_USBREV_2_0 0x20 54 55#define PCI_EHCI_FLADJ 0x61 /*RW Frame len adj, SOF=59488+6*fladj */ 56 57#define PCI_EHCI_PORTWAKECAP 0x62 /* RW Port wake caps (opt) */ 58 59/* Regs at EECP + offset */ 60#define PCI_EHCI_USBLEGSUP 0x00 61#define EHCI_LEG_HC_OS_OWNED 0x01000000 62#define EHCI_LEG_HC_BIOS_OWNED 0x00010000 63#define PCI_EHCI_USBLEGCTLSTS 0x04 64#define EHCI_LEG_EXT_SMI_BAR 0x80000000 65#define EHCI_LEG_EXT_SMI_PCICMD 0x40000000 66#define EHCI_LEG_EXT_SMI_OS_CHANGE 0x20000000 67 68#define EHCI_CAP_GET_ID(cap) ((cap) & 0xff) 69#define EHCI_CAP_GET_NEXT(cap) (((cap) >> 8) & 0xff) 70#define EHCI_CAP_ID_LEGACY 1 71 72/*** EHCI capability registers ***/ 73 74#define EHCI_CAPLENGTH 0x00 /*RO Capability register length field */ 75/* reserved 0x01 */ 76#define EHCI_HCIVERSION 0x02 /* RO Interface version number */ 77 78#define EHCI_HCSPARAMS 0x04 /* RO Structural parameters */ 79#define EHCI_HCS_N_TT(x) (((x) >> 20) & 0xf) /* # of xacts xlater ETTF */ 80#define EHCI_HCS_N_PTT(x) (((x) >> 20) & 0xf) /* ports per xlater ETTF */ 81#define EHCI_HCS_DEBUGPORT(x) (((x) >> 20) & 0xf) 82#define EHCI_HCS_P_INDICATOR(x) ((x) & 0x10000) 83#define EHCI_HCS_N_CC(x) (((x) >> 12) & 0xf) /* # of companion ctlrs */ 84#define EHCI_HCS_N_PCC(x) (((x) >> 8) & 0xf) /* # of ports per comp. */ 85#define EHCI_HCS_PPC(x) ((x) & 0x10) /* port power control */ 86#define EHCI_HCS_N_PORTS(x) ((x) & 0xf) /* # of ports */ 87 88#define EHCI_HCCPARAMS 0x08 /* RO Capability parameters */ 89#define EHCI_HCC_EECP(x) (((x) >> 8) & 0xff) /* extended ports caps */ 90#define EHCI_HCC_IST_FULLFRAME __BIT(7) 91#define EHCI_HCC_IST_THRESHOLD_MASK __BITS(6,4) /* isoc sched threshold */ 92#define EHCI_HCC_GET_IST_THRESHOLD(x) __SHIFTOUT((x), EHCI_HCC_IST_THRESHOLD_MASK) 93#define EHCI_HCC_ASPC(x) ((x) & 0x4) /* async sched park cap */ 94#define EHCI_HCC_PFLF(x) ((x) & 0x2) /* prog frame list flag */ 95#define EHCI_HCC_64BIT(x) ((x) & 0x1) /* 64 bit address cap */ 96 97#define EHCI_HCSP_PORTROUTE 0x0c /*RO Companion port route description */ 98 99/* EHCI operational registers. Offset given by EHCI_CAPLENGTH register */ 100#define EHCI_USBCMD 0x00 /* RO, RW, WO Command register */ 101#define EHCI_CMD_ITC_M 0x00ff0000 /* RW interrupt threshold ctrl */ 102#define EHCI_CMD_ITC_1 0x00010000 103#define EHCI_CMD_ITC_2 0x00020000 104#define EHCI_CMD_ITC_4 0x00040000 105#define EHCI_CMD_ITC_8 0x00080000 106#define EHCI_CMD_ITC_16 0x00100000 107#define EHCI_CMD_ITC_32 0x00200000 108#define EHCI_CMD_ITC_64 0x00400000 109#define EHCI_CMD_ASPME 0x00000800 /* RW/RO async park enable */ 110#define EHCI_CMD_ASPMC 0x00000300 /* RW/RO async park count */ 111#define EHCI_CMD_LHCR 0x00000080 /* RW light host ctrl reset */ 112#define EHCI_CMD_IAAD 0x00000040 /* RW intr on async adv door bell */ 113#define EHCI_CMD_ASE 0x00000020 /* RW async sched enable */ 114#define EHCI_CMD_PSE 0x00000010 /* RW periodic sched enable */ 115#define EHCI_CMD_FLS_M 0x0000000c /* RW/RO frame list size */ 116#define EHCI_CMD_FLS(x) (((x) >> 2) & 3) /* RW/RO frame list size */ 117#define EHCI_CMD_HCRESET 0x00000002 /* RW reset */ 118#define EHCI_CMD_RS 0x00000001 /* RW run/stop */ 119 120#define EHCI_USBSTS 0x04 /* RO, RW, RWC Status register */ 121#define EHCI_STS_ASS 0x00008000 /* RO async sched status */ 122#define EHCI_STS_PSS 0x00004000 /* RO periodic sched status */ 123#define EHCI_STS_REC 0x00002000 /* RO reclamation */ 124#define EHCI_STS_HCH 0x00001000 /* RO host controller halted */ 125#define EHCI_STS_IAA 0x00000020 /* RWC interrupt on async adv */ 126#define EHCI_STS_HSE 0x00000010 /* RWC host system error */ 127#define EHCI_STS_FLR 0x00000008 /* RWC frame list rollover */ 128#define EHCI_STS_PCD 0x00000004 /* RWC port change detect */ 129#define EHCI_STS_ERRINT 0x00000002 /* RWC error interrupt */ 130#define EHCI_STS_INT 0x00000001 /* RWC interrupt */ 131#define EHCI_STS_INTRS(x) ((x) & 0x3f) 132 133#define EHCI_NORMAL_INTRS (EHCI_STS_IAA | EHCI_STS_HSE | EHCI_STS_PCD | EHCI_STS_ERRINT | EHCI_STS_INT) 134 135#define EHCI_USBINTR 0x08 /* RW Interrupt register */ 136#define EHCI_INTR_IAAE 0x00000020 /* interrupt on async advance ena */ 137#define EHCI_INTR_HSEE 0x00000010 /* host system error ena */ 138#define EHCI_INTR_FLRE 0x00000008 /* frame list rollover ena */ 139#define EHCI_INTR_PCIE 0x00000004 /* port change ena */ 140#define EHCI_INTR_UEIE 0x00000002 /* USB error intr ena */ 141#define EHCI_INTR_UIE 0x00000001 /* USB intr ena */ 142 143#define EHCI_FRINDEX 0x0c /* RW Frame Index register */ 144 145#define EHCI_CTRLDSSEGMENT 0x10 /* RW Control Data Structure Segment */ 146 147#define EHCI_PERIODICLISTBASE 0x14 /* RW Periodic List Base */ 148#define EHCI_ASYNCLISTADDR 0x18 /* RW Async List Base */ 149 150#define EHCI_CONFIGFLAG 0x40 /* RW Configure Flag register */ 151#define EHCI_CONF_CF 0x00000001 /* RW configure flag */ 152 153#define EHCI_PORTSC(n) (0x40+4*(n)) /* RO, RW, RWC Port Status reg */ 154#define EHCI_PS_PSPD 0x0C000000 /* RO port speed (ETTF) */ 155#define EHCI_PS_PSPD_FS 0x00000000 /* Full speed (ETTF) */ 156#define EHCI_PS_PSPD_LS 0x04000000 /* Low speed (ETTF) */ 157#define EHCI_PS_PSPD_HS 0x08000000 /* High speed (ETTF) */ 158#define EHCI_PS_WKOC_E 0x00400000 /* RW wake on over current ena */ 159#define EHCI_PS_WKDSCNNT_E 0x00200000 /* RW wake on disconnect ena */ 160#define EHCI_PS_WKCNNT_E 0x00100000 /* RW wake on connect ena */ 161#define EHCI_PS_PTC 0x000f0000 /* RW port test control */ 162#define EHCI_PS_PIC 0x0000c000 /* RW port indicator control */ 163#define EHCI_PS_PO 0x00002000 /* RW port owner */ 164#define EHCI_PS_PP 0x00001000 /* RW,RO port power */ 165#define EHCI_PS_LS 0x00000c00 /* RO line status */ 166#define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == 0x00000400) 167#define EHCI_PS_PR 0x00000100 /* RW port reset */ 168#define EHCI_PS_SUSP 0x00000080 /* RW suspend */ 169#define EHCI_PS_FPR 0x00000040 /* RW force port resume */ 170#define EHCI_PS_OCC 0x00000020 /* RWC over current change */ 171#define EHCI_PS_OCA 0x00000010 /* RO over current active */ 172#define EHCI_PS_PEC 0x00000008 /* RWC port enable change */ 173#define EHCI_PS_PE 0x00000004 /* RW port enable */ 174#define EHCI_PS_CSC 0x00000002 /* RWC connect status change */ 175#define EHCI_PS_CS 0x00000001 /* RO connect status */ 176#define EHCI_PS_CLEAR (EHCI_PS_OCC|EHCI_PS_PEC|EHCI_PS_CSC) 177 178#define EHCI_PORT_RESET_COMPLETE 2 /* ms */ 179 180#define EHCI_FLALIGN_ALIGN 0x1000 181#define EHCI_MAX_PORTS 16 /* only 4 bits available in EHCI_HCS_N_PORTS */ 182 183/* No data structure may cross a page boundary. */ 184#define EHCI_PAGE_SHIFT 12 185#define EHCI_PAGE_SIZE (1 << EHCI_PAGE_SHIFT) 186#define EHCI_PAGE_MASK (EHCI_PAGE_SIZE - 1) 187#define EHCI_PAGE(x) ((x) & ~EHCI_PAGE_MASK) 188#define EHCI_PAGE_OFFSET(x) ((x) & EHCI_PAGE_MASK) 189#define EHCI_NPAGES(x) (((x) + EHCI_PAGE_MASK) >> EHCI_PAGE_SHIFT) 190 191typedef uint32_t ehci_link_t; 192#define EHCI_LINK_TERMINATE __BIT(0) 193#define EHCI_LINK_TYPE(x) ((x) & 0x00000006) 194#define EHCI_LINK_ITD 0x0 195#define EHCI_LINK_QH 0x2 196#define EHCI_LINK_SITD 0x4 197#define EHCI_LINK_FSTN 0x6 198#define EHCI_LINK_ADDR(x) ((x) &~ 0x1f) 199 200typedef uint32_t ehci_physaddr_t; 201 202typedef uint32_t ehci_isoc_trans_t; 203typedef uint32_t ehci_isoc_bufr_ptr_t; 204 205/* Isochronous Transfer Descriptor */ 206#define EHCI_ITD_ALIGN 32 207#define EHCI_ITD_NUFRAMES USB_UFRAMES_PER_FRAME 208#define EHCI_ITD_NBUFFERS 7 209typedef struct ehci_itd_t { 210 volatile ehci_link_t itd_next; 211 volatile ehci_isoc_trans_t itd_ctl[EHCI_ITD_NUFRAMES]; 212#define EHCI_ITD_STATUS_MASK __BITS(31,28) 213#define EHCI_ITD_GET_STATUS(x) __SHIFTOUT((x), EHCI_ITD_STATUS_MASK) 214#define EHCI_ITD_SET_STATUS(x) __SHIFTIN((x), EHCI_ITD_STATUS_MASK) 215#define EHCI_ITD_ACTIVE __BIT(31) 216#define EHCI_ITD_BUF_ERR __BIT(30) 217#define EHCI_ITD_BABBLE __BIT(29) 218#define EHCI_ITD_ERROR __BIT(28) 219#define EHCI_ITD_LEN_MASK __BITS(27,16) 220#define EHCI_ITD_GET_LEN(x) __SHIFTOUT((x), EHCI_ITD_LEN_MASK) 221#define EHCI_ITD_SET_LEN(x) __SHIFTIN((x), EHCI_ITD_LEN_MASK) 222#define EHCI_ITD_IOC __BIT(15) 223#define EHCI_ITD_GET_IOC(x) __SHIFTOUT((x), EHCI_ITD_IOC) 224#define EHCI_ITD_SET_IOC(x) __SHIFTIN((x), EHCI_ITD_IOC) 225#define EHCI_ITD_PG_MASK __BITS(14,12) 226#define EHCI_ITD_GET_PG(x) __SHIFTOUT((x), EHCI_ITD_PG_MASK) 227#define EHCI_ITD_SET_PG(x) __SHIFTIN((x), EHCI_ITD_PG_MASK) 228#define EHCI_ITD_OFFSET_MASK __BITS(11,0) 229#define EHCI_ITD_GET_OFFS(x) __SHIFTOUT((x), EHCI_ITD_OFFSET_MASK) 230#define EHCI_ITD_SET_OFFS(x) __SHIFTIN((x), EHCI_ITD_OFFSET_MASK) 231 volatile ehci_isoc_bufr_ptr_t itd_bufr[EHCI_ITD_NBUFFERS]; 232#define EHCI_ITD_BPTR_MASK __BITS(31,12) 233#define EHCI_ITD_GET_BPTR(x) ((x) & EHCI_ITD_BPTR_MASK) 234#define EHCI_ITD_SET_BPTR(x) ((x) & EHCI_ITD_BPTR_MASK) 235#define EHCI_ITD_EP_MASK __BITS(11,8) 236#define EHCI_ITD_GET_EP(x) __SHIFTOUT((x), EHCI_ITD_EP_MASK) 237#define EHCI_ITD_SET_EP(x) __SHIFTIN((x), EHCI_ITD_EP_MASK) 238#define EHCI_ITD_DADDR_MASK __BITS(6,0) 239#define EHCI_ITD_GET_DADDR(x) __SHIFTOUT((x), EHCI_ITD_DADDR_MASK) 240#define EHCI_ITD_SET_DADDR(x) __SHIFTIN((x), EHCI_ITD_DADDR_MASK) 241#define EHCI_ITD_DIR_MASK __BIT(11) 242#define EHCI_ITD_GET_DIR(x) __SHIFTOUT((x), EHCI_ITD_DIR_MASK) 243#define EHCI_ITD_SET_DIR(x) __SHIFTIN((x), EHCI_ITD_DIR_MASK) 244#define EHCI_ITD_MAXPKT_MASK __BITS(10,0) 245#define EHCI_ITD_GET_MAXPKT(x) __SHIFTOUT((x), EHCI_ITD_MAXPKT_MASK) 246#define EHCI_ITD_SET_MAXPKT(x) __SHIFTIN((x), EHCI_ITD_MAXPKT_MASK) 247#define EHCI_ITD_MULTI_MASK __BITS(1,0) 248#define EHCI_ITD_GET_MULTI(x) __SHIFTOUT((x), EHCI_ITD_MULTI_MASK) 249#define EHCI_ITD_SET_MULTI(x) __SHIFTIN((x), EHCI_ITD_MULTI_MASK) 250 volatile ehci_isoc_bufr_ptr_t itd_bufr_hi[EHCI_ITD_NBUFFERS]; 251} __aligned(EHCI_ITD_ALIGN) ehci_itd_t; 252 253/* Split Transaction Isochronous Transfer Descriptor */ 254#define EHCI_SITD_ALIGN 32 255typedef struct ehci_sitd_t { 256 volatile ehci_link_t sitd_next; 257 volatile uint32_t sitd_endp; 258#define EHCI_SITD_DIR_MASK __BIT(31) 259#define EHCI_SITD_PORT_MASK __BITS(30,24) 260#define EHCI_SITD_HUBA_MASK __BITS(22,16) 261#define EHCI_SITD_ENDPT_MASK __BITS(11,8) 262#define EHCI_SITD_DADDR_MASK __BITS(6,0) 263#define EHCI_SITD_SET_DIR(x) __SHIFTIN((x), EHCI_SITD_DIR_MASK) 264#define EHCI_SITD_SET_PORT(x) __SHIFTIN((x), EHCI_SITD_PORT_MASK) 265#define EHCI_SITD_SET_HUBA(x) __SHIFTIN((x), EHCI_SITD_HUBA_MASK) 266#define EHCI_SITD_SET_ENDPT(x) __SHIFTIN((x), EHCI_SITD_ENDPT_MASK) 267#define EHCI_SITD_SET_DADDR(x) __SHIFTIN((x), EHCI_SITD_DADDR_MASK) 268 volatile uint32_t sitd_sched; 269#define EHCI_SITD_SMASK_MASK __BITS(7,0) 270#define EHCI_SITD_CMASK_MASK __BITS(15,8) 271#define EHCI_SITD_SET_SMASK(x) __SHIFTIN((x), EHCI_SITD_SMASK_MASK) 272#define EHCI_SITD_SET_CMASK(x) __SHIFTIN((x), EHCI_SITD_CMASK_MASK) 273 volatile uint32_t sitd_trans; 274#define EHCI_SITD_IOC __BIT(31) 275#define EHCI_SITD_P __BIT(30) 276#define EHCI_SITD_LENGTH_MASK __BITS(25,16) 277#define EHCI_SITD_GET_LEN(x) __SHIFTOUT((x), EHCI_SITD_LENGTH_MASK) 278#define EHCI_SITD_SET_LEN(x) __SHIFTIN((x), EHCI_SITD_LENGTH_MASK) 279#define EHCI_SITD_STATUS_MASK __BITS(7,0) 280#define EHCI_SITD_ACTIVE 0x00000080 281#define EHCI_SITD_ERR 0x00000040 282#define EHCI_SITD_BUFERR 0x00000020 283#define EHCI_SITD_BABBLE 0x00000010 284#define EHCI_SITD_XACTERR 0x00000008 285#define EHCI_SITD_MISS 0x00000004 286#define EHCI_SITD_SPLITXSTATE 0x00000002 287 288#define EHCI_SITD_BUFFERS 2 289 290 volatile uint32_t sitd_buffer[EHCI_SITD_BUFFERS]; 291#define EHCI_SITD_SET_BPTR(x) ((x) & 0xfffff000) 292#define EHCI_SITD_SET_OFFS(x) ((x) & 0xfff) 293#define EHCI_SITD_TP_MASK __BITS(4,3) 294#define EHCI_SITD_TCOUNT_MASK __BITS(2,0) 295 296 volatile ehci_link_t sitd_back; 297 volatile uint32_t sitd_buffer_hi[EHCI_SITD_BUFFERS]; 298} __aligned(EHCI_SITD_ALIGN) ehci_sitd_t; 299 300/* Queue Element Transfer Descriptor */ 301#define EHCI_QTD_NBUFFERS 5 302#define EHCI_QTD_MAXTRANSFER (EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) 303#define EHCI_QTD_ALIGN 32 304typedef struct ehci_qtd_t { 305 volatile ehci_link_t qtd_next; 306 volatile ehci_link_t qtd_altnext; 307 volatile uint32_t qtd_status; 308#define EHCI_QTD_STATUS_MASK __BITS(7,0) 309#define EHCI_QTD_GET_STATUS(x) __SHIFTOUT((x), EHCI_QTD_STATUS_MASK) 310#define EHCI_QTD_SET_STATUS(x) __SHIFTIN((x), EHCI_QTD_STATUS_MASK) 311#define EHCI_QTD_ACTIVE 0x80 312#define EHCI_QTD_HALTED 0x40 313#define EHCI_QTD_BUFERR 0x20 314#define EHCI_QTD_BABBLE 0x10 315#define EHCI_QTD_XACTERR 0x08 316#define EHCI_QTD_MISSEDMICRO 0x04 317#define EHCI_QTD_SPLITXSTATE 0x02 318#define EHCI_QTD_PINGSTATE 0x01 319#define EHCI_QTD_STATERRS 0x3c 320#define EHCI_QTD_PID_MASK __BITS(9,8) 321#define EHCI_QTD_GET_PID(x) __SHIFTOUT((x), EHCI_QTD_PID_MASK) 322#define EHCI_QTD_SET_PID(x) __SHIFTIN((x), EHCI_QTD_PID_MASK) 323#define EHCI_QTD_PID_OUT 0x0 324#define EHCI_QTD_PID_IN 0x1 325#define EHCI_QTD_PID_SETUP 0x2 326#define EHCI_QTD_CERR_MASK __BITS(11,10) 327#define EHCI_QTD_GET_CERR(x) __SHIFTOUT((x), EHCI_QTD_CERR_MASK) 328#define EHCI_QTD_SET_CERR(x) __SHIFTIN((x), EHCI_QTD_CERR_MASK) 329#define EHCI_QTD_C_PAGE_MASK __BITS(14,12) 330#define EHCI_QTD_GET_C_PAGE(x) __SHIFTOUT((x), EHCI_QTD_C_PAGE_MASK) 331#define EHCI_QTD_SET_C_PAGE(x) __SHIFTIN((x), EHCI_QTD_C_PAGE_MASK) 332#define EHCI_QTD_IOC __BIT(15) 333#define EHCI_QTD_GET_IOC(x) __SHIFTOUT((x), EHCI_QTD_IOC) 334#define EHCI_QTD_BYTES_MASK __BITS(30,16) 335#define EHCI_QTD_GET_BYTES(x) __SHIFTOUT((x), EHCI_QTD_BYTES_MASK) 336#define EHCI_QTD_SET_BYTES(x) __SHIFTIN((x), EHCI_QTD_BYTES_MASK) 337#define EHCI_QTD_TOGGLE_MASK __BIT(31) 338#define EHCI_QTD_GET_TOGGLE(x) __SHIFTOUT((x), EHCI_QTD_TOGGLE_MASK) 339#define EHCI_QTD_SET_TOGGLE(x) __SHIFTIN((x), EHCI_QTD_TOGGLE_MASK) 340 volatile ehci_physaddr_t qtd_buffer[EHCI_QTD_NBUFFERS]; 341 volatile ehci_physaddr_t qtd_buffer_hi[EHCI_QTD_NBUFFERS]; 342} __aligned(EHCI_QTD_ALIGN) ehci_qtd_t; 343 344/* Queue Head */ 345#define EHCI_QH_ALIGN 32 346typedef struct ehci_qh_t { 347 volatile ehci_link_t qh_link; 348 volatile uint32_t qh_endp; 349#define EHCI_QH_ADDR_MASK __BITS(6,0) /* endpoint addr */ 350#define EHCI_QH_GET_ADDR(x) __SHIFTOUT((x), EHCI_QH_ADDR_MASK) 351#define EHCI_QH_SET_ADDR(x) __SHIFTIN((x), EHCI_QH_ADDR_MASK) 352#define EHCI_QH_INACT __BIT(7) /* inactivate on next */ 353#define EHCI_QH_GET_INACT(x) __SHIFTOUT((x), EHCI_QH_INACT) 354#define EHCI_QH_ENDPT_MASK __BITS(11,8) /* endpoint no */ 355#define EHCI_QH_GET_ENDPT(x) __SHIFTOUT((x), EHCI_QH_ENDPT_MASK) 356#define EHCI_QH_SET_ENDPT(x) __SHIFTIN((x), EHCI_QH_ENDPT_MASK) 357#define EHCI_QH_EPS_MASK __BITS(13,12) /* endpoint speed */ 358#define EHCI_QH_GET_EPS(x) __SHIFTOUT((x), EHCI_QH_EPS_MASK) 359#define EHCI_QH_SET_EPS(x) __SHIFTIN((x), EHCI_QH_EPS_MASK) 360#define EHCI_QH_SPEED_FULL 0x0 361#define EHCI_QH_SPEED_LOW 0x1 362#define EHCI_QH_SPEED_HIGH 0x2 363#define EHCI_QH_DTC __BIT(14) /* data toggle control */ 364#define EHCI_QH_GET_DTC(x) __SHIFTOUT((x), EHCI_QH_DTC) 365#define EHCI_QH_HRECL __BIT(15) /* head of reclamation */ 366#define EHCI_QH_GET_HRECL(x) __SHIFTOUT((x), EHCI_QH_HRECL) 367#define EHCI_QH_MPL_MASK __BITS(26,16) /* max packet len */ 368#define EHCI_QH_GET_MPL(x) __SHIFTOUT((x), EHCI_QH_MPL_MASK) 369#define EHCI_QH_SET_MPL(x) __SHIFTIN((x), EHCI_QH_MPL_MASK) 370#define EHCI_QH_CTL __BIT(27) /* control endpoint */ 371#define EHCI_QH_GET_CTL(x) __SHIFTOUT((x), EHCI_QH_CTL) 372#define EHCI_QH_NRL_MASK __BITS(31,28) /* NAK reload */ 373#define EHCI_QH_GET_NRL(x) __SHIFTOUT((x), EHCI_QH_NRL_MASK) 374#define EHCI_QH_SET_NRL(x) __SHIFTIN((x), EHCI_QH_NRL_MASK) 375 volatile uint32_t qh_endphub; 376#define EHCI_QH_SMASK_MASK __BITS(7,0) /* intr sched mask */ 377#define EHCI_QH_GET_SMASK(x) __SHIFTOUT((x), EHCI_QH_SMASK_MASK) 378#define EHCI_QH_SET_SMASK(x) __SHIFTIN((x), EHCI_QH_SMASK_MASK) 379#define EHCI_QH_CMASK_MASK __BITS(15,8) /* split completion mask */ 380#define EHCI_QH_GET_CMASK(x) __SHIFTOUT((x), EHCI_QH_CMASK_MASK) 381#define EHCI_QH_SET_CMASK(x) __SHIFTIN((x), EHCI_QH_CMASK_MASK) 382#define EHCI_QH_HUBA_MASK __BITS(22,16) /* hub address */ 383#define EHCI_QH_GET_HUBA(x) __SHIFTOUT((x), EHCI_QH_HUBA_MASK) 384#define EHCI_QH_SET_HUBA(x) __SHIFTIN((x), EHCI_QH_HUBA_MASK) 385#define EHCI_QH_PORT_MASK __BITS(29,23) /* hub port */ 386#define EHCI_QH_GET_PORT(x) __SHIFTOUT((x), EHCI_QH_PORT_MASK) 387#define EHCI_QH_SET_PORT(x) __SHIFTIN((x), EHCI_QH_PORT_MASK) 388#define EHCI_QH_MULTI_MASK __BITS(31,30) /* pipe multiplier */ 389#define EHCI_QH_GET_MULT(x) __SHIFTOUT((x), EHCI_QH_MULTI_MASK) 390#define EHCI_QH_SET_MULT(x) __SHIFTIN((x), EHCI_QH_MULTI_MASK) 391 volatile ehci_link_t qh_curqtd; 392 /* 393 * The QH descriptor contains a TD overlay, but it is not 394 * 32-byte aligned, so declare the fields instead of embedding 395 * a ehci_qtd_t directly. 396 */ 397 struct ehci_qh_qtd_t { 398 volatile ehci_link_t qtd_next; 399 volatile ehci_link_t qtd_altnext; 400 volatile uint32_t qtd_status; 401 volatile ehci_physaddr_t qtd_buffer[EHCI_QTD_NBUFFERS]; 402 volatile ehci_physaddr_t qtd_buffer_hi[EHCI_QTD_NBUFFERS]; 403 } qh_qtd; 404} __aligned(EHCI_QH_ALIGN) ehci_qh_t; 405 406/* Periodic Frame Span Traversal Node */ 407#define EHCI_FSTN_ALIGN 32 408typedef struct ehci_fstn_t { 409 volatile ehci_link_t fstn_link; 410 volatile ehci_link_t fstn_back; 411} __aligned(EHCI_FSTN_ALIGN) ehci_fstn_t; 412 413/* Debug Port */ 414#define PCI_CAP_DEBUGPORT_OFFSET __BITS(28,16) 415#define PCI_CAP_DEBUGPORT_BAR __BITS(31,29) 416/* Debug Port Registers, offset into DEBUGPORT_BAR at DEBUGPORT_OFFSET */ 417#define EHCI_DEBUG_SC 0x00 418/* Status/Control Register */ 419#define EHCI_DSC_DATA_LENGTH __BITS(3,0) 420#define EHCI_DSC_WRITE __BIT(4) 421#define EHCI_DSC_GO __BIT(5) 422#define EHCI_DSC_ERROR __BIT(6) 423#define EHCI_DSC_EXCEPTION __BITS(9,7) 424#define EHCI_DSC_EXCEPTION_NONE 0 425#define EHCI_DSC_EXCEPTION_XACT 1 426#define EHCI_DSC_EXCEPTION_HW 2 427#define EHCI_DSC_IN_USE __BIT(10) 428#define EHCI_DSC_DONE __BIT(16) 429#define EHCI_DSC_ENABLED __BIT(28) 430#define EHCI_DSC_OWNER __BIT(30) 431#define EHCI_DEBUG_UPR 0x04 432/* USB PIDs Register */ 433#define EHCI_DPR_TOKEN __BITS(7,0) 434#define EHCI_DPR_SEND __BITS(15,8) 435#define EHCI_DPR_RECEIVED __BITS(23,16) 436/* Data Registers */ 437#define EHCI_DEBUG_DATA0123 0x08 438#define EHCI_DEBUG_DATA4567 0x0c 439#define EHCI_DEBUG_DAR 0x10 440/* Device Address Register */ 441#define EHCI_DAR_ENDPOINT __BITS(3,0) 442#define EHCI_DAR_ADDRESS __BITS(14,8) 443 444#endif /* _DEV_USB_EHCIREG_H_ */ 445