1/*	$NetBSD: dbrivar.h,v 1.17 2021/02/06 09:15:11 isaki Exp $	*/
2
3/*
4 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
5 * Copyright (c) 1998, 1999 Brent Baccala (baccala@freesoft.org)
6 * Copyright (c) 2001, 2002 Jared D. McNeill <jmcneill@netbsd.org>
7 * Copyright (c) 2005 Michael Lorenz <macallan@netbsd.org>
8 * All rights reserved.
9 *
10 * This driver is losely based on a Linux driver written by Rudolf Koenig and
11 * Brent Baccala who kindly gave their permission to use their code in a
12 * BSD-licensed driver.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 *    notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 *    notice, this list of conditions and the following disclaimer in the
21 *    documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
35
36#ifndef DBRI_VAR_H
37#define DBRI_VAR_H
38
39#define	DBRI_NUM_COMMANDS	64
40#define	DBRI_NUM_DESCRIPTORS	32
41#define	DBRI_INT_BLOCKS		64
42
43#define DBRI_PIPE_MAX		32
44
45struct dbri_softc;
46
47enum direction {
48	in,
49	out
50};
51
52/* DBRI DMA transmit descriptor */
53struct dbri_xmit {
54	volatile uint32_t	flags;
55		#define TX_EOF	0x80000000	/* End of frame marker */
56		#define TX_BCNT(x)	((x&0x3fff)<<16)
57		#define TX_BINT	0x00008000	/* interrupt when EOF */
58		#define TX_MINT 0x00004000	/* marker interrupt */
59		#define TX_IDLE	0x00002000	/* send idles after data */
60		#define TX_FCNT(x)	(x&0x1fff)
61
62	volatile uint32_t	ba;		/* tx/rx buffer address */
63	volatile uint32_t	nda;		/* next descriptor address */
64	volatile uint32_t	status;
65		#define TS_OK		0x0001	/* transmission completed */
66		#define TS_ABORT	0x0004	/* transmission aborted */
67		#define TS_UNDERRUN	0x0008	/* DMA underrun */
68};
69
70struct dbri_recv {
71	volatile uint32_t	status;
72		#define RX_EOF		0x80000000
73		#define RX_COMPLETED	0x40000000
74		#define RX_BCNT(x)	((x & 0x3fff) << 16)
75		#define RX_CRCERROR	0x00000080
76		#define RX_BBC		0x00000040	/* bad byte count */
77		#define RX_ABORT	0x00000020
78		#define RX_OVERRUN	0x00000008
79	volatile uint32_t	ba;
80	volatile uint32_t	nda;
81	volatile uint32_t	flags;
82		#define RX_BSIZE(x)	(x & 0x3fff)
83		#define RX_FINAL	0x00008000
84		#define RX_MARKER	0x00004000
85};
86
87struct dbri_pipe {
88	uint32_t	sdp;		/* SDP command word */
89	enum direction	direction;
90	int		next;		/* next pipe in linked list */
91	int		prev;		/* previous pipe in linked list */
92	int		cycle;		/* offset of timeslot (bits) */
93	int		length;		/* length of timeslot (bits) */
94	int		desc;		/* index of active descriptor */
95	volatile uint32_t	*prec;	/* pointer to received fixed data */
96};
97
98struct dbri_desc {
99	int		busy;
100	void *		buf;		/* cpu view of buffer */
101	void *		buf_dvma;	/* device view */
102	bus_addr_t	dmabase;
103	bus_dma_segment_t dmaseg;
104	bus_dmamap_t	dmamap;
105	size_t		len;
106	void		(*callback)(void *);
107	void		*callback_args;
108	void		*softint;
109	struct dbri_softc *sc;
110};
111
112struct dbri_dma {
113	volatile uint32_t	command[DBRI_NUM_COMMANDS];
114	volatile int32_t	intr[DBRI_INT_BLOCKS];
115	struct dbri_xmit	xmit[DBRI_NUM_DESCRIPTORS];
116	struct dbri_recv	recv[DBRI_NUM_DESCRIPTORS];
117};
118
119struct dbri_softc {
120	device_t	sc_dev;		/* base device */
121
122	bus_space_handle_t sc_ioh;
123	bus_space_tag_t	sc_iot;
124	/* DMA buffer for sending commands to the chip */
125	bus_dma_tag_t	sc_dmat;
126	bus_dmamap_t	sc_dmamap;
127	bus_dma_segment_t sc_dmaseg;
128
129	int		sc_have_powerctl;
130	int		sc_init_done;
131	int		sc_powerstate;	/* DBRI's powered up or not */
132	int		sc_pmgrstate;	/* PWR_RESUME etc. */
133	int		sc_burst;	/* DVMA burst size in effect */
134
135	bus_addr_t	sc_dmabase;	/* VA of buffer we provide */
136	void *		sc_membase;
137	int		sc_bufsiz;	/* size of the buffer */
138	int		sc_locked;
139	int		sc_irqp;
140
141	int		sc_waitseen;
142
143	int		sc_playing;
144	int		sc_recording;
145
146	int		sc_liu_state;
147	void		(*sc_liu)(void *);
148	void		*sc_liu_args;
149
150	struct dbri_pipe sc_pipe[DBRI_PIPE_MAX];
151	struct dbri_desc sc_desc[DBRI_NUM_DESCRIPTORS];
152
153	struct cs4215_state	sc_mm;
154	int		sc_latt, sc_ratt;	/* output attenuation */
155	int		sc_linp, sc_rinp;	/* input volume */
156	int		sc_monitor;		/* monitor volume */
157	int		sc_input;		/* 0 - line, 1 - mic */
158	int		sc_whack_codec;	 /* 1 - codec needs control mode */
159
160	int		sc_ctl_mode;
161
162	uint32_t	sc_version;
163	int		sc_chi_pipe_in;
164	int		sc_chi_pipe_out;
165	int		sc_chi_bpf;
166
167	int		sc_desc_used;
168
169	struct audio_params sc_params;
170
171	struct dbri_dma	*sc_dma;
172
173	kmutex_t	sc_lock;
174	kmutex_t	sc_intr_lock;
175#ifndef DBRI_SPIN
176	kcondvar_t	sc_cv;
177#endif
178};
179
180#define dbri_dma_off(member, elem)	\
181	((uint32_t)(unsigned long)	\
182	 (&(((struct dbri_dma *)0)->member[elem])))
183
184#if 1
185#define DBRI_CMD(cmd, intr, value)	((cmd << 28) | (intr << 27) | value)
186#else
187#define	DBRI_CMD(cmd, intr, value)	((cmd << 28) | (1 << 27) | value)
188#endif
189#define DBRI_INTR_GETCHAN(v)		(((v) >> 24) & 0x3f)
190#define DBRI_INTR_GETCODE(v)		(((v) >> 20) & 0xf)
191#define DBRI_INTR_GETCMD(v)		(((v) >> 16) & 0xf)
192#define DBRI_INTR_GETVAL(v)		((v) & 0xffff)
193#define DBRI_INTR_GETRVAL(v)		((v) & 0xfffff)
194
195#define	DBRI_SDP_MODE(v)		((v) & (7 << 13))
196#define DBRI_PIPE(v)			((v) << 0)
197
198#endif /* DBRI_VAR_H */
199