ppbreg.h revision 1.9 
1/*	$NetBSD: ppbreg.h,v 1.9 2018/07/02 04:04:08 msaitoh Exp $	*/
2
3/*
4 * Copyright (c) 1996 Christopher G. Demetriou.  All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 *    must display the following acknowledgement:
16 *      This product includes software developed by Christopher G. Demetriou
17 *	for the NetBSD Project.
18 * 4. The name of the author may not be used to endorse or promote products
19 *    derived from this software without specific prior written permission
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/*
34 * PCI-PCI Bridge chip register definitions and macros.
35 * Derived from information found in the ``PCI to PCI Bridge
36 * Architecture Specification, Revision 1.0, April 5, 1994.''
37 *
38 * XXX much is missing.
39 */
40
41/*
42 * Register offsets
43 */
44#define	PPB_REG_BASE0		0x10		/* Base Addr Reg. 0 */
45#define	PPB_REG_BASE1		0x14		/* Base Addr Reg. 1 */
46#define	PPB_REG_BUSINFO		0x18		/* Bus information */
47#define	PPB_REG_IOSTATUS	0x1c		/* I/O base+lim & sec stat */
48#define	PPB_REG_MEM		0x20		/* Memory base/limit */
49#define	PPB_REG_PREFMEM		0x24		/* Pref Mem  base/limit */
50#define	PPB_REG_PREFBASE_HI32	0x28		/* Pref Mem base high bits */
51#define	PPB_REG_PREFLIM_HI32	0x2c		/* Pref Mem lim high bits */
52#define	PPB_REG_IO_HI		0x30		/* I/O base+lim high bits */
53#define	PPB_REG_BRIDGECONTROL	0x3c		/* bridge control register */
54
55/*
56 * Macros to extract the contents of the "Bus Info" register.
57 */
58#define	PPB_BUSINFO_PRIMARY(bir)					\
59	    ((bir >>  0) & 0xff)
60#define	PPB_BUSINFO_SECONDARY(bir)					\
61	    ((bir >>  8) & 0xff)
62#define	PPB_BUSINFO_SUBORDINATE(bir)					\
63	    ((bir >> 16) & 0xff)
64#define	PPB_BUSINFO_SECLAT(bir)						\
65	    ((bir >> 24) & 0xff)
66
67/*
68 * Routine to translate between secondary bus interrupt pin/device number and
69 * primary bus interrupt pin number.
70 */
71#define	PPB_INTERRUPT_SWIZZLE(pin, device)				\
72	    ((((pin) + (device) - 1) % 4) + 1)
73
74/*
75 * secondary bus I/O base and limits
76 */
77#define PPB_IOBASE_SHIFT   0
78#define PPB_IOLIMIT_SHIFT  8
79#define PPB_IO_MASK   0xf000
80#define PPB_IO_MIN    4096
81
82/*
83 * secondary bus memory base and limits
84 */
85#define PPB_MEMBASE_SHIFT  0
86#define PPB_MEMLIMIT_SHIFT 16
87#define PPB_MEM_MASK   0xfff00000
88#define PPB_MEM_SHIFT  16
89#define PPB_MEM_MIN    0x00100000
90
91/*
92 * bridge control register (see table 3.9 of ppb rev. 1.1)
93 *
94 * Note these are in the *upper* 16 bits of the Bridge Control
95 * Register (the bottom 16 are Interrupt Line and Interrupt Pin).
96 */
97#define	PPB_BC_BITBASE			   16
98
99#define PPB_BC_PARITYERRORRESPONSE_ENABLE  (1U << (0 + PPB_BC_BITBASE))
100#define PPB_BC_SERR_ENABLE                 (1U << (1 + PPB_BC_BITBASE))
101#define PPB_BC_ISA_ENABLE                  (1U << (2 + PPB_BC_BITBASE))
102#define PPB_BC_VGA_ENABLE                  (1U << (3 + PPB_BC_BITBASE))
103#define PPB_BC_VGA16_ENABLE                (1U << (4 + PPB_BC_BITBASE))
104#define PPB_BC_MASTER_ABORT_MODE           (1U << (5 + PPB_BC_BITBASE))
105#define PPB_BC_SECONDARY_RESET             (1U << (6 + PPB_BC_BITBASE))
106#define	PPB_BC_FAST_B2B_ENABLE		   (1U << (7 + PPB_BC_BITBASE))
107	/* PCI 2.2 */
108#define	PPB_BC_PRIMARY_DISCARD_TIMEOUT	   (1U << (8 + PPB_BC_BITBASE))
109#define	PPB_BC_SECONDARY_DISCARD_TIMEOUT   (1U << (9 + PPB_BC_BITBASE))
110#define	PPB_BC_DISCARD_TIMER_STATUS	   (1U << (10 + PPB_BC_BITBASE))
111#define	PPB_BC_DISCARD_TIMER_SERR_ENABLE   (1U << (11 + PPB_BC_BITBASE))
112