1/* $NetBSD: if_rtw_pci.c,v 1.25 2022/09/25 17:52:25 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 2004, 2005, 2010 David Young. All rights reserved. 5 * 6 * Adapted for the RTL8180 by David Young. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 18 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 19 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 20 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 21 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 23 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 28 * OF SUCH DAMAGE. 29 */ 30/*- 31 * Copyright (c) 1998, 1999, 2000, 2002 The NetBSD Foundation, Inc. 32 * All rights reserved. 33 * 34 * This code is derived from software contributed to The NetBSD Foundation 35 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 36 * NASA Ames Research Center; Charles M. Hannum; and David Young. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 48 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 49 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 50 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 51 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 52 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 53 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 54 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 55 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 56 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 57 * POSSIBILITY OF SUCH DAMAGE. 58 */ 59 60/* 61 * PCI bus front-end for the Realtek RTL8180 802.11 MAC/BBP chip. 62 * 63 * Derived from the ADMtek ADM8211 PCI bus front-end. 64 * 65 * Derived from the ``Tulip'' PCI bus front-end. 66 */ 67 68#include <sys/cdefs.h> 69__KERNEL_RCSID(0, "$NetBSD: if_rtw_pci.c,v 1.25 2022/09/25 17:52:25 thorpej Exp $"); 70 71#include <sys/param.h> 72#include <sys/systm.h> 73#include <sys/mbuf.h> 74#include <sys/kernel.h> 75#include <sys/socket.h> 76#include <sys/ioctl.h> 77#include <sys/errno.h> 78#include <sys/device.h> 79 80#include <machine/endian.h> 81 82#include <net/if.h> 83#include <net/if_dl.h> 84#include <net/if_media.h> 85#include <net/if_ether.h> 86 87#include <net80211/ieee80211_netbsd.h> 88#include <net80211/ieee80211_radiotap.h> 89#include <net80211/ieee80211_var.h> 90 91#include <sys/bus.h> 92#include <sys/intr.h> 93 94#include <dev/ic/rtwreg.h> 95#include <dev/ic/rtwvar.h> 96 97#include <dev/pci/pcivar.h> 98#include <dev/pci/pcireg.h> 99#include <dev/pci/pcidevs.h> 100 101/* 102 * PCI configuration space registers used by the RTL8180. 103 */ 104#define RTW_PCI_IOBA PCI_BAR(0) /* i/o mapped base */ 105#define RTW_PCI_MMBA PCI_BAR(1) /* memory mapped base */ 106 107struct rtw_pci_softc { 108 struct rtw_softc psc_rtw; 109 110 pcireg_t psc_csr; 111 void *psc_ih; 112 pci_chipset_tag_t psc_pc; 113 pci_intr_handle_t psc_pih; 114 pcitag_t psc_tag; 115}; 116 117static void rtw_pci_attach(device_t, device_t, void *); 118static int rtw_pci_detach(device_t, int); 119#if 0 120static void rtw_pci_funcregen(struct rtw_regs *, int); 121#endif 122static const struct rtw_pci_product * 123 rtw_pci_lookup(const struct pci_attach_args *); 124static int rtw_pci_match(device_t, cfdata_t, void *); 125static bool rtw_pci_resume(device_t, const pmf_qual_t *); 126static int rtw_pci_setup(struct rtw_pci_softc *); 127static bool rtw_pci_suspend(device_t, const pmf_qual_t *); 128 129CFATTACH_DECL3_NEW(rtw_pci, sizeof(struct rtw_pci_softc), 130 rtw_pci_match, rtw_pci_attach, rtw_pci_detach, NULL, NULL, NULL, 131 DVF_DETACH_SHUTDOWN); 132 133static const struct rtw_pci_product { 134 u_int32_t rpp_vendor; /* PCI vendor ID */ 135 u_int32_t rpp_product; /* PCI product ID */ 136 const char *rpp_product_name; 137} rtw_pci_products[] = { 138 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8180, 139 "Realtek RTL8180 802.11 MAC/BBP" }, 140#ifdef RTW_DEBUG 141#if 0 /* These came from openbsd, netbsd doesn't have the definitions. */ 142 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8185, 143 "Realtek RTL8185 802.11 MAC/BBP" }, 144 { PCI_VENDOR_BELKIN2, PCI_PRODUCT_BELKIN2_F5D7010, 145 "Belkin F5D7010" }, 146#endif 147#endif 148 { PCI_VENDOR_BELKIN, PCI_PRODUCT_BELKIN_F5D6001, 149 "Belkin F5D6001" }, 150 { PCI_VENDOR_BELKIN, PCI_PRODUCT_BELKIN_F5D6020V3, 151 "Belkin F5D6020v3" }, 152 {PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DWL610, 153 "DWL-610 D-Link Air 802.11b (RTL8180 MAC/BBP)"}, 154 { 0, 0, NULL }, 155}; 156 157static const struct rtw_pci_product * 158rtw_pci_lookup(const struct pci_attach_args *pa) 159{ 160 const struct rtw_pci_product *rpp; 161 162 for (rpp = rtw_pci_products; rpp->rpp_product_name != NULL; rpp++) { 163 if (PCI_VENDOR(pa->pa_id) == rpp->rpp_vendor && 164 PCI_PRODUCT(pa->pa_id) == rpp->rpp_product) 165 return rpp; 166 } 167 return NULL; 168} 169 170static int 171rtw_pci_match(device_t parent, cfdata_t match, void *aux) 172{ 173 struct pci_attach_args *pa = aux; 174 175 if (rtw_pci_lookup(pa) != NULL) 176 return 1; 177 178 return 0; 179} 180 181static void 182rtw_pci_attach(device_t parent, device_t self, void *aux) 183{ 184 struct rtw_pci_softc *psc = device_private(self); 185 struct rtw_softc *sc = &psc->psc_rtw; 186 struct rtw_regs *regs = &sc->sc_regs; 187 struct pci_attach_args *pa = aux; 188 const char *intrstr = NULL; 189 const struct rtw_pci_product *rpp; 190 char intrbuf[PCI_INTRSTR_LEN]; 191 192 sc->sc_dev = self; 193 sc->sc_dmat = pa->pa_dmat; 194 psc->psc_pc = pa->pa_pc; 195 psc->psc_tag = pa->pa_tag; 196 197 rpp = rtw_pci_lookup(pa); 198 if (rpp == NULL) { 199 printf("\n"); 200 panic("rtw_pci_attach: impossible"); 201 } 202 203 /* 204 * Get revision info, and set some chip-specific variables. 205 */ 206 sc->sc_rev = PCI_REVISION(pa->pa_class); 207 aprint_normal(": %s, revision %d.%d signature %08x\n", 208 rpp->rpp_product_name, 209 (sc->sc_rev >> 4) & 0xf, sc->sc_rev & 0xf, 210 pci_conf_read(psc->psc_pc, psc->psc_tag, 0x80)); 211 212 /* 213 * Map the device. 214 */ 215 psc->psc_csr = PCI_COMMAND_MASTER_ENABLE | 216 PCI_COMMAND_PARITY_ENABLE | 217 PCI_COMMAND_SERR_ENABLE; 218 if (pci_mapreg_map(pa, RTW_PCI_MMBA, PCI_MAPREG_TYPE_MEM, 0, 219 ®s->r_bt, ®s->r_bh, NULL, ®s->r_sz) == 0) { 220 RTW_DPRINTF(RTW_DEBUG_ATTACH, 221 ("%s: %s mapped %" PRIuMAX " bytes mem space\n", 222 device_xname(self), __func__, (uintmax_t)regs->r_sz)); 223 psc->psc_csr |= PCI_COMMAND_MEM_ENABLE; 224 } else if (pci_mapreg_map(pa, RTW_PCI_IOBA, PCI_MAPREG_TYPE_IO, 0, 225 ®s->r_bt, ®s->r_bh, NULL, ®s->r_sz) == 0) { 226 RTW_DPRINTF(RTW_DEBUG_ATTACH, 227 ("%s: %s mapped %" PRIuMAX " bytes I/O space\n", 228 device_xname(self), __func__, (uintmax_t)regs->r_sz)); 229 psc->psc_csr |= PCI_COMMAND_IO_ENABLE; 230 } else { 231 aprint_error_dev(self, "unable to map device registers\n"); 232 return; 233 } 234 235 /* 236 * Bring the chip out of powersave mode and initialize the 237 * configuration registers. 238 */ 239 if (rtw_pci_setup(psc) != 0) 240 return; 241 242 /* 243 * Map and establish our interrupt. 244 */ 245 if (pci_intr_map(pa, &psc->psc_pih)) { 246 aprint_error_dev(self, "unable to map interrupt\n"); 247 return; 248 } 249 intrstr = pci_intr_string(psc->psc_pc, psc->psc_pih, intrbuf, sizeof(intrbuf)); 250 psc->psc_ih = pci_intr_establish_xname(psc->psc_pc, psc->psc_pih, 251 IPL_NET, rtw_intr, sc, device_xname(self)); 252 if (psc->psc_ih == NULL) { 253 aprint_error_dev(self, "unable to establish interrupt"); 254 if (intrstr != NULL) 255 aprint_error(" at %s", intrstr); 256 aprint_error("\n"); 257 return; 258 } 259 260 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 261 262 /* 263 * Finish off the attach. 264 */ 265 rtw_attach(sc); 266 267 if (pmf_device_register(self, rtw_pci_suspend, rtw_pci_resume)) { 268 pmf_class_network_register(self, &sc->sc_if); 269 /* 270 * Power down the socket. 271 */ 272 pmf_device_suspend(self, &sc->sc_qual); 273 } else 274 aprint_error_dev(self, "couldn't establish power handler\n"); 275} 276 277static int 278rtw_pci_detach(device_t self, int flags) 279{ 280 struct rtw_pci_softc *psc = device_private(self); 281 struct rtw_softc *sc = &psc->psc_rtw; 282 struct rtw_regs *regs = &sc->sc_regs; 283 int rc; 284 285 if ((rc = rtw_detach(sc)) != 0) 286 return rc; 287 if (psc->psc_ih != NULL) 288 pci_intr_disestablish(psc->psc_pc, psc->psc_ih); 289 bus_space_unmap(regs->r_bt, regs->r_bh, regs->r_sz); 290 291 return 0; 292} 293 294static bool 295rtw_pci_resume(device_t self, const pmf_qual_t *qual) 296{ 297 struct rtw_pci_softc *psc = device_private(self); 298 struct rtw_softc *sc = &psc->psc_rtw; 299 300 /* XXX re-establishing interrupt shouldn't be needed */ 301 psc->psc_ih = pci_intr_establish_xname(psc->psc_pc, psc->psc_pih, 302 IPL_NET, rtw_intr, sc, device_xname(self)); 303 if (psc->psc_ih == NULL) { 304 aprint_error_dev(sc->sc_dev, "unable to establish interrupt\n"); 305 return false; 306 } 307 308 return rtw_resume(self, qual); 309} 310 311static bool 312rtw_pci_suspend(device_t self, const pmf_qual_t *qual) 313{ 314 struct rtw_pci_softc *psc = device_private(self); 315 316 if (!rtw_suspend(self, qual)) 317 return false; 318 319 /* Unhook the interrupt handler. */ 320 pci_intr_disestablish(psc->psc_pc, psc->psc_ih); 321 psc->psc_ih = NULL; 322 return true; 323} 324 325static int 326rtw_pci_setup(struct rtw_pci_softc *psc) 327{ 328 pcitag_t tag = psc->psc_tag; 329 pcireg_t bhlc, csr, lattimer; 330 device_t self = psc->psc_rtw.sc_dev; 331 int rc; 332 333 /* power up chip */ 334 rc = pci_activate(psc->psc_pc, psc->psc_tag, self, NULL); 335 336 if (rc != 0 && rc != EOPNOTSUPP) { 337 aprint_error_dev(self, "cannot activate (%d)\n", rc); 338 return rc; 339 } 340 341 /* I believe the datasheet tries to warn us that the RTL8180 342 * wants for 16 (0x10) to divide the latency timer. 343 */ 344 bhlc = pci_conf_read(psc->psc_pc, tag, PCI_BHLC_REG); 345 lattimer = rounddown(PCI_LATTIMER(bhlc), 0x10); 346 if (PCI_LATTIMER(bhlc) != lattimer) { 347 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 348 bhlc |= (lattimer << PCI_LATTIMER_SHIFT); 349 pci_conf_write(psc->psc_pc, tag, PCI_BHLC_REG, bhlc); 350 } 351 352 /* Enable the appropriate bits in the PCI CSR. */ 353 csr = pci_conf_read(psc->psc_pc, tag, PCI_COMMAND_STATUS_REG); 354 csr &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE); 355 csr |= psc->psc_csr; 356 pci_conf_write(psc->psc_pc, tag, PCI_COMMAND_STATUS_REG, csr); 357 358 return 0; 359} 360