1/* $NetBSD: if_ipw.c,v 1.77 2023/12/20 05:08:34 thorpej Exp $ */ 2/* FreeBSD: src/sys/dev/ipw/if_ipw.c,v 1.15 2005/11/13 17:17:40 damien Exp */ 3 4/*- 5 * Copyright (c) 2004, 2005 6 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31#include <sys/cdefs.h> 32__KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.77 2023/12/20 05:08:34 thorpej Exp $"); 33 34/*- 35 * Intel(R) PRO/Wireless 2100 MiniPCI driver 36 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 37 */ 38 39 40#include <sys/param.h> 41#include <sys/sockio.h> 42#include <sys/sysctl.h> 43#include <sys/mbuf.h> 44#include <sys/kernel.h> 45#include <sys/socket.h> 46#include <sys/systm.h> 47#include <sys/conf.h> 48#include <sys/proc.h> 49 50#include <sys/bus.h> 51#include <machine/endian.h> 52#include <sys/intr.h> 53 54#include <dev/pci/pcireg.h> 55#include <dev/pci/pcivar.h> 56#include <dev/pci/pcidevs.h> 57 58#include <net/bpf.h> 59#include <net/if.h> 60#include <net/if_arp.h> 61#include <net/if_dl.h> 62#include <net/if_ether.h> 63#include <net/if_media.h> 64#include <net/if_types.h> 65 66#include <net80211/ieee80211_var.h> 67#include <net80211/ieee80211_radiotap.h> 68 69#include <netinet/in.h> 70#include <netinet/in_systm.h> 71#include <netinet/in_var.h> 72#include <netinet/ip.h> 73 74#include <dev/firmload.h> 75 76#include <dev/pci/if_ipwreg.h> 77#include <dev/pci/if_ipwvar.h> 78 79#ifdef IPW_DEBUG 80#define DPRINTF(x) if (ipw_debug > 0) printf x 81#define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x 82int ipw_debug = 0; 83#else 84#define DPRINTF(x) 85#define DPRINTFN(n, x) 86#endif 87 88/* Permit loading the Intel firmware */ 89static int ipw_accept_eula; 90 91static int ipw_dma_alloc(struct ipw_softc *); 92static void ipw_release(struct ipw_softc *); 93static int ipw_match(device_t, cfdata_t, void *); 94static void ipw_attach(device_t, device_t, void *); 95static int ipw_detach(device_t, int); 96 97static int ipw_media_change(struct ifnet *); 98static void ipw_media_status(struct ifnet *, struct ifmediareq *); 99static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 100static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 101static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 102static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 103static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 104 struct ipw_soft_bd *, struct ipw_soft_buf *); 105static void ipw_rx_intr(struct ipw_softc *); 106static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 107static void ipw_tx_intr(struct ipw_softc *); 108static int ipw_intr(void *); 109static void ipw_softintr(void *); 110static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 111static int ipw_tx_start(struct ifnet *, struct mbuf *, 112 struct ieee80211_node *); 113static void ipw_start(struct ifnet *); 114static void ipw_watchdog(struct ifnet *); 115static int ipw_ioctl(struct ifnet *, u_long, void *); 116static int ipw_get_table1(struct ipw_softc *, uint32_t *); 117static int ipw_get_radio(struct ipw_softc *, int *); 118static void ipw_stop_master(struct ipw_softc *); 119static int ipw_reset(struct ipw_softc *); 120static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 121static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 122static int ipw_cache_firmware(struct ipw_softc *); 123static void ipw_free_firmware(struct ipw_softc *); 124static int ipw_config(struct ipw_softc *); 125static int ipw_init(struct ifnet *); 126static void ipw_stop(struct ifnet *, int); 127static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 128static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 129static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, uint32_t *); 130static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 131 bus_size_t); 132static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 133 bus_size_t); 134 135static inline uint8_t 136MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 137{ 138 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 139 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 140} 141 142static inline uint32_t 143MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 144{ 145 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 146 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 147} 148 149CFATTACH_DECL_NEW(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach, 150 ipw_detach, NULL); 151 152static int 153ipw_match(device_t parent, cfdata_t match, void *aux) 154{ 155 struct pci_attach_args *pa = aux; 156 157 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL && 158 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100) 159 return 1; 160 161 return 0; 162} 163 164/* Base Address Register */ 165#define IPW_PCI_BAR0 0x10 166 167static void 168ipw_attach(device_t parent, device_t self, void *aux) 169{ 170 struct ipw_softc *sc = device_private(self); 171 struct ieee80211com *ic = &sc->sc_ic; 172 struct ifnet *ifp = &sc->sc_if; 173 struct pci_attach_args *pa = aux; 174 const char *intrstr; 175 bus_space_tag_t memt; 176 bus_space_handle_t memh; 177 bus_addr_t base; 178 pci_intr_handle_t ih; 179 uint32_t data; 180 uint16_t val; 181 int i, error; 182 char intrbuf[PCI_INTRSTR_LEN]; 183 184 sc->sc_dev = self; 185 sc->sc_pct = pa->pa_pc; 186 sc->sc_pcitag = pa->pa_tag; 187 188 pci_aprint_devinfo(pa, NULL); 189 190 /* enable bus-mastering */ 191 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG); 192 data |= PCI_COMMAND_MASTER_ENABLE; 193 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 194 195 /* map the register window */ 196 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM | 197 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz); 198 if (error != 0) { 199 aprint_error_dev(sc->sc_dev, "could not map memory space\n"); 200 return; 201 } 202 203 sc->sc_st = memt; 204 sc->sc_sh = memh; 205 sc->sc_dmat = pa->pa_dmat; 206 sc->sc_fwname = "ipw2100-1.2.fw"; 207 208 /* disable interrupts */ 209 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 210 211 if (pci_intr_map(pa, &ih) != 0) { 212 aprint_error_dev(sc->sc_dev, "could not map interrupt\n"); 213 goto fail; 214 } 215 216 sc->sc_soft_ih = softint_establish(SOFTINT_NET, ipw_softintr, sc); 217 if (sc->sc_soft_ih == NULL) { 218 aprint_error_dev(sc->sc_dev, "could not establish softint\n"); 219 goto fail; 220 } 221 222 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 223 sc->sc_ih = pci_intr_establish_xname(sc->sc_pct, ih, IPL_NET, ipw_intr, 224 sc, device_xname(self)); 225 if (sc->sc_ih == NULL) { 226 aprint_error_dev(sc->sc_dev, "could not establish interrupt"); 227 if (intrstr != NULL) 228 aprint_error(" at %s", intrstr); 229 aprint_error("\n"); 230 goto fail; 231 } 232 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 233 234 if (ipw_reset(sc) != 0) { 235 aprint_error_dev(sc->sc_dev, "could not reset adapter\n"); 236 goto fail; 237 } 238 239 if (ipw_dma_alloc(sc) != 0) { 240 aprint_error_dev(sc->sc_dev, "could not allocate DMA resources\n"); 241 goto fail; 242 } 243 244 ifp->if_softc = sc; 245 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 246 ifp->if_init = ipw_init; 247 ifp->if_stop = ipw_stop; 248 ifp->if_ioctl = ipw_ioctl; 249 ifp->if_start = ipw_start; 250 ifp->if_watchdog = ipw_watchdog; 251 IFQ_SET_READY(&ifp->if_snd); 252 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 253 254 ic->ic_ifp = ifp; 255 ic->ic_phytype = IEEE80211_T_DS; 256 ic->ic_opmode = IEEE80211_M_STA; 257 ic->ic_state = IEEE80211_S_INIT; 258 259 /* set device capabilities */ 260 ic->ic_caps = 261 IEEE80211_C_SHPREAMBLE /* short preamble supported */ 262 | IEEE80211_C_TXPMGT /* tx power management */ 263 | IEEE80211_C_IBSS /* ibss mode */ 264 | IEEE80211_C_MONITOR /* monitor mode */ 265 ; 266 267 /* read MAC address from EEPROM */ 268 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 269 ic->ic_myaddr[0] = val >> 8; 270 ic->ic_myaddr[1] = val & 0xff; 271 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 272 ic->ic_myaddr[2] = val >> 8; 273 ic->ic_myaddr[3] = val & 0xff; 274 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 275 ic->ic_myaddr[4] = val >> 8; 276 ic->ic_myaddr[5] = val & 0xff; 277 278 /* set supported .11b rates */ 279 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 280 281 /* set supported .11b channels (read from EEPROM) */ 282 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 283 val = 0x7ff; /* default to channels 1-11 */ 284 val <<= 1; 285 for (i = 1; i < 16; i++) { 286 if (val & (1 << i)) { 287 ic->ic_channels[i].ic_freq = 288 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 289 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 290 } 291 } 292 293 /* check support for radio transmitter switch in EEPROM */ 294 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 295 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 296 297 aprint_normal_dev(sc->sc_dev, "802.11 address %s\n", 298 ether_sprintf(ic->ic_myaddr)); 299 300 if_initialize(ifp); 301 ieee80211_ifattach(ic); 302 /* Use common softint-based if_input */ 303 ifp->if_percpuq = if_percpuq_create(ifp); 304 if_register(ifp); 305 306 /* override state transition machine */ 307 sc->sc_newstate = ic->ic_newstate; 308 ic->ic_newstate = ipw_newstate; 309 310 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 311 312 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 313 sizeof(struct ieee80211_frame) + 64, &sc->sc_drvbpf); 314 315 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 316 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 317 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 318 319 sc->sc_txtap_len = sizeof sc->sc_txtapu; 320 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 321 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 322 323 /* 324 * Add a few sysctl knobs. 325 * XXX: Not yet 326 */ 327 sc->dwelltime = 100; 328 329 if (pmf_device_register(self, NULL, NULL)) 330 pmf_class_network_register(self, ifp); 331 else 332 aprint_error_dev(self, "couldn't establish power handler\n"); 333 334 ieee80211_announce(ic); 335 336 return; 337 338fail: ipw_detach(self, 0); 339} 340 341static int 342ipw_detach(device_t self, int flags) 343{ 344 struct ipw_softc *sc = device_private(self); 345 struct ifnet *ifp = &sc->sc_if; 346 347 if (ifp->if_softc) { 348 ipw_stop(ifp, 1); 349 ipw_free_firmware(sc); 350 351 bpf_detach(ifp); 352 ieee80211_ifdetach(&sc->sc_ic); 353 if_detach(ifp); 354 355 ipw_release(sc); 356 } 357 358 if (sc->sc_ih != NULL) { 359 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 360 sc->sc_ih = NULL; 361 } 362 363 if (sc->sc_soft_ih != NULL) { 364 softint_disestablish(sc->sc_soft_ih); 365 sc->sc_soft_ih = NULL; 366 } 367 368 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 369 370 return 0; 371} 372 373static int 374ipw_dma_alloc(struct ipw_softc *sc) 375{ 376 struct ipw_soft_bd *sbd; 377 struct ipw_soft_hdr *shdr; 378 struct ipw_soft_buf *sbuf; 379 int error, i, nsegs; 380 381 /* 382 * Allocate and map tx ring. 383 */ 384 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, 385 BUS_DMA_NOWAIT, &sc->tbd_map); 386 if (error != 0) { 387 aprint_error_dev(sc->sc_dev, "could not create tbd dma map\n"); 388 goto fail; 389 } 390 391 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0, 392 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 393 if (error != 0) { 394 aprint_error_dev(sc->sc_dev, "could not allocate tbd dma memory\n"); 395 goto fail; 396 } 397 398 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ, 399 (void **)&sc->tbd_list, BUS_DMA_NOWAIT); 400 if (error != 0) { 401 aprint_error_dev(sc->sc_dev, "could not map tbd dma memory\n"); 402 goto fail; 403 } 404 405 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list, 406 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT); 407 if (error != 0) { 408 aprint_error_dev(sc->sc_dev, "could not load tbd dma memory\n"); 409 goto fail; 410 } 411 412 (void)memset(sc->tbd_list, 0, IPW_TBD_SZ); 413 414 /* 415 * Allocate and map rx ring. 416 */ 417 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, 418 BUS_DMA_NOWAIT, &sc->rbd_map); 419 if (error != 0) { 420 aprint_error_dev(sc->sc_dev, "could not create rbd dma map\n"); 421 goto fail; 422 } 423 424 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0, 425 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 426 if (error != 0) { 427 aprint_error_dev(sc->sc_dev, "could not allocate rbd dma memory\n"); 428 goto fail; 429 } 430 431 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ, 432 (void **)&sc->rbd_list, BUS_DMA_NOWAIT); 433 if (error != 0) { 434 aprint_error_dev(sc->sc_dev, "could not map rbd dma memory\n"); 435 goto fail; 436 } 437 438 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list, 439 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT); 440 if (error != 0) { 441 aprint_error_dev(sc->sc_dev, "could not load rbd dma memory\n"); 442 goto fail; 443 } 444 445 (void)memset(sc->rbd_list, 0, IPW_RBD_SZ); 446 447 /* 448 * Allocate and map status ring. 449 */ 450 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 451 0, BUS_DMA_NOWAIT, &sc->status_map); 452 if (error != 0) { 453 aprint_error_dev(sc->sc_dev, "could not create status dma map\n"); 454 goto fail; 455 } 456 457 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0, 458 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT); 459 if (error != 0) { 460 aprint_error_dev(sc->sc_dev, "could not allocate status dma memory\n"); 461 goto fail; 462 } 463 464 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs, 465 IPW_STATUS_SZ, (void **)&sc->status_list, BUS_DMA_NOWAIT); 466 if (error != 0) { 467 aprint_error_dev(sc->sc_dev, "could not map status dma memory\n"); 468 goto fail; 469 } 470 471 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list, 472 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT); 473 if (error != 0) { 474 aprint_error_dev(sc->sc_dev, "could not load status dma memory\n"); 475 goto fail; 476 } 477 478 (void)memset(sc->status_list, 0, IPW_STATUS_SZ); 479 480 /* 481 * Allocate command DMA map. 482 */ 483 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd), 484 1, sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map); 485 if (error != 0) { 486 aprint_error_dev(sc->sc_dev, "could not create cmd dma map\n"); 487 goto fail; 488 } 489 490 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd), 491 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT); 492 if (error != 0) { 493 aprint_error_dev(sc->sc_dev, "could not allocate cmd dma memory\n"); 494 goto fail; 495 } 496 497 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs, 498 sizeof (struct ipw_cmd), (void **)&sc->cmd, BUS_DMA_NOWAIT); 499 if (error != 0) { 500 aprint_error_dev(sc->sc_dev, "could not map cmd dma memory\n"); 501 goto fail; 502 } 503 504 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd, 505 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT); 506 if (error != 0) { 507 aprint_error_dev(sc->sc_dev, "could not map cmd dma memory\n"); 508 return error; 509 } 510 511 /* 512 * Allocate and map hdr list. 513 */ 514 515 error = bus_dmamap_create(sc->sc_dmat, 516 IPW_NDATA * sizeof(struct ipw_hdr), 1, 517 sizeof(struct ipw_hdr), 0, BUS_DMA_NOWAIT, 518 &sc->hdr_map); 519 if (error != 0) { 520 aprint_error_dev(sc->sc_dev, "could not create hdr dma map\n"); 521 goto fail; 522 } 523 524 error = bus_dmamem_alloc(sc->sc_dmat, 525 IPW_NDATA * sizeof(struct ipw_hdr), PAGE_SIZE, 0, &sc->hdr_seg, 526 1, &nsegs, BUS_DMA_NOWAIT); 527 if (error != 0) { 528 aprint_error_dev(sc->sc_dev, "could not allocate hdr memory\n"); 529 goto fail; 530 } 531 532 error = bus_dmamem_map(sc->sc_dmat, &sc->hdr_seg, nsegs, 533 IPW_NDATA * sizeof(struct ipw_hdr), (void **)&sc->hdr_list, 534 BUS_DMA_NOWAIT); 535 if (error != 0) { 536 aprint_error_dev(sc->sc_dev, "could not map hdr memory\n"); 537 goto fail; 538 } 539 540 error = bus_dmamap_load(sc->sc_dmat, sc->hdr_map, sc->hdr_list, 541 IPW_NDATA * sizeof(struct ipw_hdr), NULL, BUS_DMA_NOWAIT); 542 if (error != 0) { 543 aprint_error_dev(sc->sc_dev, "could not load hdr memory\n"); 544 goto fail; 545 } 546 547 (void)memset(sc->hdr_list, 0, IPW_HDR_SZ); 548 549 /* 550 * Create DMA hdrs tailq. 551 */ 552 TAILQ_INIT(&sc->sc_free_shdr); 553 for (i = 0; i < IPW_NDATA; i++) { 554 shdr = &sc->shdr_list[i]; 555 shdr->hdr = sc->hdr_list + i; 556 shdr->offset = sizeof(struct ipw_hdr) * i; 557 shdr->addr = sc->hdr_map->dm_segs[0].ds_addr + shdr->offset; 558 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 559 } 560 561 /* 562 * Allocate tx buffers DMA maps. 563 */ 564 TAILQ_INIT(&sc->sc_free_sbuf); 565 for (i = 0; i < IPW_NDATA; i++) { 566 sbuf = &sc->tx_sbuf_list[i]; 567 568 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 569 IPW_MAX_NSEG, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map); 570 if (error != 0) { 571 aprint_error_dev(sc->sc_dev, "could not create txbuf dma map\n"); 572 goto fail; 573 } 574 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 575 } 576 577 /* 578 * Initialize tx ring. 579 */ 580 for (i = 0; i < IPW_NTBD; i++) { 581 sbd = &sc->stbd_list[i]; 582 sbd->bd = &sc->tbd_list[i]; 583 sbd->type = IPW_SBD_TYPE_NOASSOC; 584 } 585 586 /* 587 * Pre-allocate rx buffers and DMA maps 588 */ 589 for (i = 0; i < IPW_NRBD; i++) { 590 sbd = &sc->srbd_list[i]; 591 sbuf = &sc->rx_sbuf_list[i]; 592 sbd->bd = &sc->rbd_list[i]; 593 594 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA); 595 if (sbuf->m == NULL) { 596 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf\n"); 597 error = ENOMEM; 598 goto fail; 599 } 600 601 MCLGET(sbuf->m, M_DONTWAIT); 602 if (!(sbuf->m->m_flags & M_EXT)) { 603 m_freem(sbuf->m); 604 sbuf->m = NULL; 605 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf cluster\n"); 606 error = ENOMEM; 607 goto fail; 608 } 609 610 sbuf->m->m_pkthdr.len = sbuf->m->m_len = sbuf->m->m_ext.ext_size; 611 612 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 613 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sbuf->map); 614 if (error != 0) { 615 aprint_error_dev(sc->sc_dev, "could not create rxbuf dma map\n"); 616 m_freem(sbuf->m); 617 sbuf->m = NULL; 618 goto fail; 619 } 620 621 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 622 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 623 if (error != 0) { 624 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 625 sbuf->map = NULL; 626 m_freem(sbuf->m); 627 sbuf->m = NULL; 628 aprint_error_dev(sc->sc_dev, "could not map rxbuf dma memory\n"); 629 goto fail; 630 } 631 632 sbd->type = IPW_SBD_TYPE_DATA; 633 sbd->priv = sbuf; 634 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 635 sbd->bd->len = htole32(MCLBYTES); 636 637 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 638 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 639 640 } 641 642 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ, 643 BUS_DMASYNC_PREREAD); 644 645 return 0; 646 647fail: ipw_release(sc); 648 return error; 649} 650 651static void 652ipw_release(struct ipw_softc *sc) 653{ 654 struct ipw_soft_buf *sbuf; 655 int i; 656 657 if (sc->tbd_map != NULL) { 658 if (sc->tbd_list != NULL) { 659 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map); 660 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->tbd_list, 661 IPW_TBD_SZ); 662 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1); 663 } 664 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map); 665 } 666 667 if (sc->rbd_map != NULL) { 668 if (sc->rbd_list != NULL) { 669 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map); 670 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->rbd_list, 671 IPW_RBD_SZ); 672 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1); 673 } 674 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map); 675 } 676 677 if (sc->status_map != NULL) { 678 if (sc->status_list != NULL) { 679 bus_dmamap_unload(sc->sc_dmat, sc->status_map); 680 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->status_list, 681 IPW_RBD_SZ); 682 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1); 683 } 684 bus_dmamap_destroy(sc->sc_dmat, sc->status_map); 685 } 686 687 for (i = 0; i < IPW_NTBD; i++) 688 ipw_release_sbd(sc, &sc->stbd_list[i]); 689 690 if (sc->cmd_map != NULL) 691 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map); 692 693 if (sc->hdr_list != NULL) { 694 bus_dmamap_unload(sc->sc_dmat, sc->hdr_map); 695 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->hdr_list, 696 IPW_NDATA * sizeof(struct ipw_hdr)); 697 } 698 if (sc->hdr_map != NULL) { 699 bus_dmamem_free(sc->sc_dmat, &sc->hdr_seg, 1); 700 bus_dmamap_destroy(sc->sc_dmat, sc->hdr_map); 701 } 702 703 for (i = 0; i < IPW_NDATA; i++) 704 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map); 705 706 for (i = 0; i < IPW_NRBD; i++) { 707 sbuf = &sc->rx_sbuf_list[i]; 708 if (sbuf->map != NULL) { 709 if (sbuf->m != NULL) { 710 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 711 m_freem(sbuf->m); 712 } 713 bus_dmamap_destroy(sc->sc_dmat, sbuf->map); 714 } 715 } 716 717} 718 719static int 720ipw_media_change(struct ifnet *ifp) 721{ 722 int error; 723 724 error = ieee80211_media_change(ifp); 725 if (error != ENETRESET) 726 return error; 727 728 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 729 ipw_init(ifp); 730 731 return 0; 732} 733 734/* 735 * The firmware automatically adapts the transmit speed. We report the current 736 * transmit speed here. 737 */ 738static void 739ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 740{ 741#define N(a) (sizeof (a) / sizeof (a[0])) 742 struct ipw_softc *sc = ifp->if_softc; 743 struct ieee80211com *ic = &sc->sc_ic; 744 static const struct { 745 uint32_t val; 746 int rate; 747 } rates[] = { 748 { IPW_RATE_DS1, 2 }, 749 { IPW_RATE_DS2, 4 }, 750 { IPW_RATE_DS5, 11 }, 751 { IPW_RATE_DS11, 22 }, 752 }; 753 uint32_t val; 754 int rate, i; 755 756 imr->ifm_status = IFM_AVALID; 757 imr->ifm_active = IFM_IEEE80211; 758 if (ic->ic_state == IEEE80211_S_RUN) 759 imr->ifm_status |= IFM_ACTIVE; 760 761 /* read current transmission rate from adapter */ 762 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 763 764 /* convert ipw rate to 802.11 rate */ 765 for (i = 0; i < N(rates) && rates[i].val != val; i++); 766 rate = (i < N(rates)) ? rates[i].rate : 0; 767 768 imr->ifm_active |= IFM_IEEE80211_11B; 769 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 770 switch (ic->ic_opmode) { 771 case IEEE80211_M_STA: 772 break; 773 774 case IEEE80211_M_IBSS: 775 imr->ifm_active |= IFM_IEEE80211_ADHOC; 776 break; 777 778 case IEEE80211_M_MONITOR: 779 imr->ifm_active |= IFM_IEEE80211_MONITOR; 780 break; 781 782 case IEEE80211_M_AHDEMO: 783 case IEEE80211_M_HOSTAP: 784 /* should not get there */ 785 break; 786 } 787#undef N 788} 789 790static int 791ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, 792 int arg) 793{ 794 struct ifnet *ifp = ic->ic_ifp; 795 struct ipw_softc *sc = ifp->if_softc; 796 struct ieee80211_node *ni; 797 uint8_t macaddr[IEEE80211_ADDR_LEN]; 798 uint32_t len; 799 struct ipw_rx_radiotap_header *wr = &sc->sc_rxtap; 800 struct ipw_tx_radiotap_header *wt = &sc->sc_txtap; 801 802 switch (nstate) { 803 case IEEE80211_S_INIT: 804 break; 805 default: 806 KASSERT(ic->ic_curchan != IEEE80211_CHAN_ANYC); 807 KASSERT(ic->ic_curchan != NULL); 808 wt->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 809 wt->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 810 wr->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 811 wr->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 812 break; 813 } 814 815 switch (nstate) { 816 case IEEE80211_S_RUN: 817 DELAY(200); /* firmware needs a short delay here */ 818 819 len = IEEE80211_ADDR_LEN; 820 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 821 822 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 823 if (ni == NULL) 824 break; 825 826 ieee80211_ref_node(ni); 827 ieee80211_sta_join(ic, ni); 828 ieee80211_node_authorize(ni); 829 830 if (ic->ic_opmode == IEEE80211_M_STA) 831 ieee80211_notify_node_join(ic, ni, 1); 832 break; 833 834 case IEEE80211_S_INIT: 835 case IEEE80211_S_SCAN: 836 case IEEE80211_S_AUTH: 837 case IEEE80211_S_ASSOC: 838 break; 839 } 840 841 ic->ic_state = nstate; 842 return 0; 843} 844 845/* 846 * Read 16 bits at address 'addr' from the serial EEPROM. 847 */ 848static uint16_t 849ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 850{ 851 uint32_t tmp; 852 uint16_t val; 853 int n; 854 855 /* clock C once before the first command */ 856 IPW_EEPROM_CTL(sc, 0); 857 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 858 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 859 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 860 861 /* write start bit (1) */ 862 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 863 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 864 865 /* write READ opcode (10) */ 866 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 867 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 868 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 869 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 870 871 /* write address A7-A0 */ 872 for (n = 7; n >= 0; n--) { 873 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 874 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 875 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 876 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 877 } 878 879 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 880 881 /* read data Q15-Q0 */ 882 val = 0; 883 for (n = 15; n >= 0; n--) { 884 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 885 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 886 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 887 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 888 } 889 890 IPW_EEPROM_CTL(sc, 0); 891 892 /* clear Chip Select and clock C */ 893 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 894 IPW_EEPROM_CTL(sc, 0); 895 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 896 897 return le16toh(val); 898} 899 900static void 901ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 902{ 903 904 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd), 905 BUS_DMASYNC_POSTREAD); 906 907#ifdef IPW_DEBUG 908 struct ipw_cmd *cmd = mtod(sbuf->m, struct ipw_cmd *); 909 910 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 911 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 912 le32toh(cmd->status))); 913#endif 914 915 wakeup(&sc->cmd); 916} 917 918static void 919ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 920{ 921 struct ieee80211com *ic = &sc->sc_ic; 922 struct ifnet *ifp = sc->sc_ic.ic_ifp; 923 uint32_t state; 924 int s; 925 926 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state, 927 BUS_DMASYNC_POSTREAD); 928 929 state = le32toh(*mtod(sbuf->m, uint32_t *)); 930 931 DPRINTFN(2, ("entering state %u\n", state)); 932 933 s = splnet(); 934 935 switch (state) { 936 case IPW_STATE_ASSOCIATED: 937 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 938 break; 939 940 case IPW_STATE_SCANNING: 941 /* don't leave run state on background scan */ 942 if (ic->ic_state != IEEE80211_S_RUN) 943 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 944 945 ic->ic_flags |= IEEE80211_F_SCAN; 946 break; 947 948 case IPW_STATE_SCAN_COMPLETE: 949 ieee80211_notify_scan_done(ic); 950 ic->ic_flags &= ~IEEE80211_F_SCAN; 951 break; 952 953 case IPW_STATE_ASSOCIATION_LOST: 954 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 955 break; 956 957 case IPW_STATE_RADIO_DISABLED: 958 ic->ic_ifp->if_flags &= ~IFF_UP; 959 ipw_stop(ifp, 1); 960 break; 961 } 962 963 splx(s); 964} 965 966/* 967 * XXX: Hack to set the current channel to the value advertised in beacons or 968 * probe responses. Only used during AP detection. 969 */ 970static void 971ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 972{ 973 struct ieee80211_frame *wh; 974 uint8_t subtype; 975 uint8_t *frm, *efrm; 976 977 wh = mtod(m, struct ieee80211_frame *); 978 979 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 980 return; 981 982 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 983 984 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 985 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 986 return; 987 988 frm = (uint8_t *)(wh + 1); 989 efrm = mtod(m, uint8_t *) + m->m_len; 990 991 frm += 12; /* skip tstamp, bintval and capinfo fields */ 992 while (frm + 2 < efrm) { 993 if (*frm == IEEE80211_ELEMID_DSPARMS) { 994#if IEEE80211_CHAN_MAX < 255 995 if (frm[2] <= IEEE80211_CHAN_MAX) 996#endif 997 ic->ic_curchan = &ic->ic_channels[frm[2]]; 998 } 999 1000 frm += frm[1] + 2; 1001 } 1002} 1003 1004static void 1005ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 1006 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 1007{ 1008 struct ieee80211com *ic = &sc->sc_ic; 1009 struct ifnet *ifp = &sc->sc_if; 1010 struct mbuf *mnew, *m; 1011 struct ieee80211_frame *wh; 1012 struct ieee80211_node *ni; 1013 int error, s; 1014 1015 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 1016 status->rssi)); 1017 1018 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 1019 le32toh(status->len) > MCLBYTES) 1020 return; 1021 1022 /* 1023 * Try to allocate a new mbuf for this ring element and load it before 1024 * processing the current mbuf. If the ring element cannot be loaded, 1025 * drop the received packet and reuse the old mbuf. In the unlikely 1026 * case that the old mbuf can't be reloaded either, explicitly panic. 1027 */ 1028 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1029 if (mnew == NULL) { 1030 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf\n"); 1031 if_statinc(ifp, if_ierrors); 1032 return; 1033 } 1034 1035 MCLGET(mnew, M_DONTWAIT); 1036 if (!(mnew->m_flags & M_EXT)) { 1037 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf cluster\n"); 1038 m_freem(mnew); 1039 if_statinc(ifp, if_ierrors); 1040 return; 1041 } 1042 1043 mnew->m_pkthdr.len = mnew->m_len = mnew->m_ext.ext_size; 1044 1045 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len), 1046 BUS_DMASYNC_POSTREAD); 1047 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1048 1049 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, mnew, 1050 BUS_DMA_READ | BUS_DMA_NOWAIT); 1051 if (error != 0) { 1052 aprint_error_dev(sc->sc_dev, "could not load rx buf DMA map\n"); 1053 m_freem(mnew); 1054 1055 /* try to reload the old mbuf */ 1056 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, 1057 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT); 1058 if (error != 0) { 1059 /* very unlikely that it will fail... */ 1060 panic("%s: unable to remap rx buf", 1061 device_xname(sc->sc_dev)); 1062 } 1063 if_statinc(ifp, if_ierrors); 1064 return; 1065 } 1066 1067 /* 1068 * New mbuf successfully loaded, update Rx ring and continue 1069 * processing. 1070 */ 1071 m = sbuf->m; 1072 sbuf->m = mnew; 1073 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); 1074 1075 /* finalize mbuf */ 1076 m_set_rcvif(m, ifp); 1077 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1078 1079 s = splnet(); 1080 1081 if (sc->sc_drvbpf != NULL) { 1082 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1083 1084 tap->wr_antsignal = status->rssi; 1085 1086 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 1087 } 1088 1089 if (ic->ic_state == IEEE80211_S_SCAN) 1090 ipw_fix_channel(ic, m); 1091 1092 wh = mtod(m, struct ieee80211_frame *); 1093 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1094 1095 /* send the frame to the 802.11 layer */ 1096 ieee80211_input(ic, m, ni, status->rssi, 0); 1097 1098 /* node is no longer needed */ 1099 ieee80211_free_node(ni); 1100 1101 splx(s); 1102 1103 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, 1104 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD); 1105} 1106 1107static void 1108ipw_rx_intr(struct ipw_softc *sc) 1109{ 1110 struct ipw_status *status; 1111 struct ipw_soft_bd *sbd; 1112 struct ipw_soft_buf *sbuf; 1113 uint32_t r, i; 1114 1115 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1116 return; 1117 1118 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1119 1120 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1121 1122 /* firmware was killed, stop processing received frames */ 1123 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1124 return; 1125 1126 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1127 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1128 BUS_DMASYNC_POSTREAD); 1129 1130 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1131 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1132 BUS_DMASYNC_POSTREAD); 1133 1134 status = &sc->status_list[i]; 1135 sbd = &sc->srbd_list[i]; 1136 sbuf = sbd->priv; 1137 1138 switch (le16toh(status->code) & 0xf) { 1139 case IPW_STATUS_CODE_COMMAND: 1140 ipw_command_intr(sc, sbuf); 1141 break; 1142 1143 case IPW_STATUS_CODE_NEWSTATE: 1144 ipw_newstate_intr(sc, sbuf); 1145 break; 1146 1147 case IPW_STATUS_CODE_DATA_802_3: 1148 case IPW_STATUS_CODE_DATA_802_11: 1149 ipw_data_intr(sc, status, sbd, sbuf); 1150 break; 1151 1152 case IPW_STATUS_CODE_NOTIFICATION: 1153 DPRINTFN(2, ("received notification\n")); 1154 break; 1155 1156 default: 1157 aprint_error_dev(sc->sc_dev, "unknown status code %u\n", 1158 le16toh(status->code)); 1159 } 1160 1161 sbd->bd->flags = 0; 1162 1163 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 1164 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1165 BUS_DMASYNC_PREREAD); 1166 1167 bus_dmamap_sync(sc->sc_dmat, sc->status_map, 1168 i * sizeof (struct ipw_status), sizeof (struct ipw_status), 1169 BUS_DMASYNC_PREREAD); 1170 } 1171 1172 /* Tell the firmware what we have processed */ 1173 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1174 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1175} 1176 1177static void 1178ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1179{ 1180 struct ipw_soft_hdr *shdr; 1181 struct ipw_soft_buf *sbuf; 1182 1183 switch (sbd->type) { 1184 case IPW_SBD_TYPE_COMMAND: 1185 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 1186 0, sizeof(struct ipw_cmd), BUS_DMASYNC_POSTWRITE); 1187/* bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); */ 1188 break; 1189 1190 case IPW_SBD_TYPE_HEADER: 1191 shdr = sbd->priv; 1192 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, 1193 shdr->offset, sizeof(struct ipw_hdr), BUS_DMASYNC_POSTWRITE); 1194 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next); 1195 break; 1196 1197 case IPW_SBD_TYPE_DATA: 1198 sbuf = sbd->priv; 1199 1200 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 1201 0, sbuf->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1202 bus_dmamap_unload(sc->sc_dmat, sbuf->map); 1203 m_freem(sbuf->m); 1204 if (sbuf->ni != NULL) 1205 ieee80211_free_node(sbuf->ni); 1206 /* kill watchdog timer */ 1207 sc->sc_tx_timer = 0; 1208 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next); 1209 break; 1210 } 1211 sbd->type = IPW_SBD_TYPE_NOASSOC; 1212} 1213 1214static void 1215ipw_tx_intr(struct ipw_softc *sc) 1216{ 1217 struct ifnet *ifp = &sc->sc_if; 1218 struct ipw_soft_bd *sbd; 1219 uint32_t r, i; 1220 int s; 1221 1222 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1223 return; 1224 1225 s = splnet(); 1226 1227 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1228 1229 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1230 sbd = &sc->stbd_list[i]; 1231 1232 if (sbd->type == IPW_SBD_TYPE_DATA) 1233 if_statinc(ifp, if_opackets); 1234 1235 ipw_release_sbd(sc, sbd); 1236 sc->txfree++; 1237 } 1238 1239 /* remember what the firmware has processed */ 1240 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1241 1242 /* Call start() since some buffer descriptors have been released */ 1243 ifp->if_flags &= ~IFF_OACTIVE; 1244 ipw_start(ifp); /* in softint */ 1245 1246 splx(s); 1247} 1248 1249static int 1250ipw_intr(void *arg) 1251{ 1252 struct ipw_softc *sc = arg; 1253 uint32_t r; 1254 1255 r = CSR_READ_4(sc, IPW_CSR_INTR); 1256 if (r == 0 || r == 0xffffffff) 1257 return 0; 1258 1259 /* Disable interrupts */ 1260 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1261 1262 softint_schedule(sc->sc_soft_ih); 1263 return 1; 1264} 1265 1266static void 1267ipw_softintr(void *arg) 1268{ 1269 struct ipw_softc *sc = arg; 1270 uint32_t r; 1271 int s; 1272 1273 r = CSR_READ_4(sc, IPW_CSR_INTR); 1274 if (r == 0 || r == 0xffffffff) 1275 goto out; 1276 1277 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1278 aprint_error_dev(sc->sc_dev, "fatal error\n"); 1279 s = splnet(); 1280 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; 1281 ipw_stop(&sc->sc_if, 1); 1282 splx(s); 1283 } 1284 1285 if (r & IPW_INTR_FW_INIT_DONE) { 1286 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1287 wakeup(sc); 1288 } 1289 1290 if (r & IPW_INTR_RX_TRANSFER) 1291 ipw_rx_intr(sc); 1292 1293 if (r & IPW_INTR_TX_TRANSFER) 1294 ipw_tx_intr(sc); 1295 1296 /* Acknowledge all interrupts */ 1297 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1298 1299 out: 1300 /* Re-enable interrupts */ 1301 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1302} 1303 1304/* 1305 * Send a command to the firmware and wait for the acknowledgement. 1306 */ 1307static int 1308ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1309{ 1310 struct ipw_soft_bd *sbd; 1311 1312 sbd = &sc->stbd_list[sc->txcur]; 1313 1314 sc->cmd.type = htole32(type); 1315 sc->cmd.subtype = 0; 1316 sc->cmd.len = htole32(len); 1317 sc->cmd.seq = 0; 1318 1319 (void)memcpy(sc->cmd.data, data, len); 1320 1321 sbd->type = IPW_SBD_TYPE_COMMAND; 1322 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr); 1323 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1324 sbd->bd->nfrag = 1; 1325 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1326 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1327 1328 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd), 1329 BUS_DMASYNC_PREWRITE); 1330 1331 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1332 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd), 1333 BUS_DMASYNC_PREWRITE); 1334 1335 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1336 1337 /* kick firmware */ 1338 sc->txfree--; 1339 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1340 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1341 1342 /* Wait at most one second for command to complete */ 1343 return tsleep(&sc->cmd, 0, "ipwcmd", hz); 1344} 1345 1346static int 1347ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1348{ 1349 struct ipw_softc *sc = ifp->if_softc; 1350 struct ieee80211com *ic = &sc->sc_ic; 1351 struct ieee80211_frame *wh; 1352 struct ipw_soft_bd *sbd; 1353 struct ipw_soft_hdr *shdr; 1354 struct ipw_soft_buf *sbuf; 1355 struct ieee80211_key *k; 1356 struct mbuf *mnew; 1357 int error, i; 1358 1359 wh = mtod(m0, struct ieee80211_frame *); 1360 1361 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1362 k = ieee80211_crypto_encap(ic, ni, m0); 1363 if (k == NULL) { 1364 m_freem(m0); 1365 return ENOBUFS; 1366 } 1367 1368 /* packet header may have moved, reset our local pointer */ 1369 wh = mtod(m0, struct ieee80211_frame *); 1370 } 1371 1372 if (sc->sc_drvbpf != NULL) { 1373 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1374 1375 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0, BPF_D_OUT); 1376 } 1377 1378 shdr = TAILQ_FIRST(&sc->sc_free_shdr); 1379 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf); 1380 KASSERT(shdr != NULL && sbuf != NULL); 1381 1382 shdr->hdr->type = htole32(IPW_HDR_TYPE_SEND); 1383 shdr->hdr->subtype = 0; 1384 shdr->hdr->encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1385 shdr->hdr->encrypt = 0; 1386 shdr->hdr->keyidx = 0; 1387 shdr->hdr->keysz = 0; 1388 shdr->hdr->fragmentsz = 0; 1389 IEEE80211_ADDR_COPY(shdr->hdr->src_addr, wh->i_addr2); 1390 if (ic->ic_opmode == IEEE80211_M_STA) 1391 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr3); 1392 else 1393 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr1); 1394 1395 /* trim IEEE802.11 header */ 1396 m_adj(m0, sizeof (struct ieee80211_frame)); 1397 1398 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1399 BUS_DMA_NOWAIT); 1400 if (error != 0 && error != EFBIG) { 1401 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", 1402 error); 1403 m_freem(m0); 1404 return error; 1405 } 1406 1407 if (error != 0) { 1408 /* too many fragments, linearize */ 1409 1410 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1411 if (mnew == NULL) { 1412 m_freem(m0); 1413 return ENOMEM; 1414 } 1415 1416 m_copy_pkthdr(mnew, m0); 1417 1418 /* If the data won't fit in the header, get a cluster */ 1419 if (m0->m_pkthdr.len > MHLEN) { 1420 MCLGET(mnew, M_DONTWAIT); 1421 if (!(mnew->m_flags & M_EXT)) { 1422 m_freem(m0); 1423 m_freem(mnew); 1424 return ENOMEM; 1425 } 1426 } 1427 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, void *)); 1428 m_freem(m0); 1429 mnew->m_len = mnew->m_pkthdr.len; 1430 m0 = mnew; 1431 1432 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, 1433 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1434 if (error != 0) { 1435 aprint_error_dev(sc->sc_dev, 1436 "could not map mbuf (error %d)\n", error); 1437 m_freem(m0); 1438 return error; 1439 } 1440 } 1441 1442 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next); 1443 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next); 1444 1445 sbd = &sc->stbd_list[sc->txcur]; 1446 sbd->type = IPW_SBD_TYPE_HEADER; 1447 sbd->priv = shdr; 1448 sbd->bd->physaddr = htole32(shdr->addr); 1449 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1450 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs; 1451 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1452 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1453 1454 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, )\n", 1455 shdr->hdr->type, shdr->hdr->subtype, shdr->hdr->encrypted, 1456 shdr->hdr->encrypt)); 1457 DPRINTFN(5, ("%s->", ether_sprintf(shdr->hdr->src_addr))); 1458 DPRINTFN(5, ("%s\n", ether_sprintf(shdr->hdr->dst_addr))); 1459 1460 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1461 sc->txcur * sizeof (struct ipw_bd), 1462 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1463 1464 sc->txfree--; 1465 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1466 1467 sbuf->m = m0; 1468 sbuf->ni = ni; 1469 1470 for (i = 0; i < sbuf->map->dm_nsegs; i++) { 1471 sbd = &sc->stbd_list[sc->txcur]; 1472 1473 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr); 1474 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len); 1475 sbd->bd->nfrag = 0; 1476 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1477 if (i == sbuf->map->dm_nsegs - 1) { 1478 sbd->type = IPW_SBD_TYPE_DATA; 1479 sbd->priv = sbuf; 1480 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1481 } else { 1482 sbd->type = IPW_SBD_TYPE_NOASSOC; 1483 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1484 } 1485 1486 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, 1487 (int)sbuf->map->dm_segs[i].ds_len)); 1488 1489 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map, 1490 sc->txcur * sizeof (struct ipw_bd), 1491 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE); 1492 1493 sc->txfree--; 1494 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1495 } 1496 1497 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, shdr->offset, 1498 sizeof (struct ipw_hdr), BUS_DMASYNC_PREWRITE); 1499 1500 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sbuf->map->dm_mapsize, 1501 BUS_DMASYNC_PREWRITE); 1502 1503 /* Inform firmware about this new packet */ 1504 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1505 1506 return 0; 1507} 1508 1509static void 1510ipw_start(struct ifnet *ifp) 1511{ 1512 struct ipw_softc *sc = ifp->if_softc; 1513 struct ieee80211com *ic = &sc->sc_ic; 1514 struct mbuf *m0; 1515 struct ether_header *eh; 1516 struct ieee80211_node *ni; 1517 1518 if (ic->ic_state != IEEE80211_S_RUN) 1519 return; 1520 1521 for (;;) { 1522 IF_POLL(&ifp->if_snd, m0); 1523 if (m0 == NULL) 1524 break; 1525 1526 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1527 ifp->if_flags |= IFF_OACTIVE; 1528 break; 1529 } 1530 IF_DEQUEUE(&ifp->if_snd, m0); 1531 1532 KASSERT(m0->m_len >= sizeof(struct ether_header)); 1533 1534 eh = mtod(m0, struct ether_header *); 1535 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1536 if (ni == NULL) { 1537 m_freem(m0); 1538 continue; 1539 } 1540 1541 bpf_mtap(ifp, m0, BPF_D_OUT); 1542 1543 m0 = ieee80211_encap(ic, m0, ni); 1544 if (m0 == NULL) { 1545 ieee80211_free_node(ni); 1546 continue; 1547 } 1548 1549 bpf_mtap3(ic->ic_rawbpf, m0, BPF_D_OUT); 1550 1551 if (ipw_tx_start(ifp, m0, ni) != 0) { 1552 ieee80211_free_node(ni); 1553 if_statinc(ifp, if_oerrors); 1554 break; 1555 } 1556 1557 /* start watchdog timer */ 1558 sc->sc_tx_timer = 5; 1559 ifp->if_timer = 1; 1560 } 1561} 1562 1563static void 1564ipw_watchdog(struct ifnet *ifp) 1565{ 1566 struct ipw_softc *sc = ifp->if_softc; 1567 1568 ifp->if_timer = 0; 1569 1570 if (sc->sc_tx_timer > 0) { 1571 if (--sc->sc_tx_timer == 0) { 1572 aprint_error_dev(sc->sc_dev, "device timeout\n"); 1573 if_statinc(ifp, if_oerrors); 1574 ifp->if_flags &= ~IFF_UP; 1575 ipw_stop(ifp, 1); 1576 return; 1577 } 1578 ifp->if_timer = 1; 1579 } 1580 1581 ieee80211_watchdog(&sc->sc_ic); 1582} 1583 1584static int 1585ipw_get_table1(struct ipw_softc *sc, uint32_t *tbl) 1586{ 1587 uint32_t addr, size, data, i; 1588 int error; 1589 1590 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1591 return ENOTTY; 1592 1593 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 1594 1595 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1596 if ((error = copyout(&size, tbl, sizeof(size))) != 0) 1597 return error; 1598 1599 for (i = 1, ++tbl; i < size; i++, tbl++) { 1600 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); 1601 data = MEM_READ_4(sc, addr); 1602 if ((error = copyout(&data, tbl, sizeof(data))) != 0) 1603 return error; 1604 } 1605 return 0; 1606} 1607 1608static int 1609ipw_get_radio(struct ipw_softc *sc, int *ret) 1610{ 1611 uint32_t addr, data; 1612 1613 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1614 return ENOTTY; 1615 1616 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS); 1617 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1) 1618 data = -1; 1619 else if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) 1620 data = 0; 1621 else 1622 data = 1; 1623 1624 return copyout(&data, ret, sizeof(data)); 1625} 1626 1627static int 1628ipw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1629{ 1630#define IS_RUNNING(ifp) \ 1631 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 1632 1633 struct ipw_softc *sc = ifp->if_softc; 1634 struct ieee80211com *ic = &sc->sc_ic; 1635 struct ifreq *ifr = (struct ifreq *)data; 1636 int s, error = 0; 1637 1638 s = splnet(); 1639 1640 switch (cmd) { 1641 case SIOCSIFFLAGS: 1642 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1643 break; 1644 if (ifp->if_flags & IFF_UP) { 1645 if (!(ifp->if_flags & IFF_RUNNING)) 1646 ipw_init(ifp); 1647 } else { 1648 if (ifp->if_flags & IFF_RUNNING) 1649 ipw_stop(ifp, 1); 1650 } 1651 break; 1652 1653 case SIOCADDMULTI: 1654 case SIOCDELMULTI: 1655 /* XXX no h/w multicast filter? --dyoung */ 1656 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1657 /* setup multicast filter, etc */ 1658 error = 0; 1659 } 1660 break; 1661 1662 case SIOCGTABLE1: 1663 error = ipw_get_table1(sc, (uint32_t *)ifr->ifr_data); 1664 break; 1665 1666 case SIOCGRADIO: 1667 error = ipw_get_radio(sc, (int *)ifr->ifr_data); 1668 break; 1669 1670 case SIOCSIFMEDIA: 1671 if (ifr->ifr_media & IFM_IEEE80211_ADHOC) 1672 sc->sc_fwname = "ipw2100-1.2-i.fw"; 1673 else if (ifr->ifr_media & IFM_IEEE80211_MONITOR) 1674 sc->sc_fwname = "ipw2100-1.2-p.fw"; 1675 else 1676 sc->sc_fwname = "ipw2100-1.2.fw"; 1677 1678 ipw_free_firmware(sc); 1679 /* FALLTHROUGH */ 1680 default: 1681 error = ieee80211_ioctl(&sc->sc_ic, cmd, data); 1682 if (error != ENETRESET) 1683 break; 1684 1685 if (error == ENETRESET) { 1686 if (IS_RUNNING(ifp) && 1687 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1688 ipw_init(ifp); 1689 error = 0; 1690 } 1691 1692 } 1693 1694 splx(s); 1695 return error; 1696#undef IS_RUNNING 1697} 1698 1699static uint32_t 1700ipw_read_table1(struct ipw_softc *sc, uint32_t off) 1701{ 1702 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 1703} 1704 1705static void 1706ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 1707{ 1708 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 1709} 1710 1711static int 1712ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 1713{ 1714 uint32_t addr, info; 1715 uint16_t count, size; 1716 uint32_t total; 1717 1718 /* addr[4] + count[2] + size[2] */ 1719 addr = MEM_READ_4(sc, sc->table2_base + off); 1720 info = MEM_READ_4(sc, sc->table2_base + off + 4); 1721 1722 count = info >> 16; 1723 size = info & 0xffff; 1724 total = count * size; 1725 1726 if (total > *len) { 1727 *len = total; 1728 return EINVAL; 1729 } 1730 1731 *len = total; 1732 ipw_read_mem_1(sc, addr, buf, total); 1733 1734 return 0; 1735} 1736 1737static void 1738ipw_stop_master(struct ipw_softc *sc) 1739{ 1740 int ntries; 1741 1742 /* disable interrupts */ 1743 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1744 1745 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1746 for (ntries = 0; ntries < 50; ntries++) { 1747 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1748 break; 1749 DELAY(10); 1750 } 1751 if (ntries == 50) 1752 aprint_error_dev(sc->sc_dev, "timeout waiting for master\n"); 1753 1754 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1755 IPW_RST_PRINCETON_RESET); 1756 1757 sc->flags &= ~IPW_FLAG_FW_INITED; 1758} 1759 1760static int 1761ipw_reset(struct ipw_softc *sc) 1762{ 1763 int ntries; 1764 1765 ipw_stop_master(sc); 1766 1767 /* move adapter to D0 state */ 1768 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1769 IPW_CTL_INIT); 1770 1771 /* wait for clock stabilization */ 1772 for (ntries = 0; ntries < 1000; ntries++) { 1773 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1774 break; 1775 DELAY(200); 1776 } 1777 if (ntries == 1000) 1778 return EIO; 1779 1780 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1781 IPW_RST_SW_RESET); 1782 1783 DELAY(10); 1784 1785 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1786 IPW_CTL_INIT); 1787 1788 return 0; 1789} 1790 1791/* 1792 * Upload the microcode to the device. 1793 */ 1794static int 1795ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1796{ 1797 int ntries; 1798 1799 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1800 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1801 1802 MEM_WRITE_2(sc, 0x220000, 0x0703); 1803 MEM_WRITE_2(sc, 0x220000, 0x0707); 1804 1805 MEM_WRITE_1(sc, 0x210014, 0x72); 1806 MEM_WRITE_1(sc, 0x210014, 0x72); 1807 1808 MEM_WRITE_1(sc, 0x210000, 0x40); 1809 MEM_WRITE_1(sc, 0x210000, 0x00); 1810 MEM_WRITE_1(sc, 0x210000, 0x40); 1811 1812 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1813 1814 MEM_WRITE_1(sc, 0x210000, 0x00); 1815 MEM_WRITE_1(sc, 0x210000, 0x00); 1816 MEM_WRITE_1(sc, 0x210000, 0x80); 1817 1818 MEM_WRITE_2(sc, 0x220000, 0x0703); 1819 MEM_WRITE_2(sc, 0x220000, 0x0707); 1820 1821 MEM_WRITE_1(sc, 0x210014, 0x72); 1822 MEM_WRITE_1(sc, 0x210014, 0x72); 1823 1824 MEM_WRITE_1(sc, 0x210000, 0x00); 1825 MEM_WRITE_1(sc, 0x210000, 0x80); 1826 1827 for (ntries = 0; ntries < 10; ntries++) { 1828 if (MEM_READ_1(sc, 0x210000) & 1) 1829 break; 1830 DELAY(10); 1831 } 1832 if (ntries == 10) { 1833 aprint_error_dev(sc->sc_dev, "timeout waiting for ucode to initialize\n"); 1834 return EIO; 1835 } 1836 1837 MEM_WRITE_4(sc, 0x3000e0, 0); 1838 1839 return 0; 1840} 1841 1842/* set of macros to handle unaligned little endian data in firmware image */ 1843#define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1844#define GETLE16(p) ((p)[0] | (p)[1] << 8) 1845static int 1846ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1847{ 1848 u_char *p, *end; 1849 uint32_t dst; 1850 uint16_t len; 1851 int error; 1852 1853 p = fw; 1854 end = fw + size; 1855 while (p < end) { 1856 dst = GETLE32(p); p += 4; 1857 len = GETLE16(p); p += 2; 1858 1859 ipw_write_mem_1(sc, dst, p, len); 1860 p += len; 1861 } 1862 1863 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1864 IPW_IO_LED_OFF); 1865 1866 /* enable interrupts */ 1867 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1868 1869 /* kick the firmware */ 1870 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1871 1872 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1873 IPW_CTL_ALLOW_STANDBY); 1874 1875 /* wait at most one second for firmware initialization to complete */ 1876 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) { 1877 aprint_error_dev(sc->sc_dev, 1878 "timeout waiting for firmware initialization " 1879 "to complete\n"); 1880 return error; 1881 } 1882 1883 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1884 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1885 1886 return 0; 1887} 1888 1889/* 1890 * Store firmware into kernel memory so we can download it when we need to, 1891 * e.g when the adapter wakes up from suspend mode. 1892 */ 1893static int 1894ipw_cache_firmware(struct ipw_softc *sc) 1895{ 1896 struct ipw_firmware *fw = &sc->fw; 1897 struct ipw_firmware_hdr hdr; 1898 firmware_handle_t fwh; 1899 off_t fwsz, p; 1900 int error; 1901 1902 ipw_free_firmware(sc); 1903 1904 if (ipw_accept_eula == 0) { 1905 aprint_error_dev(sc->sc_dev, 1906 "EULA not accepted; please see the ipw(4) man page.\n"); 1907 return EPERM; 1908 } 1909 1910 if ((error = firmware_open("if_ipw", sc->sc_fwname, &fwh)) != 0) 1911 goto fail0; 1912 1913 fwsz = firmware_get_size(fwh); 1914 1915 if (fwsz < sizeof(hdr)) 1916 goto fail2; 1917 1918 if ((error = firmware_read(fwh, 0, &hdr, sizeof(hdr))) != 0) 1919 goto fail2; 1920 1921 fw->main_size = le32toh(hdr.main_size); 1922 fw->ucode_size = le32toh(hdr.ucode_size); 1923 1924 fw->main = firmware_malloc(fw->main_size); 1925 if (fw->main == NULL) { 1926 error = ENOMEM; 1927 goto fail1; 1928 } 1929 1930 fw->ucode = firmware_malloc(fw->ucode_size); 1931 if (fw->ucode == NULL) { 1932 error = ENOMEM; 1933 goto fail2; 1934 } 1935 1936 p = sizeof(hdr); 1937 if ((error = firmware_read(fwh, p, fw->main, fw->main_size)) != 0) 1938 goto fail3; 1939 1940 p += fw->main_size; 1941 if ((error = firmware_read(fwh, p, fw->ucode, fw->ucode_size)) != 0) 1942 goto fail3; 1943 1944 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 1945 fw->ucode_size)); 1946 1947 sc->flags |= IPW_FLAG_FW_CACHED; 1948 1949 firmware_close(fwh); 1950 1951 return 0; 1952 1953fail3: firmware_free(fw->ucode, fw->ucode_size); 1954fail2: firmware_free(fw->main, fw->main_size); 1955fail1: firmware_close(fwh); 1956fail0: 1957 return error; 1958} 1959 1960static void 1961ipw_free_firmware(struct ipw_softc *sc) 1962{ 1963 if (!(sc->flags & IPW_FLAG_FW_CACHED)) 1964 return; 1965 1966 firmware_free(sc->fw.main, sc->fw.main_size); 1967 firmware_free(sc->fw.ucode, sc->fw.ucode_size); 1968 1969 sc->flags &= ~IPW_FLAG_FW_CACHED; 1970} 1971 1972static int 1973ipw_config(struct ipw_softc *sc) 1974{ 1975 struct ieee80211com *ic = &sc->sc_ic; 1976 struct ifnet *ifp = &sc->sc_if; 1977 struct ipw_security security; 1978 struct ieee80211_key *k; 1979 struct ipw_wep_key wepkey; 1980 struct ipw_scan_options options; 1981 struct ipw_configuration config; 1982 uint32_t data; 1983 int error, i; 1984 1985 switch (ic->ic_opmode) { 1986 case IEEE80211_M_STA: 1987 case IEEE80211_M_HOSTAP: 1988 data = htole32(IPW_MODE_BSS); 1989 break; 1990 1991 case IEEE80211_M_IBSS: 1992 case IEEE80211_M_AHDEMO: 1993 data = htole32(IPW_MODE_IBSS); 1994 break; 1995 1996 case IEEE80211_M_MONITOR: 1997 data = htole32(IPW_MODE_MONITOR); 1998 break; 1999 } 2000 DPRINTF(("Setting mode to %u\n", le32toh(data))); 2001 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 2002 if (error != 0) 2003 return error; 2004 2005 if (ic->ic_opmode == IEEE80211_M_IBSS || 2006 ic->ic_opmode == IEEE80211_M_MONITOR) { 2007 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 2008 DPRINTF(("Setting channel to %u\n", le32toh(data))); 2009 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 2010 if (error != 0) 2011 return error; 2012 } 2013 2014 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2015 DPRINTF(("Enabling adapter\n")); 2016 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2017 } 2018 2019 DPRINTF(("Setting MAC to %s\n", ether_sprintf(ic->ic_myaddr))); 2020 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 2021 IEEE80211_ADDR_LEN); 2022 if (error != 0) 2023 return error; 2024 2025 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 2026 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 2027 2028 if (ic->ic_opmode == IEEE80211_M_IBSS) 2029 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 2030 if (ifp->if_flags & IFF_PROMISC) 2031 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 2032 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 2033 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 2034 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags)); 2035 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 2036 if (error != 0) 2037 return error; 2038 2039 data = htole32(0x3); /* 1, 2 */ 2040 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 2041 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 2042 if (error != 0) 2043 return error; 2044 2045 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 2046 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 2047 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 2048 if (error != 0) 2049 return error; 2050 2051 data = htole32(IPW_POWER_MODE_CAM); 2052 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 2053 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 2054 if (error != 0) 2055 return error; 2056 2057 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2058 data = htole32(32); /* default value */ 2059 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 2060 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 2061 sizeof data); 2062 if (error != 0) 2063 return error; 2064 } 2065 2066 data = htole32(ic->ic_rtsthreshold); 2067 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 2068 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 2069 if (error != 0) 2070 return error; 2071 2072 data = htole32(ic->ic_fragthreshold); 2073 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 2074 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 2075 if (error != 0) 2076 return error; 2077 2078#ifdef IPW_DEBUG 2079 if (ipw_debug > 0) { 2080 printf("Setting ESSID to "); 2081 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 2082 printf("\n"); 2083 } 2084#endif 2085 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 2086 ic->ic_des_esslen); 2087 if (error != 0) 2088 return error; 2089 2090 /* no mandatory BSSID */ 2091 DPRINTF(("Setting mandatory BSSID to null\n")); 2092 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 2093 if (error != 0) 2094 return error; 2095 2096 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 2097 DPRINTF(("Setting desired BSSID to %s\n", 2098 ether_sprintf(ic->ic_des_bssid))); 2099 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 2100 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 2101 if (error != 0) 2102 return error; 2103 } 2104 2105 (void)memset(&security, 0, sizeof(security)); 2106 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 2107 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 2108 security.ciphers = htole32(IPW_CIPHER_NONE); 2109 DPRINTF(("Setting authmode to %u\n", security.authmode)); 2110 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 2111 sizeof security); 2112 if (error != 0) 2113 return error; 2114 2115 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 2116 k = ic->ic_crypto.cs_nw_keys; 2117 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 2118 if (k->wk_keylen == 0) 2119 continue; 2120 2121 wepkey.idx = i; 2122 wepkey.len = k->wk_keylen; 2123 memset(wepkey.key, 0, sizeof(wepkey.key)); 2124 memcpy(wepkey.key, k->wk_key, k->wk_keylen); 2125 DPRINTF(("Setting wep key index %u len %u\n", 2126 wepkey.idx, wepkey.len)); 2127 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 2128 sizeof wepkey); 2129 if (error != 0) 2130 return error; 2131 } 2132 2133 data = htole32(ic->ic_crypto.cs_def_txkey); 2134 DPRINTF(("Setting tx key index to %u\n", le32toh(data))); 2135 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 2136 sizeof data); 2137 if (error != 0) 2138 return error; 2139 } 2140 2141 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 2142 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 2143 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 2144 if (error != 0) 2145 return error; 2146 2147#if 0 2148 struct ipw_wpa_ie ie; 2149 2150 memset(&ie, 0 sizeof(ie)); 2151 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 2152 DPRINTF(("Setting wpa ie\n")); 2153 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 2154 if (error != 0) 2155 return error; 2156#endif 2157 2158 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2159 data = htole32(ic->ic_bintval); 2160 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 2161 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 2162 sizeof data); 2163 if (error != 0) 2164 return error; 2165 } 2166 2167 options.flags = 0; 2168 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 2169 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 2170 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 2171 if (error != 0) 2172 return error; 2173 2174 /* finally, enable adapter (start scanning for an access point) */ 2175 DPRINTF(("Enabling adapter\n")); 2176 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2177} 2178 2179static int 2180ipw_init(struct ifnet *ifp) 2181{ 2182 struct ipw_softc *sc = ifp->if_softc; 2183 struct ipw_firmware *fw = &sc->fw; 2184 2185 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 2186 if (ipw_cache_firmware(sc) != 0) { 2187 aprint_error_dev(sc->sc_dev, 2188 "could not cache the firmware (%s)\n", 2189 sc->sc_fwname); 2190 goto fail; 2191 } 2192 } 2193 2194 ipw_stop(ifp, 0); 2195 2196 if (ipw_reset(sc) != 0) { 2197 aprint_error_dev(sc->sc_dev, "could not reset adapter\n"); 2198 goto fail; 2199 } 2200 2201 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { 2202 aprint_error_dev(sc->sc_dev, "could not load microcode\n"); 2203 goto fail; 2204 } 2205 2206 ipw_stop_master(sc); 2207 2208 /* 2209 * Setup tx, rx and status rings. 2210 */ 2211 sc->txold = IPW_NTBD - 1; 2212 sc->txcur = 0; 2213 sc->txfree = IPW_NTBD - 2; 2214 sc->rxcur = IPW_NRBD - 1; 2215 2216 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_map->dm_segs[0].ds_addr); 2217 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2218 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2219 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2220 2221 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_map->dm_segs[0].ds_addr); 2222 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2223 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2224 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2225 2226 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_map->dm_segs[0].ds_addr); 2227 2228 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { 2229 aprint_error_dev(sc->sc_dev, "could not load firmware\n"); 2230 goto fail; 2231 } 2232 2233 sc->flags |= IPW_FLAG_FW_INITED; 2234 2235 /* retrieve information tables base addresses */ 2236 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2237 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2238 2239 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2240 2241 if (ipw_config(sc) != 0) { 2242 aprint_error_dev(sc->sc_dev, "device configuration failed\n"); 2243 goto fail; 2244 } 2245 2246 ifp->if_flags &= ~IFF_OACTIVE; 2247 ifp->if_flags |= IFF_RUNNING; 2248 2249 return 0; 2250 2251fail: ifp->if_flags &= ~IFF_UP; 2252 ipw_stop(ifp, 0); 2253 2254 return EIO; 2255} 2256 2257static void 2258ipw_stop(struct ifnet *ifp, int disable) 2259{ 2260 struct ipw_softc *sc = ifp->if_softc; 2261 struct ieee80211com *ic = &sc->sc_ic; 2262 int i; 2263 2264 ipw_stop_master(sc); 2265 2266 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2267 2268 /* 2269 * Release tx buffers. 2270 */ 2271 for (i = 0; i < IPW_NTBD; i++) 2272 ipw_release_sbd(sc, &sc->stbd_list[i]); 2273 2274 sc->sc_tx_timer = 0; 2275 ifp->if_timer = 0; 2276 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2277 2278 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2279} 2280 2281static void 2282ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2283 bus_size_t count) 2284{ 2285 for (; count > 0; offset++, datap++, count--) { 2286 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2287 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2288 } 2289} 2290 2291static void 2292ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2293 bus_size_t count) 2294{ 2295 for (; count > 0; offset++, datap++, count--) { 2296 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2297 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2298 } 2299} 2300 2301SYSCTL_SETUP(sysctl_hw_ipw_accept_eula_setup, "sysctl hw.ipw.accept_eula") 2302{ 2303 const struct sysctlnode *rnode; 2304 const struct sysctlnode *cnode; 2305 2306 sysctl_createv(NULL, 0, NULL, &rnode, 2307 CTLFLAG_PERMANENT, 2308 CTLTYPE_NODE, "ipw", 2309 NULL, 2310 NULL, 0, 2311 NULL, 0, 2312 CTL_HW, CTL_CREATE, CTL_EOL); 2313 2314 sysctl_createv(NULL, 0, &rnode, &cnode, 2315 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, 2316 CTLTYPE_INT, "accept_eula", 2317 SYSCTL_DESCR("Accept Intel EULA and permit use of ipw(4) firmware"), 2318 NULL, 0, 2319 &ipw_accept_eula, sizeof(ipw_accept_eula), 2320 CTL_CREATE, CTL_EOL); 2321} 2322