ehci_pci.c revision 1.76 
1/*	$NetBSD: ehci_pci.c,v 1.76 2023/01/24 08:40:46 mlelstv Exp $	*/
2
3/*
4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Lennart Augustsson (lennart@augustsson.net).
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#include <sys/cdefs.h>
33__KERNEL_RCSID(0, "$NetBSD: ehci_pci.c,v 1.76 2023/01/24 08:40:46 mlelstv Exp $");
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/kernel.h>
38#include <sys/device.h>
39#include <sys/proc.h>
40#include <sys/queue.h>
41
42#include <sys/bus.h>
43
44#include <dev/pci/pcidevs.h>
45#include <dev/pci/pcivar.h>
46#include <dev/pci/usb_pci.h>
47
48#include <dev/usb/usb.h>
49#include <dev/usb/usbdi.h>
50#include <dev/usb/usbdivar.h>
51#include <dev/usb/usb_mem.h>
52
53#include <dev/usb/ehcireg.h>
54#include <dev/usb/ehcivar.h>
55
56#ifdef EHCI_DEBUG
57#define DPRINTF(x)	if (ehcidebug) printf x
58extern int ehcidebug;
59#else
60#define DPRINTF(x)
61#endif
62
63enum ehci_pci_quirk_flags {
64	EHCI_PCI_QUIRK_AMD_SB600 = 0x1,	/* always need a quirk */
65	EHCI_PCI_QUIRK_AMD_SB700 = 0x2,	/* depends on the SMB revision */
66};
67
68static const struct pci_quirkdata ehci_pci_quirks[] = {
69	{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_USB_EHCI,
70	    EHCI_PCI_QUIRK_AMD_SB600 },
71	{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_USB_EHCI,
72	    EHCI_PCI_QUIRK_AMD_SB700 },
73};
74
75static void ehci_release_ownership(ehci_softc_t *, pci_chipset_tag_t, pcitag_t);
76static void ehci_get_ownership(ehci_softc_t *, pci_chipset_tag_t, pcitag_t);
77static bool ehci_pci_suspend(device_t, const pmf_qual_t *);
78static bool ehci_pci_resume(device_t, const pmf_qual_t *);
79
80struct ehci_pci_softc {
81	ehci_softc_t		sc;
82	pci_chipset_tag_t	sc_pc;
83	pcitag_t		sc_tag;
84	pci_intr_handle_t	*sc_pihp;
85	void 			*sc_ih;		/* interrupt vectoring */
86	enum {
87		EHCI_INIT_NONE,
88		EHCI_INIT_INITED
89	} sc_init_state;
90};
91
92static int ehci_sb700_match(const struct pci_attach_args *);
93static int ehci_apply_amd_quirks(struct ehci_pci_softc *);
94static enum ehci_pci_quirk_flags ehci_pci_lookup_quirkdata(pci_vendor_id_t,
95    pci_product_id_t);
96
97#define EHCI_MAX_BIOS_WAIT		100 /* ms*10 */
98#define EHCI_SBx00_WORKAROUND_REG	0x50
99#define EHCI_SBx00_WORKAROUND_ENABLE	__BIT(27)
100
101static int
102ehci_pci_match(device_t parent, cfdata_t match, void *aux)
103{
104	struct pci_attach_args *pa = (struct pci_attach_args *) aux;
105
106	if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS &&
107	    PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB &&
108	    PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_EHCI)
109		return 1;
110
111	return 0;
112}
113
114static void
115ehci_pci_attach(device_t parent, device_t self, void *aux)
116{
117	struct ehci_pci_softc *sc = device_private(self);
118	struct pci_attach_args *pa = (struct pci_attach_args *)aux;
119	pci_chipset_tag_t pc = pa->pa_pc;
120	pcitag_t tag = pa->pa_tag;
121	char intrbuf[PCI_INTRSTR_LEN];
122	char const *intrstr;
123	struct usb_pci *up;
124	int ncomp, quirk;
125	pcireg_t csr;
126
127	sc->sc_init_state = EHCI_INIT_NONE;
128	sc->sc.sc_dev = self;
129	sc->sc.sc_bus.ub_hcpriv = sc;
130
131	pci_aprint_devinfo(pa, "USB controller");
132
133	/* Check for quirks */
134	quirk = ehci_pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id),
135	    PCI_PRODUCT(pa->pa_id));
136
137	/* Map I/O registers */
138	if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0,
139	    &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) {
140		sc->sc.sc_size = 0;
141		aprint_error_dev(self, "can't map memory space\n");
142		return;
143	}
144
145	sc->sc_pc = pc;
146	sc->sc_tag = tag;
147
148	const uint32_t hccparams = EREAD4(&sc->sc, EHCI_HCCPARAMS);
149
150	if (EHCI_HCC_64BIT(hccparams)) {
151		aprint_verbose_dev(self, "64-bit DMA");
152		if (pci_dma64_available(pa)) {
153			sc->sc.sc_bus.ub_dmatag = pa->pa_dmat64;
154			aprint_verbose("\n");
155		} else {
156			aprint_verbose(" - limited\n");
157			sc->sc.sc_bus.ub_dmatag = pa->pa_dmat;
158		}
159	} else {
160		aprint_verbose_dev(self, "32-bit DMA\n");
161		sc->sc.sc_bus.ub_dmatag = pa->pa_dmat;
162	}
163
164	/* Disable interrupts, so we don't get any spurious ones. */
165	sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH);
166	DPRINTF(("%s: offs=%d\n", device_xname(self), sc->sc.sc_offs));
167	EOWRITE4(&sc->sc, EHCI_USBINTR, 0);
168
169	/* Handle quirks */
170	switch (quirk) {
171	case EHCI_PCI_QUIRK_AMD_SB600:
172		ehci_apply_amd_quirks(sc);
173		break;
174	case EHCI_PCI_QUIRK_AMD_SB700:
175		if (pci_find_device(NULL, ehci_sb700_match))
176			ehci_apply_amd_quirks(sc);
177		break;
178	}
179
180	pcireg_t intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
181	int pin = PCI_INTERRUPT_PIN(intr);
182
183	/* Enable the device. */
184	csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
185	csr |= PCI_COMMAND_MASTER_ENABLE;
186	csr &= ~(pin ? PCI_COMMAND_INTERRUPT_DISABLE : 0);
187	pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
188
189	/* Map and establish the interrupt. */
190	if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0) != 0) {
191		aprint_error_dev(self, "couldn't map interrupt\n");
192		goto fail;
193	}
194
195	/*
196	 * Allocate IRQ
197	 */
198	intrstr = pci_intr_string(pc, sc->sc_pihp[0], intrbuf, sizeof(intrbuf));
199	pci_intr_setattr(pc, &sc->sc_pihp[0], PCI_INTR_MPSAFE, true);
200	sc->sc_ih = pci_intr_establish_xname(pc, sc->sc_pihp[0], IPL_USB,
201	    ehci_intr, sc, device_xname(self));
202	if (sc->sc_ih == NULL) {
203		pci_intr_release(sc->sc_pc, sc->sc_pihp, 1);
204		sc->sc_pihp = NULL;
205
206		aprint_error_dev(self, "couldn't establish interrupt");
207		if (intrstr != NULL)
208			aprint_error(" at %s", intrstr);
209		aprint_error("\n");
210		goto fail;
211	}
212	aprint_normal_dev(self, "interrupting at %s\n", intrstr);
213
214	switch (pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK) {
215	case PCI_USBREV_PRE_1_0:
216	case PCI_USBREV_1_0:
217	case PCI_USBREV_1_1:
218		sc->sc.sc_bus.ub_revision = USBREV_UNKNOWN;
219		aprint_verbose_dev(self, "pre-2.0 USB rev, device ignored\n");
220		goto fail;
221	case PCI_USBREV_2_0:
222		sc->sc.sc_bus.ub_revision = USBREV_2_0;
223		break;
224	default:
225		sc->sc.sc_bus.ub_revision = USBREV_UNKNOWN;
226		break;
227	}
228
229	/* Enable workaround for dropped interrupts as required */
230	switch (PCI_VENDOR(pa->pa_id)) {
231	case PCI_VENDOR_ATI:
232	case PCI_VENDOR_VIATECH:
233		sc->sc.sc_flags |= EHCIF_DROPPED_INTR_WORKAROUND;
234		aprint_normal_dev(self, "dropped intr workaround enabled\n");
235		break;
236	default:
237		break;
238	}
239
240	/*
241	 * Find companion controllers.  According to the spec they always
242	 * have lower function numbers so they should be enumerated already.
243	 */
244	const u_int maxncomp = EHCI_HCS_N_CC(EREAD4(&sc->sc, EHCI_HCSPARAMS));
245	KASSERT(maxncomp <= EHCI_COMPANION_MAX);
246	ncomp = 0;
247	TAILQ_FOREACH(up, &ehci_pci_alldevs, next) {
248		if (up->bus == pa->pa_bus && up->device == pa->pa_device &&
249		    !up->claimed) {
250			DPRINTF(("ehci_pci_attach: companion %s\n",
251			    device_xname(up->usb)));
252			sc->sc.sc_comps[ncomp++] = up->usb;
253			up->claimed = true;
254			if (ncomp == maxncomp)
255				break;
256		}
257	}
258	sc->sc.sc_ncomp = ncomp;
259
260	ehci_get_ownership(&sc->sc, pc, tag);
261
262	int err = ehci_init(&sc->sc);
263	if (err) {
264		aprint_error_dev(self, "init failed, error=%d\n", err);
265		goto fail;
266	}
267	sc->sc_init_state = EHCI_INIT_INITED;
268
269	if (!pmf_device_register1(self, ehci_pci_suspend, ehci_pci_resume,
270	    ehci_shutdown))
271		aprint_error_dev(self, "couldn't establish power handler\n");
272
273	/* Attach usb device. */
274	sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint,
275	    CFARGS_NONE);
276	return;
277
278fail:
279	if (sc->sc_ih) {
280		pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
281		sc->sc_ih = NULL;
282	}
283	if (sc->sc.sc_size) {
284		ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
285		bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
286		sc->sc.sc_size = 0;
287	}
288}
289
290static int
291ehci_pci_detach(device_t self, int flags)
292{
293	struct ehci_pci_softc *sc = device_private(self);
294	int rv;
295
296	if (sc->sc_init_state >= EHCI_INIT_INITED) {
297		rv = ehci_detach(&sc->sc, flags);
298		if (rv)
299			return rv;
300	}
301
302	pmf_device_deregister(self);
303	ehci_shutdown(self, flags);
304
305	/* disable interrupts */
306	EOWRITE4(&sc->sc, EHCI_USBINTR, 0);
307	/* XXX grotty hack to flush the write */
308	(void)EOREAD4(&sc->sc, EHCI_USBINTR);
309
310	if (sc->sc_ih != NULL) {
311		pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
312		sc->sc_ih = NULL;
313	}
314
315	if (sc->sc_pihp != NULL) {
316		pci_intr_release(sc->sc_pc, sc->sc_pihp, 1);
317		sc->sc_pihp = NULL;
318	}
319
320	if (sc->sc.sc_size) {
321		ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
322		bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
323		sc->sc.sc_size = 0;
324	}
325
326#if 1
327	/* XXX created in ehci.c */
328	if (sc->sc_init_state >= EHCI_INIT_INITED) {
329		mutex_destroy(&sc->sc.sc_rhlock);
330		mutex_destroy(&sc->sc.sc_lock);
331		mutex_destroy(&sc->sc.sc_intr_lock);
332		softint_disestablish(sc->sc.sc_doorbell_si);
333		softint_disestablish(sc->sc.sc_pcd_si);
334	}
335#endif
336
337	return 0;
338}
339
340CFATTACH_DECL3_NEW(ehci_pci, sizeof(struct ehci_pci_softc),
341    ehci_pci_match, ehci_pci_attach, ehci_pci_detach, ehci_activate, NULL,
342    ehci_childdet, DVF_DETACH_SHUTDOWN);
343
344#ifdef EHCI_DEBUG
345static void
346ehci_dump_caps(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag)
347{
348	uint32_t cparams, legctlsts, addr, cap, id;
349	int maxdump = 10;
350
351	cparams = EREAD4(sc, EHCI_HCCPARAMS);
352	addr = EHCI_HCC_EECP(cparams);
353	while (addr != 0) {
354		cap = pci_conf_read(pc, tag, addr);
355		id = EHCI_CAP_GET_ID(cap);
356		switch (id) {
357		case EHCI_CAP_ID_LEGACY:
358			legctlsts = pci_conf_read(pc, tag,
359			    addr + PCI_EHCI_USBLEGCTLSTS);
360			printf("ehci_dump_caps: legsup=0x%08x "
361			       "legctlsts=0x%08x\n", cap, legctlsts);
362			break;
363		default:
364			printf("ehci_dump_caps: cap=0x%08x\n", cap);
365			break;
366		}
367		if (--maxdump < 0)
368			break;
369		addr = EHCI_CAP_GET_NEXT(cap);
370	}
371}
372#endif
373
374static void
375ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag)
376{
377	const char *devname = device_xname(sc->sc_dev);
378	uint32_t cparams, addr, cap;
379	pcireg_t legsup;
380	int maxcap = 10;
381
382	cparams = EREAD4(sc, EHCI_HCCPARAMS);
383	addr = EHCI_HCC_EECP(cparams);
384	while (addr != 0) {
385		cap = pci_conf_read(pc, tag, addr);
386		if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY)
387			goto next;
388		legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP);
389		pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP,
390		    legsup & ~EHCI_LEG_HC_OS_OWNED);
391
392next:
393		if (--maxcap < 0) {
394			aprint_normal("%s: broken extended capabilities "
395				      "ignored\n", devname);
396			return;
397		}
398		addr = EHCI_CAP_GET_NEXT(cap);
399	}
400}
401
402static void
403ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag)
404{
405	const char *devname = device_xname(sc->sc_dev);
406	uint32_t cparams, addr, cap;
407	pcireg_t legsup;
408	int maxcap = 10;
409	int ms;
410
411#ifdef EHCI_DEBUG
412	if (ehcidebug)
413		ehci_dump_caps(sc, pc, tag);
414#endif
415	cparams = EREAD4(sc, EHCI_HCCPARAMS);
416	addr = EHCI_HCC_EECP(cparams);
417	while (addr != 0) {
418		cap = pci_conf_read(pc, tag, addr);
419		if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY)
420			goto next;
421		legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP);
422		if (legsup & EHCI_LEG_HC_BIOS_OWNED) {
423			/* Ask BIOS to give up ownership */
424			pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP,
425			    legsup | EHCI_LEG_HC_OS_OWNED);
426			for (ms = 0; ms < EHCI_MAX_BIOS_WAIT; ms++) {
427				legsup = pci_conf_read(pc, tag,
428				    addr + PCI_EHCI_USBLEGSUP);
429				if (!(legsup & EHCI_LEG_HC_BIOS_OWNED))
430					break;
431				delay(10000);
432			}
433			if (ms == EHCI_MAX_BIOS_WAIT) {
434				aprint_normal("%s: BIOS refuses to give up "
435				    "ownership, using force\n", devname);
436				pci_conf_write(pc, tag,
437				    addr + PCI_EHCI_USBLEGSUP, 0);
438			} else
439				aprint_verbose("%s: BIOS has given up "
440				    "ownership\n", devname);
441		}
442
443		/* Disable SMIs */
444		pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGCTLSTS, 0);
445
446next:
447		if (--maxcap < 0) {
448			aprint_normal("%s: broken extended capabilities "
449				      "ignored\n", devname);
450			return;
451		}
452		addr = EHCI_CAP_GET_NEXT(cap);
453	}
454
455}
456
457static bool
458ehci_pci_suspend(device_t dv, const pmf_qual_t *qual)
459{
460	struct ehci_pci_softc *sc = device_private(dv);
461
462	ehci_suspend(dv, qual);
463	ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
464
465	return true;
466}
467
468static bool
469ehci_pci_resume(device_t dv, const pmf_qual_t *qual)
470{
471	struct ehci_pci_softc *sc = device_private(dv);
472
473	ehci_get_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
474	return ehci_resume(dv, qual);
475}
476
477static int
478ehci_sb700_match(const struct pci_attach_args *pa)
479{
480	if (!(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI &&
481	    PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB))
482		return 0;
483
484	switch (PCI_REVISION(pa->pa_class)) {
485	case 0x3a:
486	case 0x3b:
487		return 1;
488	}
489
490	return 0;
491}
492
493static int
494ehci_apply_amd_quirks(struct ehci_pci_softc *sc)
495{
496	pcireg_t value;
497
498	aprint_normal_dev(sc->sc.sc_dev,
499	    "applying AMD SB600/SB700 USB freeze workaround\n");
500	value = pci_conf_read(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG);
501	pci_conf_write(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG,
502	    value | EHCI_SBx00_WORKAROUND_ENABLE);
503
504	return 0;
505}
506
507static enum ehci_pci_quirk_flags
508ehci_pci_lookup_quirkdata(pci_vendor_id_t vendor, pci_product_id_t product)
509{
510	int i;
511
512	for (i = 0; i < __arraycount(ehci_pci_quirks); i++) {
513		if (vendor == ehci_pci_quirks[i].vendor &&
514		    product == ehci_pci_quirks[i].product)
515			return ehci_pci_quirks[i].quirks;
516	}
517	return 0;
518}
519
520