1/*	$NetBSD: ehci_pci.c,v 1.77 2024/03/24 03:29:02 mrg Exp $	*/
2
3/*
4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Lennart Augustsson (lennart@augustsson.net).
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#include <sys/cdefs.h>
33__KERNEL_RCSID(0, "$NetBSD: ehci_pci.c,v 1.77 2024/03/24 03:29:02 mrg Exp $");
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/kernel.h>
38#include <sys/device.h>
39#include <sys/proc.h>
40#include <sys/queue.h>
41
42#include <sys/bus.h>
43
44#include <dev/pci/pcidevs.h>
45#include <dev/pci/pcivar.h>
46#include <dev/pci/usb_pci.h>
47
48#include <dev/usb/usb.h>
49#include <dev/usb/usbdi.h>
50#include <dev/usb/usbdivar.h>
51#include <dev/usb/usb_mem.h>
52
53#include <dev/usb/ehcireg.h>
54#include <dev/usb/ehcivar.h>
55
56#ifdef EHCI_DEBUG
57#define DPRINTF(x)	if (ehcidebug) printf x
58extern int ehcidebug;
59#else
60#define DPRINTF(x)
61#endif
62
63enum ehci_pci_quirk_flags {
64	EHCI_PCI_QUIRK_AMD_SB600 = 0x1,	/* always need a quirk */
65	EHCI_PCI_QUIRK_AMD_SB700 = 0x2,	/* depends on the SMB revision */
66};
67
68static const struct pci_quirkdata ehci_pci_quirks[] = {
69	{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_USB_EHCI,
70	    EHCI_PCI_QUIRK_AMD_SB600 },
71	{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_USB_EHCI,
72	    EHCI_PCI_QUIRK_AMD_SB700 },
73};
74
75static void ehci_release_ownership(ehci_softc_t *, pci_chipset_tag_t, pcitag_t);
76static void ehci_get_ownership(ehci_softc_t *, pci_chipset_tag_t, pcitag_t);
77static bool ehci_pci_suspend(device_t, const pmf_qual_t *);
78static bool ehci_pci_resume(device_t, const pmf_qual_t *);
79
80struct ehci_pci_softc {
81	ehci_softc_t		sc;
82	pci_chipset_tag_t	sc_pc;
83	pcitag_t		sc_tag;
84	pci_intr_handle_t	*sc_pihp;
85	void 			*sc_ih;		/* interrupt vectoring */
86	enum {
87		EHCI_INIT_NONE,
88		EHCI_INIT_OWNER,
89		EHCI_INIT_INITED
90	} sc_init_state;
91};
92
93static void ehci_pci_release_resources(struct ehci_pci_softc *);
94static int ehci_sb700_match(const struct pci_attach_args *);
95static int ehci_apply_amd_quirks(struct ehci_pci_softc *);
96static enum ehci_pci_quirk_flags ehci_pci_lookup_quirkdata(pci_vendor_id_t,
97    pci_product_id_t);
98
99#define EHCI_MAX_BIOS_WAIT		100 /* ms*10 */
100#define EHCI_SBx00_WORKAROUND_REG	0x50
101#define EHCI_SBx00_WORKAROUND_ENABLE	__BIT(27)
102
103static int
104ehci_pci_match(device_t parent, cfdata_t match, void *aux)
105{
106	struct pci_attach_args *pa = (struct pci_attach_args *) aux;
107
108	if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS &&
109	    PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB &&
110	    PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_EHCI)
111		return 1;
112
113	return 0;
114}
115
116static void
117ehci_pci_attach(device_t parent, device_t self, void *aux)
118{
119	struct ehci_pci_softc *sc = device_private(self);
120	struct pci_attach_args *pa = (struct pci_attach_args *)aux;
121	pci_chipset_tag_t pc = pa->pa_pc;
122	pcitag_t tag = pa->pa_tag;
123	char intrbuf[PCI_INTRSTR_LEN];
124	char const *intrstr;
125	struct usb_pci *up;
126	int ncomp, quirk;
127	pcireg_t csr;
128
129	sc->sc_init_state = EHCI_INIT_NONE;
130	sc->sc.sc_dev = self;
131	sc->sc.sc_bus.ub_hcpriv = sc;
132
133	pci_aprint_devinfo(pa, "USB controller");
134
135	/* Check for quirks */
136	quirk = ehci_pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id),
137	    PCI_PRODUCT(pa->pa_id));
138
139	/* Map I/O registers */
140	if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0,
141	    &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) {
142		sc->sc.sc_size = 0;
143		aprint_error_dev(self, "can't map memory space\n");
144		return;
145	}
146
147	sc->sc_pc = pc;
148	sc->sc_tag = tag;
149
150	const uint32_t hccparams = EREAD4(&sc->sc, EHCI_HCCPARAMS);
151
152	if (EHCI_HCC_64BIT(hccparams)) {
153		aprint_verbose_dev(self, "64-bit DMA");
154		if (pci_dma64_available(pa)) {
155			sc->sc.sc_bus.ub_dmatag = pa->pa_dmat64;
156			aprint_verbose("\n");
157		} else {
158			aprint_verbose(" - limited\n");
159			sc->sc.sc_bus.ub_dmatag = pa->pa_dmat;
160		}
161	} else {
162		aprint_verbose_dev(self, "32-bit DMA\n");
163		sc->sc.sc_bus.ub_dmatag = pa->pa_dmat;
164	}
165
166	/* Disable interrupts, so we don't get any spurious ones. */
167	sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH);
168	DPRINTF(("%s: offs=%d\n", device_xname(self), sc->sc.sc_offs));
169	EOWRITE4(&sc->sc, EHCI_USBINTR, 0);
170
171	/* Handle quirks */
172	switch (quirk) {
173	case EHCI_PCI_QUIRK_AMD_SB600:
174		ehci_apply_amd_quirks(sc);
175		break;
176	case EHCI_PCI_QUIRK_AMD_SB700:
177		if (pci_find_device(NULL, ehci_sb700_match))
178			ehci_apply_amd_quirks(sc);
179		break;
180	}
181
182	pcireg_t intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
183	int pin = PCI_INTERRUPT_PIN(intr);
184
185	/* Enable the device. */
186	csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
187	csr |= PCI_COMMAND_MASTER_ENABLE;
188	csr &= ~(pin ? PCI_COMMAND_INTERRUPT_DISABLE : 0);
189	pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
190
191	/* Map and establish the interrupt. */
192	if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0) != 0) {
193		aprint_error_dev(self, "couldn't map interrupt\n");
194		goto fail;
195	}
196
197	/*
198	 * Allocate IRQ
199	 */
200	intrstr = pci_intr_string(pc, sc->sc_pihp[0], intrbuf, sizeof(intrbuf));
201	pci_intr_setattr(pc, &sc->sc_pihp[0], PCI_INTR_MPSAFE, true);
202	sc->sc_ih = pci_intr_establish_xname(pc, sc->sc_pihp[0], IPL_USB,
203	    ehci_intr, sc, device_xname(self));
204	if (sc->sc_ih == NULL) {
205		aprint_error_dev(self, "couldn't establish interrupt");
206		if (intrstr != NULL)
207			aprint_error(" at %s", intrstr);
208		aprint_error("\n");
209		goto fail;
210	}
211	aprint_normal_dev(self, "interrupting at %s\n", intrstr);
212
213	switch (pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK) {
214	case PCI_USBREV_PRE_1_0:
215	case PCI_USBREV_1_0:
216	case PCI_USBREV_1_1:
217		sc->sc.sc_bus.ub_revision = USBREV_UNKNOWN;
218		aprint_verbose_dev(self, "pre-2.0 USB rev, device ignored\n");
219		goto fail;
220	case PCI_USBREV_2_0:
221		sc->sc.sc_bus.ub_revision = USBREV_2_0;
222		break;
223	default:
224		sc->sc.sc_bus.ub_revision = USBREV_UNKNOWN;
225		break;
226	}
227
228	/* Enable workaround for dropped interrupts as required */
229	switch (PCI_VENDOR(pa->pa_id)) {
230	case PCI_VENDOR_ATI:
231	case PCI_VENDOR_VIATECH:
232		sc->sc.sc_flags |= EHCIF_DROPPED_INTR_WORKAROUND;
233		aprint_normal_dev(self, "dropped intr workaround enabled\n");
234		break;
235	default:
236		break;
237	}
238
239	/*
240	 * Find companion controllers.  According to the spec they always
241	 * have lower function numbers so they should be enumerated already.
242	 */
243	const u_int maxncomp = EHCI_HCS_N_CC(EREAD4(&sc->sc, EHCI_HCSPARAMS));
244	KASSERT(maxncomp <= EHCI_COMPANION_MAX);
245	ncomp = 0;
246	TAILQ_FOREACH(up, &ehci_pci_alldevs, next) {
247		if (up->bus == pa->pa_bus && up->device == pa->pa_device &&
248		    !up->claimed) {
249			DPRINTF(("ehci_pci_attach: companion %s\n",
250			    device_xname(up->usb)));
251			sc->sc.sc_comps[ncomp++] = up->usb;
252			up->claimed = true;
253			if (ncomp == maxncomp)
254				break;
255		}
256	}
257	sc->sc.sc_ncomp = ncomp;
258
259	ehci_get_ownership(&sc->sc, pc, tag);
260	sc->sc_init_state = EHCI_INIT_OWNER;
261
262	int err = ehci_init(&sc->sc);
263	if (err) {
264		aprint_error_dev(self, "init failed, error=%d\n", err);
265		goto fail;
266	}
267	sc->sc_init_state = EHCI_INIT_INITED;
268
269	pmf_device_register1(self, ehci_pci_suspend, ehci_pci_resume,
270	    ehci_shutdown);
271
272	/* Attach usb device. */
273	sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint,
274	    CFARGS_NONE);
275	return;
276
277fail:
278	ehci_pci_release_resources(sc);
279	pmf_device_register(self, NULL, NULL);
280}
281
282static void
283ehci_pci_release_resources(struct ehci_pci_softc *sc)
284{
285	if (sc->sc_init_state >= EHCI_INIT_OWNER)
286		ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
287
288	if (sc->sc_ih) {
289		pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
290		sc->sc_ih = NULL;
291	}
292	if (sc->sc_pihp != NULL) {
293		pci_intr_release(sc->sc_pc, sc->sc_pihp, 1);
294		sc->sc_pihp = NULL;
295	}
296
297	if (sc->sc.sc_size) {
298		bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
299		sc->sc.sc_size = 0;
300	}
301
302	sc->sc_init_state = EHCI_INIT_NONE;
303}
304
305static int
306ehci_pci_detach(device_t self, int flags)
307{
308	struct ehci_pci_softc *sc = device_private(self);
309	int rv;
310
311	if (sc->sc_init_state >= EHCI_INIT_INITED) {
312		rv = ehci_detach(&sc->sc, flags);
313		if (rv)
314			return rv;
315	}
316
317	pmf_device_deregister(self);
318	ehci_shutdown(self, flags);
319
320	if (sc->sc_init_state >= EHCI_INIT_INITED) {
321		/* disable interrupts */
322		EOWRITE4(&sc->sc, EHCI_USBINTR, 0);
323		/* XXX grotty hack to flush the write */
324		(void)EOREAD4(&sc->sc, EHCI_USBINTR);
325	}
326
327	ehci_pci_release_resources(sc);
328
329#if 1
330	/* XXX created in ehci.c */
331	if (sc->sc_init_state >= EHCI_INIT_INITED) {
332		mutex_destroy(&sc->sc.sc_rhlock);
333		mutex_destroy(&sc->sc.sc_lock);
334		mutex_destroy(&sc->sc.sc_intr_lock);
335		softint_disestablish(sc->sc.sc_doorbell_si);
336		softint_disestablish(sc->sc.sc_pcd_si);
337	}
338#endif
339
340	return 0;
341}
342
343CFATTACH_DECL3_NEW(ehci_pci, sizeof(struct ehci_pci_softc),
344    ehci_pci_match, ehci_pci_attach, ehci_pci_detach, ehci_activate, NULL,
345    ehci_childdet, DVF_DETACH_SHUTDOWN);
346
347#ifdef EHCI_DEBUG
348static void
349ehci_dump_caps(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag)
350{
351	uint32_t cparams, legctlsts, addr, cap, id;
352	int maxdump = 10;
353
354	cparams = EREAD4(sc, EHCI_HCCPARAMS);
355	addr = EHCI_HCC_EECP(cparams);
356	while (addr != 0) {
357		cap = pci_conf_read(pc, tag, addr);
358		id = EHCI_CAP_GET_ID(cap);
359		switch (id) {
360		case EHCI_CAP_ID_LEGACY:
361			legctlsts = pci_conf_read(pc, tag,
362			    addr + PCI_EHCI_USBLEGCTLSTS);
363			printf("ehci_dump_caps: legsup=0x%08x "
364			       "legctlsts=0x%08x\n", cap, legctlsts);
365			break;
366		default:
367			printf("ehci_dump_caps: cap=0x%08x\n", cap);
368			break;
369		}
370		if (--maxdump < 0)
371			break;
372		addr = EHCI_CAP_GET_NEXT(cap);
373	}
374}
375#endif
376
377static void
378ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag)
379{
380	const char *devname = device_xname(sc->sc_dev);
381	uint32_t cparams, addr, cap;
382	pcireg_t legsup;
383	int maxcap = 10;
384
385	cparams = EREAD4(sc, EHCI_HCCPARAMS);
386	addr = EHCI_HCC_EECP(cparams);
387	while (addr != 0) {
388		cap = pci_conf_read(pc, tag, addr);
389		if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY)
390			goto next;
391		legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP);
392		pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP,
393		    legsup & ~EHCI_LEG_HC_OS_OWNED);
394
395next:
396		if (--maxcap < 0) {
397			aprint_normal("%s: broken extended capabilities "
398				      "ignored\n", devname);
399			return;
400		}
401		addr = EHCI_CAP_GET_NEXT(cap);
402	}
403}
404
405static void
406ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag)
407{
408	const char *devname = device_xname(sc->sc_dev);
409	uint32_t cparams, addr, cap;
410	pcireg_t legsup;
411	int maxcap = 10;
412	int ms;
413
414#ifdef EHCI_DEBUG
415	if (ehcidebug)
416		ehci_dump_caps(sc, pc, tag);
417#endif
418	cparams = EREAD4(sc, EHCI_HCCPARAMS);
419	addr = EHCI_HCC_EECP(cparams);
420	while (addr != 0) {
421		cap = pci_conf_read(pc, tag, addr);
422		if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY)
423			goto next;
424		legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP);
425		if (legsup & EHCI_LEG_HC_BIOS_OWNED) {
426			/* Ask BIOS to give up ownership */
427			pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP,
428			    legsup | EHCI_LEG_HC_OS_OWNED);
429			for (ms = 0; ms < EHCI_MAX_BIOS_WAIT; ms++) {
430				legsup = pci_conf_read(pc, tag,
431				    addr + PCI_EHCI_USBLEGSUP);
432				if (!(legsup & EHCI_LEG_HC_BIOS_OWNED))
433					break;
434				delay(10000);
435			}
436			if (ms == EHCI_MAX_BIOS_WAIT) {
437				aprint_normal("%s: BIOS refuses to give up "
438				    "ownership, using force\n", devname);
439				pci_conf_write(pc, tag,
440				    addr + PCI_EHCI_USBLEGSUP, 0);
441			} else
442				aprint_verbose("%s: BIOS has given up "
443				    "ownership\n", devname);
444		}
445
446		/* Disable SMIs */
447		pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGCTLSTS, 0);
448
449next:
450		if (--maxcap < 0) {
451			aprint_normal("%s: broken extended capabilities "
452				      "ignored\n", devname);
453			return;
454		}
455		addr = EHCI_CAP_GET_NEXT(cap);
456	}
457
458}
459
460static bool
461ehci_pci_suspend(device_t dv, const pmf_qual_t *qual)
462{
463	struct ehci_pci_softc *sc = device_private(dv);
464
465	ehci_suspend(dv, qual);
466	ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
467
468	return true;
469}
470
471static bool
472ehci_pci_resume(device_t dv, const pmf_qual_t *qual)
473{
474	struct ehci_pci_softc *sc = device_private(dv);
475
476	ehci_get_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
477	return ehci_resume(dv, qual);
478}
479
480static int
481ehci_sb700_match(const struct pci_attach_args *pa)
482{
483	if (!(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI &&
484	    PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB))
485		return 0;
486
487	switch (PCI_REVISION(pa->pa_class)) {
488	case 0x3a:
489	case 0x3b:
490		return 1;
491	}
492
493	return 0;
494}
495
496static int
497ehci_apply_amd_quirks(struct ehci_pci_softc *sc)
498{
499	pcireg_t value;
500
501	aprint_normal_dev(sc->sc.sc_dev,
502	    "applying AMD SB600/SB700 USB freeze workaround\n");
503	value = pci_conf_read(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG);
504	pci_conf_write(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG,
505	    value | EHCI_SBx00_WORKAROUND_ENABLE);
506
507	return 0;
508}
509
510static enum ehci_pci_quirk_flags
511ehci_pci_lookup_quirkdata(pci_vendor_id_t vendor, pci_product_id_t product)
512{
513	int i;
514
515	for (i = 0; i < __arraycount(ehci_pci_quirks); i++) {
516		if (vendor == ehci_pci_quirks[i].vendor &&
517		    product == ehci_pci_quirks[i].product)
518			return ehci_pci_quirks[i].quirks;
519	}
520	return 0;
521}
522
523