ehci_pci.c revision 1.74 
1/*	$NetBSD: ehci_pci.c,v 1.74 2022/03/13 11:29:21 riastradh Exp $	*/
2
3/*
4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Lennart Augustsson (lennart@augustsson.net).
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#include <sys/cdefs.h>
33__KERNEL_RCSID(0, "$NetBSD: ehci_pci.c,v 1.74 2022/03/13 11:29:21 riastradh Exp $");
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/kernel.h>
38#include <sys/device.h>
39#include <sys/proc.h>
40#include <sys/queue.h>
41
42#include <sys/bus.h>
43
44#include <dev/pci/pcidevs.h>
45#include <dev/pci/pcivar.h>
46#include <dev/pci/usb_pci.h>
47
48#include <dev/usb/usb.h>
49#include <dev/usb/usbdi.h>
50#include <dev/usb/usbdivar.h>
51#include <dev/usb/usb_mem.h>
52
53#include <dev/usb/ehcireg.h>
54#include <dev/usb/ehcivar.h>
55
56#ifdef EHCI_DEBUG
57#define DPRINTF(x)	if (ehcidebug) printf x
58extern int ehcidebug;
59#else
60#define DPRINTF(x)
61#endif
62
63enum ehci_pci_quirk_flags {
64	EHCI_PCI_QUIRK_AMD_SB600 = 0x1,	/* always need a quirk */
65	EHCI_PCI_QUIRK_AMD_SB700 = 0x2,	/* depends on the SMB revision */
66};
67
68static const struct pci_quirkdata ehci_pci_quirks[] = {
69	{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_USB_EHCI,
70	    EHCI_PCI_QUIRK_AMD_SB600 },
71	{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_USB_EHCI,
72	    EHCI_PCI_QUIRK_AMD_SB700 },
73};
74
75static void ehci_release_ownership(ehci_softc_t *, pci_chipset_tag_t, pcitag_t);
76static void ehci_get_ownership(ehci_softc_t *, pci_chipset_tag_t, pcitag_t);
77static bool ehci_pci_suspend(device_t, const pmf_qual_t *);
78static bool ehci_pci_resume(device_t, const pmf_qual_t *);
79
80struct ehci_pci_softc {
81	ehci_softc_t		sc;
82	pci_chipset_tag_t	sc_pc;
83	pcitag_t		sc_tag;
84	pci_intr_handle_t	*sc_pihp;
85	void 			*sc_ih;		/* interrupt vectoring */
86	enum {
87		EHCI_INIT_NONE,
88		EHCI_INIT_INITED
89	} sc_init_state;
90};
91
92static int ehci_sb700_match(const struct pci_attach_args *);
93static int ehci_apply_amd_quirks(struct ehci_pci_softc *);
94static enum ehci_pci_quirk_flags ehci_pci_lookup_quirkdata(pci_vendor_id_t,
95    pci_product_id_t);
96
97#define EHCI_MAX_BIOS_WAIT		100 /* ms*10 */
98#define EHCI_SBx00_WORKAROUND_REG	0x50
99#define EHCI_SBx00_WORKAROUND_ENABLE	__BIT(27)
100
101static int
102ehci_pci_match(device_t parent, cfdata_t match, void *aux)
103{
104	struct pci_attach_args *pa = (struct pci_attach_args *) aux;
105
106	if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS &&
107	    PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB &&
108	    PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_EHCI)
109		return 1;
110
111	return 0;
112}
113
114static void
115ehci_pci_attach(device_t parent, device_t self, void *aux)
116{
117	struct ehci_pci_softc *sc = device_private(self);
118	struct pci_attach_args *pa = (struct pci_attach_args *)aux;
119	pci_chipset_tag_t pc = pa->pa_pc;
120	pcitag_t tag = pa->pa_tag;
121	char intrbuf[PCI_INTRSTR_LEN];
122	char const *intrstr;
123	struct usb_pci *up;
124	int ncomp, quirk;
125	pcireg_t csr;
126
127	sc->sc_init_state = EHCI_INIT_NONE;
128	sc->sc.sc_dev = self;
129	sc->sc.sc_bus.ub_hcpriv = sc;
130
131	pci_aprint_devinfo(pa, "USB controller");
132
133	/* Check for quirks */
134	quirk = ehci_pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id),
135	    PCI_PRODUCT(pa->pa_id));
136
137	/* Map I/O registers */
138	if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0,
139	    &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) {
140		sc->sc.sc_size = 0;
141		aprint_error_dev(self, "can't map memory space\n");
142		return;
143	}
144
145	sc->sc_pc = pc;
146	sc->sc_tag = tag;
147
148	const uint32_t hccparams = EREAD4(&sc->sc, EHCI_HCCPARAMS);
149
150	if (EHCI_HCC_64BIT(hccparams)) {
151		aprint_verbose_dev(self, "64-bit DMA");
152		if (pci_dma64_available(pa)) {
153			sc->sc.sc_bus.ub_dmatag = pa->pa_dmat64;
154			aprint_verbose("\n");
155		} else {
156			aprint_verbose(" - limited\n");
157			sc->sc.sc_bus.ub_dmatag = pa->pa_dmat;
158		}
159	} else {
160		aprint_verbose_dev(self, "32-bit DMA\n");
161		sc->sc.sc_bus.ub_dmatag = pa->pa_dmat;
162	}
163
164	/* Disable interrupts, so we don't get any spurious ones. */
165	sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH);
166	DPRINTF(("%s: offs=%d\n", device_xname(self), sc->sc.sc_offs));
167	EOWRITE4(&sc->sc, EHCI_USBINTR, 0);
168
169	/* Handle quirks */
170	switch (quirk) {
171	case EHCI_PCI_QUIRK_AMD_SB600:
172		ehci_apply_amd_quirks(sc);
173		break;
174	case EHCI_PCI_QUIRK_AMD_SB700:
175		if (pci_find_device(NULL, ehci_sb700_match))
176			ehci_apply_amd_quirks(sc);
177		break;
178	}
179
180	pcireg_t intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
181	int pin = PCI_INTERRUPT_PIN(intr);
182
183	/* Enable the device. */
184	csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
185	csr |= PCI_COMMAND_MASTER_ENABLE;
186	csr &= ~(pin ? PCI_COMMAND_INTERRUPT_DISABLE : 0);
187	pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
188
189	/* Map and establish the interrupt. */
190	if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0) != 0) {
191		aprint_error_dev(self, "couldn't map interrupt\n");
192		goto fail;
193	}
194
195	/*
196	 * Allocate IRQ
197	 */
198	intrstr = pci_intr_string(pc, sc->sc_pihp[0], intrbuf, sizeof(intrbuf));
199	sc->sc_ih = pci_intr_establish_xname(pc, sc->sc_pihp[0], IPL_USB,
200	    ehci_intr, sc, device_xname(self));
201	if (sc->sc_ih == NULL) {
202		pci_intr_release(sc->sc_pc, sc->sc_pihp, 1);
203		sc->sc_pihp = NULL;
204
205		aprint_error_dev(self, "couldn't establish interrupt");
206		if (intrstr != NULL)
207			aprint_error(" at %s", intrstr);
208		aprint_error("\n");
209		goto fail;
210	}
211	aprint_normal_dev(self, "interrupting at %s\n", intrstr);
212
213	switch (pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK) {
214	case PCI_USBREV_PRE_1_0:
215	case PCI_USBREV_1_0:
216	case PCI_USBREV_1_1:
217		sc->sc.sc_bus.ub_revision = USBREV_UNKNOWN;
218		aprint_verbose_dev(self, "pre-2.0 USB rev, device ignored\n");
219		goto fail;
220	case PCI_USBREV_2_0:
221		sc->sc.sc_bus.ub_revision = USBREV_2_0;
222		break;
223	default:
224		sc->sc.sc_bus.ub_revision = USBREV_UNKNOWN;
225		break;
226	}
227
228	/* Enable workaround for dropped interrupts as required */
229	switch (PCI_VENDOR(pa->pa_id)) {
230	case PCI_VENDOR_ATI:
231	case PCI_VENDOR_VIATECH:
232		sc->sc.sc_flags |= EHCIF_DROPPED_INTR_WORKAROUND;
233		aprint_normal_dev(self, "dropped intr workaround enabled\n");
234		break;
235	default:
236		break;
237	}
238
239	/*
240	 * Find companion controllers.  According to the spec they always
241	 * have lower function numbers so they should be enumerated already.
242	 */
243	const u_int maxncomp = EHCI_HCS_N_CC(EREAD4(&sc->sc, EHCI_HCSPARAMS));
244	KASSERT(maxncomp <= EHCI_COMPANION_MAX);
245	ncomp = 0;
246	TAILQ_FOREACH(up, &ehci_pci_alldevs, next) {
247		if (up->bus == pa->pa_bus && up->device == pa->pa_device &&
248		    !up->claimed) {
249			DPRINTF(("ehci_pci_attach: companion %s\n",
250			    device_xname(up->usb)));
251			sc->sc.sc_comps[ncomp++] = up->usb;
252			up->claimed = true;
253			if (ncomp == maxncomp)
254				break;
255		}
256	}
257	sc->sc.sc_ncomp = ncomp;
258
259	ehci_get_ownership(&sc->sc, pc, tag);
260
261	int err = ehci_init(&sc->sc);
262	if (err) {
263		aprint_error_dev(self, "init failed, error=%d\n", err);
264		goto fail;
265	}
266	sc->sc_init_state = EHCI_INIT_INITED;
267
268	if (!pmf_device_register1(self, ehci_pci_suspend, ehci_pci_resume,
269	    ehci_shutdown))
270		aprint_error_dev(self, "couldn't establish power handler\n");
271
272	/* Attach usb device. */
273	sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint,
274	    CFARGS_NONE);
275	return;
276
277fail:
278	if (sc->sc_ih) {
279		pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
280		sc->sc_ih = NULL;
281	}
282	if (sc->sc.sc_size) {
283		ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
284		bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
285		sc->sc.sc_size = 0;
286	}
287}
288
289static int
290ehci_pci_detach(device_t self, int flags)
291{
292	struct ehci_pci_softc *sc = device_private(self);
293	int rv;
294
295	if (sc->sc_init_state >= EHCI_INIT_INITED) {
296		rv = ehci_detach(&sc->sc, flags);
297		if (rv)
298			return rv;
299	}
300
301	pmf_device_deregister(self);
302	ehci_shutdown(self, flags);
303
304	/* disable interrupts */
305	EOWRITE4(&sc->sc, EHCI_USBINTR, 0);
306	/* XXX grotty hack to flush the write */
307	(void)EOREAD4(&sc->sc, EHCI_USBINTR);
308
309	if (sc->sc_ih != NULL) {
310		pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
311		sc->sc_ih = NULL;
312	}
313
314	if (sc->sc_pihp != NULL) {
315		pci_intr_release(sc->sc_pc, sc->sc_pihp, 1);
316		sc->sc_pihp = NULL;
317	}
318
319	if (sc->sc.sc_size) {
320		ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
321		bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
322		sc->sc.sc_size = 0;
323	}
324
325#if 1
326	/* XXX created in ehci.c */
327	if (sc->sc_init_state >= EHCI_INIT_INITED) {
328		mutex_destroy(&sc->sc.sc_rhlock);
329		mutex_destroy(&sc->sc.sc_lock);
330		mutex_destroy(&sc->sc.sc_intr_lock);
331		softint_disestablish(sc->sc.sc_doorbell_si);
332		softint_disestablish(sc->sc.sc_pcd_si);
333	}
334#endif
335
336	return 0;
337}
338
339CFATTACH_DECL3_NEW(ehci_pci, sizeof(struct ehci_pci_softc),
340    ehci_pci_match, ehci_pci_attach, ehci_pci_detach, ehci_activate, NULL,
341    ehci_childdet, DVF_DETACH_SHUTDOWN);
342
343#ifdef EHCI_DEBUG
344static void
345ehci_dump_caps(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag)
346{
347	uint32_t cparams, legctlsts, addr, cap, id;
348	int maxdump = 10;
349
350	cparams = EREAD4(sc, EHCI_HCCPARAMS);
351	addr = EHCI_HCC_EECP(cparams);
352	while (addr != 0) {
353		cap = pci_conf_read(pc, tag, addr);
354		id = EHCI_CAP_GET_ID(cap);
355		switch (id) {
356		case EHCI_CAP_ID_LEGACY:
357			legctlsts = pci_conf_read(pc, tag,
358			    addr + PCI_EHCI_USBLEGCTLSTS);
359			printf("ehci_dump_caps: legsup=0x%08x "
360			       "legctlsts=0x%08x\n", cap, legctlsts);
361			break;
362		default:
363			printf("ehci_dump_caps: cap=0x%08x\n", cap);
364			break;
365		}
366		if (--maxdump < 0)
367			break;
368		addr = EHCI_CAP_GET_NEXT(cap);
369	}
370}
371#endif
372
373static void
374ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag)
375{
376	const char *devname = device_xname(sc->sc_dev);
377	uint32_t cparams, addr, cap;
378	pcireg_t legsup;
379	int maxcap = 10;
380
381	cparams = EREAD4(sc, EHCI_HCCPARAMS);
382	addr = EHCI_HCC_EECP(cparams);
383	while (addr != 0) {
384		cap = pci_conf_read(pc, tag, addr);
385		if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY)
386			goto next;
387		legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP);
388		pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP,
389		    legsup & ~EHCI_LEG_HC_OS_OWNED);
390
391next:
392		if (--maxcap < 0) {
393			aprint_normal("%s: broken extended capabilities "
394				      "ignored\n", devname);
395			return;
396		}
397		addr = EHCI_CAP_GET_NEXT(cap);
398	}
399}
400
401static void
402ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag)
403{
404	const char *devname = device_xname(sc->sc_dev);
405	uint32_t cparams, addr, cap;
406	pcireg_t legsup;
407	int maxcap = 10;
408	int ms;
409
410#ifdef EHCI_DEBUG
411	if (ehcidebug)
412		ehci_dump_caps(sc, pc, tag);
413#endif
414	cparams = EREAD4(sc, EHCI_HCCPARAMS);
415	addr = EHCI_HCC_EECP(cparams);
416	while (addr != 0) {
417		cap = pci_conf_read(pc, tag, addr);
418		if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY)
419			goto next;
420		legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP);
421		if (legsup & EHCI_LEG_HC_BIOS_OWNED) {
422			/* Ask BIOS to give up ownership */
423			pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP,
424			    legsup | EHCI_LEG_HC_OS_OWNED);
425			for (ms = 0; ms < EHCI_MAX_BIOS_WAIT; ms++) {
426				legsup = pci_conf_read(pc, tag,
427				    addr + PCI_EHCI_USBLEGSUP);
428				if (!(legsup & EHCI_LEG_HC_BIOS_OWNED))
429					break;
430				delay(10000);
431			}
432			if (ms == EHCI_MAX_BIOS_WAIT) {
433				aprint_normal("%s: BIOS refuses to give up "
434				    "ownership, using force\n", devname);
435				pci_conf_write(pc, tag,
436				    addr + PCI_EHCI_USBLEGSUP, 0);
437			} else
438				aprint_verbose("%s: BIOS has given up "
439				    "ownership\n", devname);
440		}
441
442		/* Disable SMIs */
443		pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGCTLSTS, 0);
444
445next:
446		if (--maxcap < 0) {
447			aprint_normal("%s: broken extended capabilities "
448				      "ignored\n", devname);
449			return;
450		}
451		addr = EHCI_CAP_GET_NEXT(cap);
452	}
453
454}
455
456static bool
457ehci_pci_suspend(device_t dv, const pmf_qual_t *qual)
458{
459	struct ehci_pci_softc *sc = device_private(dv);
460
461	ehci_suspend(dv, qual);
462	ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
463
464	return true;
465}
466
467static bool
468ehci_pci_resume(device_t dv, const pmf_qual_t *qual)
469{
470	struct ehci_pci_softc *sc = device_private(dv);
471
472	ehci_get_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
473	return ehci_resume(dv, qual);
474}
475
476static int
477ehci_sb700_match(const struct pci_attach_args *pa)
478{
479	if (!(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI &&
480	    PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB))
481		return 0;
482
483	switch (PCI_REVISION(pa->pa_class)) {
484	case 0x3a:
485	case 0x3b:
486		return 1;
487	}
488
489	return 0;
490}
491
492static int
493ehci_apply_amd_quirks(struct ehci_pci_softc *sc)
494{
495	pcireg_t value;
496
497	aprint_normal_dev(sc->sc.sc_dev,
498	    "applying AMD SB600/SB700 USB freeze workaround\n");
499	value = pci_conf_read(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG);
500	pci_conf_write(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG,
501	    value | EHCI_SBx00_WORKAROUND_ENABLE);
502
503	return 0;
504}
505
506static enum ehci_pci_quirk_flags
507ehci_pci_lookup_quirkdata(pci_vendor_id_t vendor, pci_product_id_t product)
508{
509	int i;
510
511	for (i = 0; i < __arraycount(ehci_pci_quirks); i++) {
512		if (vendor == ehci_pci_quirks[i].vendor &&
513		    product == ehci_pci_quirks[i].product)
514			return ehci_pci_quirks[i].quirks;
515	}
516	return 0;
517}
518
519