ehci_pci.c revision 1.69 
1/*	$NetBSD: ehci_pci.c,v 1.69 2019/06/13 17:20:25 maxv Exp $	*/
2
3/*
4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Lennart Augustsson (lennart@augustsson.net).
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#include <sys/cdefs.h>
33__KERNEL_RCSID(0, "$NetBSD: ehci_pci.c,v 1.69 2019/06/13 17:20:25 maxv Exp $");
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/kernel.h>
38#include <sys/device.h>
39#include <sys/proc.h>
40#include <sys/queue.h>
41
42#include <sys/bus.h>
43
44#include <dev/pci/pcidevs.h>
45#include <dev/pci/pcivar.h>
46#include <dev/pci/usb_pci.h>
47
48#include <dev/usb/usb.h>
49#include <dev/usb/usbdi.h>
50#include <dev/usb/usbdivar.h>
51#include <dev/usb/usb_mem.h>
52
53#include <dev/usb/ehcireg.h>
54#include <dev/usb/ehcivar.h>
55
56#ifdef EHCI_DEBUG
57#define DPRINTF(x)	if (ehcidebug) printf x
58extern int ehcidebug;
59#else
60#define DPRINTF(x)
61#endif
62
63enum ehci_pci_quirk_flags {
64	EHCI_PCI_QUIRK_AMD_SB600 = 0x1,	/* always need a quirk */
65	EHCI_PCI_QUIRK_AMD_SB700 = 0x2,	/* depends on the SMB revision */
66};
67
68static const struct pci_quirkdata ehci_pci_quirks[] = {
69	{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_USB_EHCI,
70	    EHCI_PCI_QUIRK_AMD_SB600 },
71	{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_USB_EHCI,
72	    EHCI_PCI_QUIRK_AMD_SB700 },
73};
74
75static void ehci_release_ownership(ehci_softc_t *, pci_chipset_tag_t, pcitag_t);
76static void ehci_get_ownership(ehci_softc_t *, pci_chipset_tag_t, pcitag_t);
77static bool ehci_pci_suspend(device_t, const pmf_qual_t *);
78static bool ehci_pci_resume(device_t, const pmf_qual_t *);
79
80struct ehci_pci_softc {
81	ehci_softc_t		sc;
82	pci_chipset_tag_t	sc_pc;
83	pcitag_t		sc_tag;
84	pci_intr_handle_t	*sc_pihp;
85	void 			*sc_ih;		/* interrupt vectoring */
86};
87
88static int ehci_sb700_match(const struct pci_attach_args *);
89static int ehci_apply_amd_quirks(struct ehci_pci_softc *);
90static enum ehci_pci_quirk_flags ehci_pci_lookup_quirkdata(pci_vendor_id_t,
91    pci_product_id_t);
92
93#define EHCI_MAX_BIOS_WAIT		100 /* ms*10 */
94#define EHCI_SBx00_WORKAROUND_REG	0x50
95#define EHCI_SBx00_WORKAROUND_ENABLE	__BIT(27)
96
97static int
98ehci_pci_match(device_t parent, cfdata_t match, void *aux)
99{
100	struct pci_attach_args *pa = (struct pci_attach_args *) aux;
101
102	if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS &&
103	    PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB &&
104	    PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_EHCI)
105		return 1;
106
107	return 0;
108}
109
110static void
111ehci_pci_attach(device_t parent, device_t self, void *aux)
112{
113	struct ehci_pci_softc *sc = device_private(self);
114	struct pci_attach_args *pa = (struct pci_attach_args *)aux;
115	pci_chipset_tag_t pc = pa->pa_pc;
116	pcitag_t tag = pa->pa_tag;
117	char intrbuf[PCI_INTRSTR_LEN];
118	char const *intrstr;
119	struct usb_pci *up;
120	int ncomp, quirk;
121	pcireg_t csr;
122
123	sc->sc.sc_dev = self;
124	sc->sc.sc_bus.ub_hcpriv = sc;
125
126	pci_aprint_devinfo(pa, "USB controller");
127
128	/* Check for quirks */
129	quirk = ehci_pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id),
130	    PCI_PRODUCT(pa->pa_id));
131
132	/* Map I/O registers */
133	if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0,
134	    &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) {
135		sc->sc.sc_size = 0;
136		aprint_error_dev(self, "can't map memory space\n");
137		return;
138	}
139
140	sc->sc_pc = pc;
141	sc->sc_tag = tag;
142	sc->sc.sc_bus.ub_dmatag = pa->pa_dmat;
143
144	/* Disable interrupts, so we don't get any spurious ones. */
145	sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH);
146	DPRINTF(("%s: offs=%d\n", device_xname(self), sc->sc.sc_offs));
147	EOWRITE4(&sc->sc, EHCI_USBINTR, 0);
148
149	/* Handle quirks */
150	switch (quirk) {
151	case EHCI_PCI_QUIRK_AMD_SB600:
152		ehci_apply_amd_quirks(sc);
153		break;
154	case EHCI_PCI_QUIRK_AMD_SB700:
155		if (pci_find_device(NULL, ehci_sb700_match))
156			ehci_apply_amd_quirks(sc);
157		break;
158	}
159
160	pcireg_t intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
161	int pin = PCI_INTERRUPT_PIN(intr);
162
163	/* Enable the device. */
164	csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
165	csr |= PCI_COMMAND_MASTER_ENABLE;
166	csr &= ~(pin ? PCI_COMMAND_INTERRUPT_DISABLE : 0);
167	pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
168
169	/* Map and establish the interrupt. */
170	if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0) != 0) {
171		aprint_error_dev(self, "couldn't map interrupt\n");
172		goto fail;
173	}
174
175	/*
176	 * Allocate IRQ
177	 */
178	intrstr = pci_intr_string(pc, sc->sc_pihp[0], intrbuf, sizeof(intrbuf));
179	sc->sc_ih = pci_intr_establish_xname(pc, sc->sc_pihp[0], IPL_USB,
180	    ehci_intr, sc, device_xname(self));
181	if (sc->sc_ih == NULL) {
182		pci_intr_release(sc->sc_pc, sc->sc_pihp, 1);
183		sc->sc_pihp = NULL;
184
185		aprint_error_dev(self, "couldn't establish interrupt");
186		if (intrstr != NULL)
187			aprint_error(" at %s", intrstr);
188		aprint_error("\n");
189		goto fail;
190	}
191	aprint_normal_dev(self, "interrupting at %s\n", intrstr);
192
193	switch (pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK) {
194	case PCI_USBREV_PRE_1_0:
195	case PCI_USBREV_1_0:
196	case PCI_USBREV_1_1:
197		sc->sc.sc_bus.ub_revision = USBREV_UNKNOWN;
198		aprint_verbose_dev(self, "pre-2.0 USB rev, device ignored\n");
199		goto fail;
200	case PCI_USBREV_2_0:
201		sc->sc.sc_bus.ub_revision = USBREV_2_0;
202		break;
203	default:
204		sc->sc.sc_bus.ub_revision = USBREV_UNKNOWN;
205		break;
206	}
207
208	/* Enable workaround for dropped interrupts as required */
209	switch (PCI_VENDOR(pa->pa_id)) {
210	case PCI_VENDOR_ATI:
211	case PCI_VENDOR_VIATECH:
212		sc->sc.sc_flags |= EHCIF_DROPPED_INTR_WORKAROUND;
213		aprint_normal_dev(self, "dropped intr workaround enabled\n");
214		break;
215	default:
216		break;
217	}
218
219	/*
220	 * Find companion controllers.  According to the spec they always
221	 * have lower function numbers so they should be enumerated already.
222	 */
223	const u_int maxncomp = EHCI_HCS_N_CC(EREAD4(&sc->sc, EHCI_HCSPARAMS));
224	KASSERT(maxncomp <= EHCI_COMPANION_MAX);
225	ncomp = 0;
226	TAILQ_FOREACH(up, &ehci_pci_alldevs, next) {
227		if (up->bus == pa->pa_bus && up->device == pa->pa_device &&
228		    !up->claimed) {
229			DPRINTF(("ehci_pci_attach: companion %s\n",
230			    device_xname(up->usb)));
231			sc->sc.sc_comps[ncomp++] = up->usb;
232			up->claimed = true;
233			if (ncomp == maxncomp)
234				break;
235		}
236	}
237	sc->sc.sc_ncomp = ncomp;
238
239	ehci_get_ownership(&sc->sc, pc, tag);
240
241	int err = ehci_init(&sc->sc);
242	if (err) {
243		aprint_error_dev(self, "init failed, error=%d\n", err);
244		goto fail;
245	}
246
247	if (!pmf_device_register1(self, ehci_pci_suspend, ehci_pci_resume,
248	    ehci_shutdown))
249		aprint_error_dev(self, "couldn't establish power handler\n");
250
251	/* Attach usb device. */
252	sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint);
253	return;
254
255fail:
256	if (sc->sc_ih) {
257		pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
258		sc->sc_ih = NULL;
259	}
260	if (sc->sc.sc_size) {
261		ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
262		bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
263		sc->sc.sc_size = 0;
264	}
265}
266
267static int
268ehci_pci_detach(device_t self, int flags)
269{
270	struct ehci_pci_softc *sc = device_private(self);
271	int rv;
272
273	rv = ehci_detach(&sc->sc, flags);
274	if (rv)
275		return rv;
276
277	pmf_device_deregister(self);
278	ehci_shutdown(self, flags);
279
280	/* disable interrupts */
281	EOWRITE4(&sc->sc, EHCI_USBINTR, 0);
282	/* XXX grotty hack to flush the write */
283	(void)EOREAD4(&sc->sc, EHCI_USBINTR);
284
285	if (sc->sc_ih != NULL) {
286		pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
287		sc->sc_ih = NULL;
288	}
289
290	if (sc->sc_pihp != NULL) {
291		pci_intr_release(sc->sc_pc, sc->sc_pihp, 1);
292		sc->sc_pihp = NULL;
293	}
294
295	if (sc->sc.sc_size) {
296		ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
297		bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
298		sc->sc.sc_size = 0;
299	}
300
301#if 1
302	/* XXX created in ehci.c */
303	mutex_destroy(&sc->sc.sc_lock);
304	mutex_destroy(&sc->sc.sc_intr_lock);
305	softint_disestablish(sc->sc.sc_doorbell_si);
306	softint_disestablish(sc->sc.sc_pcd_si);
307#endif
308
309	return 0;
310}
311
312CFATTACH_DECL3_NEW(ehci_pci, sizeof(struct ehci_pci_softc),
313    ehci_pci_match, ehci_pci_attach, ehci_pci_detach, ehci_activate, NULL,
314    ehci_childdet, DVF_DETACH_SHUTDOWN);
315
316#ifdef EHCI_DEBUG
317static void
318ehci_dump_caps(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag)
319{
320	uint32_t cparams, legctlsts, addr, cap, id;
321	int maxdump = 10;
322
323	cparams = EREAD4(sc, EHCI_HCCPARAMS);
324	addr = EHCI_HCC_EECP(cparams);
325	while (addr != 0) {
326		cap = pci_conf_read(pc, tag, addr);
327		id = EHCI_CAP_GET_ID(cap);
328		switch (id) {
329		case EHCI_CAP_ID_LEGACY:
330			legctlsts = pci_conf_read(pc, tag,
331			    addr + PCI_EHCI_USBLEGCTLSTS);
332			printf("ehci_dump_caps: legsup=0x%08x "
333			       "legctlsts=0x%08x\n", cap, legctlsts);
334			break;
335		default:
336			printf("ehci_dump_caps: cap=0x%08x\n", cap);
337			break;
338		}
339		if (--maxdump < 0)
340			break;
341		addr = EHCI_CAP_GET_NEXT(cap);
342	}
343}
344#endif
345
346static void
347ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag)
348{
349	const char *devname = device_xname(sc->sc_dev);
350	uint32_t cparams, addr, cap;
351	pcireg_t legsup;
352	int maxcap = 10;
353
354	cparams = EREAD4(sc, EHCI_HCCPARAMS);
355	addr = EHCI_HCC_EECP(cparams);
356	while (addr != 0) {
357		cap = pci_conf_read(pc, tag, addr);
358		if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY)
359			goto next;
360		legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP);
361		pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP,
362		    legsup & ~EHCI_LEG_HC_OS_OWNED);
363
364next:
365		if (--maxcap < 0) {
366			aprint_normal("%s: broken extended capabilities "
367				      "ignored\n", devname);
368			return;
369		}
370		addr = EHCI_CAP_GET_NEXT(cap);
371	}
372}
373
374static void
375ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag)
376{
377	const char *devname = device_xname(sc->sc_dev);
378	uint32_t cparams, addr, cap;
379	pcireg_t legsup;
380	int maxcap = 10;
381	int ms;
382
383#ifdef EHCI_DEBUG
384	if (ehcidebug)
385		ehci_dump_caps(sc, pc, tag);
386#endif
387	cparams = EREAD4(sc, EHCI_HCCPARAMS);
388	addr = EHCI_HCC_EECP(cparams);
389	while (addr != 0) {
390		cap = pci_conf_read(pc, tag, addr);
391		if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY)
392			goto next;
393		legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP);
394		if (legsup & EHCI_LEG_HC_BIOS_OWNED) {
395			/* Ask BIOS to give up ownership */
396			pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP,
397			    legsup | EHCI_LEG_HC_OS_OWNED);
398			for (ms = 0; ms < EHCI_MAX_BIOS_WAIT; ms++) {
399				legsup = pci_conf_read(pc, tag,
400				    addr + PCI_EHCI_USBLEGSUP);
401				if (!(legsup & EHCI_LEG_HC_BIOS_OWNED))
402					break;
403				delay(10000);
404			}
405			if (ms == EHCI_MAX_BIOS_WAIT) {
406				aprint_normal("%s: BIOS refuses to give up "
407				    "ownership, using force\n", devname);
408				pci_conf_write(pc, tag,
409				    addr + PCI_EHCI_USBLEGSUP, 0);
410			} else
411				aprint_verbose("%s: BIOS has given up "
412				    "ownership\n", devname);
413		}
414
415		/* Disable SMIs */
416		pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGCTLSTS, 0);
417
418next:
419		if (--maxcap < 0) {
420			aprint_normal("%s: broken extended capabilities "
421				      "ignored\n", devname);
422			return;
423		}
424		addr = EHCI_CAP_GET_NEXT(cap);
425	}
426
427}
428
429static bool
430ehci_pci_suspend(device_t dv, const pmf_qual_t *qual)
431{
432	struct ehci_pci_softc *sc = device_private(dv);
433
434	ehci_suspend(dv, qual);
435	ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
436
437	return true;
438}
439
440static bool
441ehci_pci_resume(device_t dv, const pmf_qual_t *qual)
442{
443	struct ehci_pci_softc *sc = device_private(dv);
444
445	ehci_get_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
446	return ehci_resume(dv, qual);
447}
448
449static int
450ehci_sb700_match(const struct pci_attach_args *pa)
451{
452	if (!(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI &&
453	    PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB))
454		return 0;
455
456	switch (PCI_REVISION(pa->pa_class)) {
457	case 0x3a:
458	case 0x3b:
459		return 1;
460	}
461
462	return 0;
463}
464
465static int
466ehci_apply_amd_quirks(struct ehci_pci_softc *sc)
467{
468	pcireg_t value;
469
470	aprint_normal_dev(sc->sc.sc_dev,
471	    "applying AMD SB600/SB700 USB freeze workaround\n");
472	value = pci_conf_read(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG);
473	pci_conf_write(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG,
474	    value | EHCI_SBx00_WORKAROUND_ENABLE);
475
476	return 0;
477}
478
479static enum ehci_pci_quirk_flags
480ehci_pci_lookup_quirkdata(pci_vendor_id_t vendor, pci_product_id_t product)
481{
482	int i;
483
484	for (i = 0; i < __arraycount(ehci_pci_quirks); i++) {
485		if (vendor == ehci_pci_quirks[i].vendor &&
486		    product == ehci_pci_quirks[i].product)
487			return ehci_pci_quirks[i].quirks;
488	}
489	return 0;
490}
491
492