1/* $NetBSD: cmpci.c,v 1.61 2024/01/08 18:37:24 chs Exp $ */ 2 3/* 4 * Copyright (c) 2000, 2001, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Takuya SHIOZAKI <tshiozak@NetBSD.org> . 9 * 10 * This code is derived from software contributed to The NetBSD Foundation 11 * by ITOH Yasufumi. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 */ 35 36/* 37 * C-Media CMI8x38 Audio Chip Support. 38 * 39 * TODO: 40 * - 4ch / 6ch support. 41 * - Joystick support. 42 * 43 */ 44 45#include <sys/cdefs.h> 46__KERNEL_RCSID(0, "$NetBSD: cmpci.c,v 1.61 2024/01/08 18:37:24 chs Exp $"); 47 48#if defined(AUDIO_DEBUG) || defined(DEBUG) 49#define DPRINTF(x) if (cmpcidebug) printf x 50int cmpcidebug = 0; 51#else 52#define DPRINTF(x) 53#endif 54 55#include "mpu.h" 56 57#include <sys/param.h> 58#include <sys/systm.h> 59#include <sys/kernel.h> 60#include <sys/kmem.h> 61#include <sys/device.h> 62#include <sys/proc.h> 63 64#include <dev/pci/pcidevs.h> 65#include <dev/pci/pcivar.h> 66 67#include <sys/audioio.h> 68#include <dev/audio/audio_if.h> 69#include <dev/midi_if.h> 70 71#include <dev/pci/cmpcireg.h> 72#include <dev/pci/cmpcivar.h> 73 74#include <dev/ic/mpuvar.h> 75#include <sys/bus.h> 76#include <sys/intr.h> 77 78/* 79 * Low-level HW interface 80 */ 81static inline uint8_t cmpci_mixerreg_read(struct cmpci_softc *, uint8_t); 82static inline void cmpci_mixerreg_write(struct cmpci_softc *, 83 uint8_t, uint8_t); 84static inline void cmpci_reg_partial_write_1(struct cmpci_softc *, int, int, 85 unsigned, unsigned); 86static inline void cmpci_reg_partial_write_4(struct cmpci_softc *, int, int, 87 uint32_t, uint32_t); 88static inline void cmpci_reg_set_1(struct cmpci_softc *, int, uint8_t); 89static inline void cmpci_reg_clear_1(struct cmpci_softc *, int, uint8_t); 90static inline void cmpci_reg_set_4(struct cmpci_softc *, int, uint32_t); 91static inline void cmpci_reg_clear_4(struct cmpci_softc *, int, uint32_t); 92static inline void cmpci_reg_set_reg_misc(struct cmpci_softc *, uint32_t); 93static inline void cmpci_reg_clear_reg_misc(struct cmpci_softc *, uint32_t); 94static int cmpci_rate_to_index(int); 95static inline int cmpci_index_to_divider(int); 96 97static int cmpci_adjust(int, int); 98static void cmpci_set_mixer_gain(struct cmpci_softc *, int); 99static void cmpci_set_out_ports(struct cmpci_softc *); 100static int cmpci_set_in_ports(struct cmpci_softc *); 101 102 103/* 104 * autoconf interface 105 */ 106static int cmpci_match(device_t, cfdata_t, void *); 107static void cmpci_attach(device_t, device_t, void *); 108 109CFATTACH_DECL_NEW(cmpci, sizeof (struct cmpci_softc), 110 cmpci_match, cmpci_attach, NULL, NULL); 111 112/* interrupt */ 113static int cmpci_intr(void *); 114 115 116/* 117 * DMA stuffs 118 */ 119static int cmpci_alloc_dmamem(struct cmpci_softc *, size_t, void **); 120static int cmpci_free_dmamem(struct cmpci_softc *, void *, size_t); 121static struct cmpci_dmanode * cmpci_find_dmamem(struct cmpci_softc *, 122 void *); 123 124 125/* 126 * interface to machine independent layer 127 */ 128static int cmpci_query_format(void *, audio_format_query_t *); 129static int cmpci_set_format(void *, int, 130 const audio_params_t *, const audio_params_t *, 131 audio_filter_reg_t *, audio_filter_reg_t *); 132static int cmpci_halt_output(void *); 133static int cmpci_halt_input(void *); 134static int cmpci_getdev(void *, struct audio_device *); 135static int cmpci_set_port(void *, mixer_ctrl_t *); 136static int cmpci_get_port(void *, mixer_ctrl_t *); 137static int cmpci_query_devinfo(void *, mixer_devinfo_t *); 138static void *cmpci_allocm(void *, int, size_t); 139static void cmpci_freem(void *, void *, size_t); 140static size_t cmpci_round_buffersize(void *, int, size_t); 141static int cmpci_get_props(void *); 142static int cmpci_trigger_output(void *, void *, void *, int, 143 void (*)(void *), void *, const audio_params_t *); 144static int cmpci_trigger_input(void *, void *, void *, int, 145 void (*)(void *), void *, const audio_params_t *); 146static void cmpci_get_locks(void *, kmutex_t **, kmutex_t **); 147 148static const struct audio_hw_if cmpci_hw_if = { 149 .query_format = cmpci_query_format, 150 .set_format = cmpci_set_format, 151 .halt_output = cmpci_halt_output, 152 .halt_input = cmpci_halt_input, 153 .getdev = cmpci_getdev, 154 .set_port = cmpci_set_port, 155 .get_port = cmpci_get_port, 156 .query_devinfo = cmpci_query_devinfo, 157 .allocm = cmpci_allocm, 158 .freem = cmpci_freem, 159 .round_buffersize = cmpci_round_buffersize, 160 .get_props = cmpci_get_props, 161 .trigger_output = cmpci_trigger_output, 162 .trigger_input = cmpci_trigger_input, 163 .get_locks = cmpci_get_locks, 164}; 165 166static const struct audio_format cmpci_formats[] = { 167 { 168 .mode = AUMODE_PLAY | AUMODE_RECORD, 169 .encoding = AUDIO_ENCODING_SLINEAR_LE, 170 .validbits = 16, 171 .precision = 16, 172 .channels = 2, 173 .channel_mask = AUFMT_STEREO, 174 .frequency_type = 8, 175 .frequency = 176 { 5512, 8000, 11025, 16000, 22050, 32000, 44100, 48000 }, 177 }, 178}; 179#define CMPCI_NFORMATS __arraycount(cmpci_formats) 180 181 182/* 183 * Low-level HW interface 184 */ 185 186/* mixer register read/write */ 187static inline uint8_t 188cmpci_mixerreg_read(struct cmpci_softc *sc, uint8_t no) 189{ 190 uint8_t ret; 191 192 bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBADDR, no); 193 delay(10); 194 ret = bus_space_read_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBDATA); 195 delay(10); 196 return ret; 197} 198 199static inline void 200cmpci_mixerreg_write(struct cmpci_softc *sc, uint8_t no, uint8_t val) 201{ 202 203 bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBADDR, no); 204 delay(10); 205 bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_SBDATA, val); 206 delay(10); 207} 208 209 210/* register partial write */ 211static inline void 212cmpci_reg_partial_write_1(struct cmpci_softc *sc, int no, int shift, 213 unsigned mask, unsigned val) 214{ 215 216 bus_space_write_1(sc->sc_iot, sc->sc_ioh, no, 217 (val<<shift) | 218 (bus_space_read_1(sc->sc_iot, sc->sc_ioh, no) & ~(mask<<shift))); 219 delay(10); 220} 221 222static inline void 223cmpci_reg_partial_write_4(struct cmpci_softc *sc, int no, int shift, 224 uint32_t mask, uint32_t val) 225{ 226 227 bus_space_write_4(sc->sc_iot, sc->sc_ioh, no, 228 (val<<shift) | 229 (bus_space_read_4(sc->sc_iot, sc->sc_ioh, no) & ~(mask<<shift))); 230 delay(10); 231} 232 233/* register set/clear bit */ 234static inline void 235cmpci_reg_set_1(struct cmpci_softc *sc, int no, uint8_t mask) 236{ 237 238 bus_space_write_1(sc->sc_iot, sc->sc_ioh, no, 239 (bus_space_read_1(sc->sc_iot, sc->sc_ioh, no) | mask)); 240 delay(10); 241} 242 243static inline void 244cmpci_reg_clear_1(struct cmpci_softc *sc, int no, uint8_t mask) 245{ 246 247 bus_space_write_1(sc->sc_iot, sc->sc_ioh, no, 248 (bus_space_read_1(sc->sc_iot, sc->sc_ioh, no) & ~mask)); 249 delay(10); 250} 251 252static inline void 253cmpci_reg_set_4(struct cmpci_softc *sc, int no, uint32_t mask) 254{ 255 256 /* use cmpci_reg_set_reg_misc() for CMPCI_REG_MISC */ 257 KDASSERT(no != CMPCI_REG_MISC); 258 259 bus_space_write_4(sc->sc_iot, sc->sc_ioh, no, 260 (bus_space_read_4(sc->sc_iot, sc->sc_ioh, no) | mask)); 261 delay(10); 262} 263 264static inline void 265cmpci_reg_clear_4(struct cmpci_softc *sc, int no, uint32_t mask) 266{ 267 268 /* use cmpci_reg_clear_reg_misc() for CMPCI_REG_MISC */ 269 KDASSERT(no != CMPCI_REG_MISC); 270 271 bus_space_write_4(sc->sc_iot, sc->sc_ioh, no, 272 (bus_space_read_4(sc->sc_iot, sc->sc_ioh, no) & ~mask)); 273 delay(10); 274} 275 276/* 277 * The CMPCI_REG_MISC register needs special handling, since one of 278 * its bits has different read/write values. 279 */ 280static inline void 281cmpci_reg_set_reg_misc(struct cmpci_softc *sc, uint32_t mask) 282{ 283 284 sc->sc_reg_misc |= mask; 285 bus_space_write_4(sc->sc_iot, sc->sc_ioh, CMPCI_REG_MISC, 286 sc->sc_reg_misc); 287 delay(10); 288} 289 290static inline void 291cmpci_reg_clear_reg_misc(struct cmpci_softc *sc, uint32_t mask) 292{ 293 294 sc->sc_reg_misc &= ~mask; 295 bus_space_write_4(sc->sc_iot, sc->sc_ioh, CMPCI_REG_MISC, 296 sc->sc_reg_misc); 297 delay(10); 298} 299 300/* rate */ 301static const struct { 302 int rate; 303 int divider; 304} cmpci_rate_table[CMPCI_REG_NUMRATE] = { 305#define _RATE(n) { n, CMPCI_REG_RATE_ ## n } 306 _RATE(5512), 307 _RATE(8000), 308 _RATE(11025), 309 _RATE(16000), 310 _RATE(22050), 311 _RATE(32000), 312 _RATE(44100), 313 _RATE(48000) 314#undef _RATE 315}; 316 317static int 318cmpci_rate_to_index(int rate) 319{ 320 int i; 321 322 for (i = 0; i < CMPCI_REG_NUMRATE - 1; i++) 323 if (rate == cmpci_rate_table[i].rate) 324 return i; 325 return i; /* 48000 */ 326} 327 328static inline int 329cmpci_index_to_divider(int index) 330{ 331 332 return cmpci_rate_table[index].divider; 333} 334 335/* 336 * interface to configure the device. 337 */ 338static int 339cmpci_match(device_t parent, cfdata_t match, void *aux) 340{ 341 struct pci_attach_args *pa; 342 343 pa = (struct pci_attach_args *)aux; 344 if ( PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMEDIA && 345 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8338A || 346 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8338B || 347 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8738 || 348 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMEDIA_CMI8738B) ) 349 return 1; 350 351 return 0; 352} 353 354static void 355cmpci_attach(device_t parent, device_t self, void *aux) 356{ 357 struct cmpci_softc *sc; 358 struct pci_attach_args *pa; 359 struct audio_attach_args aa; 360 pci_intr_handle_t ih; 361 char const *strintr; 362 int i, v; 363 char intrbuf[PCI_INTRSTR_LEN]; 364 365 sc = device_private(self); 366 sc->sc_dev = self; 367 pa = (struct pci_attach_args *)aux; 368 369 sc->sc_id = pa->pa_id; 370 sc->sc_class = pa->pa_class; 371 pci_aprint_devinfo(pa, "Audio controller"); 372 switch (PCI_PRODUCT(sc->sc_id)) { 373 case PCI_PRODUCT_CMEDIA_CMI8338A: 374 /*FALLTHROUGH*/ 375 case PCI_PRODUCT_CMEDIA_CMI8338B: 376 sc->sc_capable = CMPCI_CAP_CMI8338; 377 break; 378 case PCI_PRODUCT_CMEDIA_CMI8738: 379 /*FALLTHROUGH*/ 380 case PCI_PRODUCT_CMEDIA_CMI8738B: 381 sc->sc_capable = CMPCI_CAP_CMI8738; 382 break; 383 } 384 385 /* map I/O space */ 386 if (pci_mapreg_map(pa, CMPCI_PCI_IOBASEREG, PCI_MAPREG_TYPE_IO, 0, 387 &sc->sc_iot, &sc->sc_ioh, NULL, NULL)) { 388 aprint_error_dev(sc->sc_dev, "failed to map I/O space\n"); 389 return; 390 } 391 392 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 393 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); 394 395 /* interrupt */ 396 if (pci_intr_map(pa, &ih)) { 397 aprint_error_dev(sc->sc_dev, "failed to map interrupt\n"); 398 return; 399 } 400 strintr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); 401 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih, IPL_AUDIO, 402 cmpci_intr, sc, device_xname(self)); 403 if (sc->sc_ih == NULL) { 404 aprint_error_dev(sc->sc_dev, "failed to establish interrupt"); 405 if (strintr != NULL) 406 aprint_error(" at %s", strintr); 407 aprint_error("\n"); 408 mutex_destroy(&sc->sc_lock); 409 mutex_destroy(&sc->sc_intr_lock); 410 return; 411 } 412 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", strintr); 413 414 sc->sc_dmat = pa->pa_dmat; 415 416 audio_attach_mi(&cmpci_hw_if, sc, sc->sc_dev); 417 418 /* attach OPL device */ 419 aa.type = AUDIODEV_TYPE_OPL; 420 aa.hwif = NULL; 421 aa.hdl = NULL; 422 (void)config_found(sc->sc_dev, &aa, audioprint, CFARGS(.iattr = "cmpci")); 423 424 /* attach MPU-401 device */ 425 aa.type = AUDIODEV_TYPE_MPU; 426 aa.hwif = NULL; 427 aa.hdl = NULL; 428 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 429 CMPCI_REG_MPU_BASE, CMPCI_REG_MPU_SIZE, &sc->sc_mpu_ioh) == 0) 430 sc->sc_mpudev = config_found(sc->sc_dev, &aa, audioprint, 431 CFARGS(.iattr = "cmpci")); 432 433 /* get initial value (this is 0 and may be omitted but just in case) */ 434 sc->sc_reg_misc = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 435 CMPCI_REG_MISC) & ~CMPCI_REG_SPDIF48K; 436 437 cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_RESET, 0); 438 cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0); 439 cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0); 440 cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_OUTMIX, 441 CMPCI_SB16_SW_CD|CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE); 442 for (i = 0; i < CMPCI_NDEVS; i++) { 443 switch (i) { 444 /* 445 * CMI8738 defaults are 446 * master: 0xe0 (0x00 - 0xf8) 447 * FM, DAC: 0xc0 (0x00 - 0xf8) 448 * PC speaker: 0x80 (0x00 - 0xc0) 449 * others: 0 450 */ 451 /* volume */ 452 case CMPCI_MASTER_VOL: 453 v = 128; /* 224 */ 454 break; 455 case CMPCI_FM_VOL: 456 case CMPCI_DAC_VOL: 457 v = 192; 458 break; 459 case CMPCI_PCSPEAKER: 460 v = 128; 461 break; 462 463 /* booleans, set to true */ 464 case CMPCI_CD_MUTE: 465 case CMPCI_MIC_MUTE: 466 case CMPCI_LINE_IN_MUTE: 467 case CMPCI_AUX_IN_MUTE: 468 v = 1; 469 break; 470 471 /* volume with initial value 0 */ 472 case CMPCI_CD_VOL: 473 case CMPCI_LINE_IN_VOL: 474 case CMPCI_AUX_IN_VOL: 475 case CMPCI_MIC_VOL: 476 case CMPCI_MIC_RECVOL: 477 /* FALLTHROUGH */ 478 479 /* others are cleared */ 480 case CMPCI_MIC_PREAMP: 481 case CMPCI_RECORD_SOURCE: 482 case CMPCI_PLAYBACK_MODE: 483 case CMPCI_SPDIF_IN_SELECT: 484 case CMPCI_SPDIF_IN_PHASE: 485 case CMPCI_SPDIF_LOOP: 486 case CMPCI_SPDIF_OUT_PLAYBACK: 487 case CMPCI_SPDIF_OUT_VOLTAGE: 488 case CMPCI_MONITOR_DAC: 489 case CMPCI_REAR: 490 case CMPCI_INDIVIDUAL: 491 case CMPCI_REVERSE: 492 case CMPCI_SURROUND: 493 default: 494 v = 0; 495 break; 496 } 497 sc->sc_gain[i][CMPCI_LEFT] = sc->sc_gain[i][CMPCI_RIGHT] = v; 498 cmpci_set_mixer_gain(sc, i); 499 } 500} 501 502static int 503cmpci_intr(void *handle) 504{ 505 struct cmpci_softc *sc = handle; 506#if NMPU > 0 507 struct mpu_softc *sc_mpu = device_private(sc->sc_mpudev); 508#endif 509 uint32_t intrstat; 510 511 mutex_spin_enter(&sc->sc_intr_lock); 512 513 intrstat = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 514 CMPCI_REG_INTR_STATUS); 515 516 if (!(intrstat & CMPCI_REG_ANY_INTR)) { 517 mutex_spin_exit(&sc->sc_intr_lock); 518 return 0; 519 } 520 521 delay(10); 522 523 /* disable and reset intr */ 524 if (intrstat & CMPCI_REG_CH0_INTR) 525 cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL, 526 CMPCI_REG_CH0_INTR_ENABLE); 527 if (intrstat & CMPCI_REG_CH1_INTR) 528 cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL, 529 CMPCI_REG_CH1_INTR_ENABLE); 530 531 if (intrstat & CMPCI_REG_CH0_INTR) { 532 if (sc->sc_play.intr != NULL) 533 (*sc->sc_play.intr)(sc->sc_play.intr_arg); 534 } 535 if (intrstat & CMPCI_REG_CH1_INTR) { 536 if (sc->sc_rec.intr != NULL) 537 (*sc->sc_rec.intr)(sc->sc_rec.intr_arg); 538 } 539 540 /* enable intr */ 541 if (intrstat & CMPCI_REG_CH0_INTR) 542 cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL, 543 CMPCI_REG_CH0_INTR_ENABLE); 544 if (intrstat & CMPCI_REG_CH1_INTR) 545 cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL, 546 CMPCI_REG_CH1_INTR_ENABLE); 547 548#if NMPU > 0 549 if (intrstat & CMPCI_REG_UART_INTR && sc_mpu != NULL) 550 mpu_intr(sc_mpu); 551#endif 552 553 mutex_spin_exit(&sc->sc_intr_lock); 554 return 1; 555} 556 557static int 558cmpci_query_format(void *handle, audio_format_query_t *afp) 559{ 560 561 return audio_query_format(cmpci_formats, CMPCI_NFORMATS, afp); 562} 563 564static int 565cmpci_set_format(void *handle, int setmode, 566 const audio_params_t *play, const audio_params_t *rec, 567 audio_filter_reg_t *pfil, audio_filter_reg_t *rfil) 568{ 569 int i; 570 struct cmpci_softc *sc; 571 572 sc = handle; 573 for (i = 0; i < 2; i++) { 574 int md_format; 575 int md_divide; 576 int md_index; 577 int mode; 578 const audio_params_t *p; 579 580 switch (i) { 581 case 0: 582 mode = AUMODE_PLAY; 583 p = play; 584 break; 585 case 1: 586 mode = AUMODE_RECORD; 587 p = rec; 588 break; 589 default: 590 return EINVAL; 591 } 592 593 if (!(setmode & mode)) 594 continue; 595 596 md_index = cmpci_rate_to_index(p->sample_rate); 597 md_divide = cmpci_index_to_divider(md_index); 598 DPRINTF(("%s: sample:%u, divider=%d\n", 599 device_xname(sc->sc_dev), p->sample_rate, md_divide)); 600 601 /* format */ 602 md_format = p->channels == 1 603 ? CMPCI_REG_FORMAT_MONO : CMPCI_REG_FORMAT_STEREO; 604 md_format |= p->precision == 16 605 ? CMPCI_REG_FORMAT_16BIT : CMPCI_REG_FORMAT_8BIT; 606 if (mode & AUMODE_PLAY) { 607 cmpci_reg_partial_write_4(sc, 608 CMPCI_REG_CHANNEL_FORMAT, 609 CMPCI_REG_CH0_FORMAT_SHIFT, 610 CMPCI_REG_CH0_FORMAT_MASK, md_format); 611 cmpci_reg_partial_write_4(sc, 612 CMPCI_REG_FUNC_1, CMPCI_REG_DAC_FS_SHIFT, 613 CMPCI_REG_DAC_FS_MASK, md_divide); 614 sc->sc_play.md_divide = md_divide; 615 } else { 616 cmpci_reg_partial_write_4(sc, 617 CMPCI_REG_CHANNEL_FORMAT, 618 CMPCI_REG_CH1_FORMAT_SHIFT, 619 CMPCI_REG_CH1_FORMAT_MASK, md_format); 620 cmpci_reg_partial_write_4(sc, 621 CMPCI_REG_FUNC_1, CMPCI_REG_ADC_FS_SHIFT, 622 CMPCI_REG_ADC_FS_MASK, md_divide); 623 sc->sc_rec.md_divide = md_divide; 624 } 625 cmpci_set_out_ports(sc); 626 cmpci_set_in_ports(sc); 627 } 628 return 0; 629} 630 631static int 632cmpci_halt_output(void *handle) 633{ 634 struct cmpci_softc *sc; 635 636 sc = handle; 637 sc->sc_play.intr = NULL; 638 cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 639 cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 640 /* wait for reset DMA */ 641 cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 642 delay(10); 643 cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET); 644 645 return 0; 646} 647 648static int 649cmpci_halt_input(void *handle) 650{ 651 struct cmpci_softc *sc; 652 653 sc = handle; 654 sc->sc_rec.intr = NULL; 655 cmpci_reg_clear_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 656 cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 657 /* wait for reset DMA */ 658 cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 659 delay(10); 660 cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET); 661 662 return 0; 663} 664 665/* get audio device information */ 666static int 667cmpci_getdev(void *handle, struct audio_device *ad) 668{ 669 struct cmpci_softc *sc; 670 671 sc = handle; 672 strncpy(ad->name, "CMI PCI Audio", sizeof(ad->name)); 673 snprintf(ad->version, sizeof(ad->version), "0x%02x", 674 PCI_REVISION(sc->sc_class)); 675 switch (PCI_PRODUCT(sc->sc_id)) { 676 case PCI_PRODUCT_CMEDIA_CMI8338A: 677 strncpy(ad->config, "CMI8338A", sizeof(ad->config)); 678 break; 679 case PCI_PRODUCT_CMEDIA_CMI8338B: 680 strncpy(ad->config, "CMI8338B", sizeof(ad->config)); 681 break; 682 case PCI_PRODUCT_CMEDIA_CMI8738: 683 strncpy(ad->config, "CMI8738", sizeof(ad->config)); 684 break; 685 case PCI_PRODUCT_CMEDIA_CMI8738B: 686 strncpy(ad->config, "CMI8738B", sizeof(ad->config)); 687 break; 688 default: 689 strncpy(ad->config, "unknown", sizeof(ad->config)); 690 } 691 692 return 0; 693} 694 695/* mixer device information */ 696int 697cmpci_query_devinfo(void *handle, mixer_devinfo_t *dip) 698{ 699 static const char *const mixer_port_names[] = { 700 AudioNdac, AudioNfmsynth, AudioNcd, AudioNline, AudioNaux, 701 AudioNmicrophone 702 }; 703 static const char *const mixer_classes[] = { 704 AudioCinputs, AudioCoutputs, AudioCrecord, CmpciCplayback, 705 CmpciCspdif 706 }; 707 struct cmpci_softc *sc; 708 int i; 709 710 sc = handle; 711 dip->prev = dip->next = AUDIO_MIXER_LAST; 712 713 switch (dip->index) { 714 case CMPCI_INPUT_CLASS: 715 case CMPCI_OUTPUT_CLASS: 716 case CMPCI_RECORD_CLASS: 717 case CMPCI_PLAYBACK_CLASS: 718 case CMPCI_SPDIF_CLASS: 719 dip->type = AUDIO_MIXER_CLASS; 720 dip->mixer_class = dip->index; 721 strcpy(dip->label.name, 722 mixer_classes[dip->index - CMPCI_INPUT_CLASS]); 723 return 0; 724 725 case CMPCI_AUX_IN_VOL: 726 dip->un.v.delta = 1 << (8 - CMPCI_REG_AUX_VALBITS); 727 goto vol1; 728 case CMPCI_DAC_VOL: 729 case CMPCI_FM_VOL: 730 case CMPCI_CD_VOL: 731 case CMPCI_LINE_IN_VOL: 732 case CMPCI_MIC_VOL: 733 dip->un.v.delta = 1 << (8 - CMPCI_SB16_MIXER_VALBITS); 734 vol1: dip->mixer_class = CMPCI_INPUT_CLASS; 735 dip->next = dip->index + 6; /* CMPCI_xxx_MUTE */ 736 strcpy(dip->label.name, mixer_port_names[dip->index]); 737 dip->un.v.num_channels = (dip->index == CMPCI_MIC_VOL ? 1 : 2); 738 vol: 739 dip->type = AUDIO_MIXER_VALUE; 740 strcpy(dip->un.v.units.name, AudioNvolume); 741 return 0; 742 743 case CMPCI_MIC_MUTE: 744 dip->next = CMPCI_MIC_PREAMP; 745 /* FALLTHROUGH */ 746 case CMPCI_DAC_MUTE: 747 case CMPCI_FM_MUTE: 748 case CMPCI_CD_MUTE: 749 case CMPCI_LINE_IN_MUTE: 750 case CMPCI_AUX_IN_MUTE: 751 dip->prev = dip->index - 6; /* CMPCI_xxx_VOL */ 752 dip->mixer_class = CMPCI_INPUT_CLASS; 753 strcpy(dip->label.name, AudioNmute); 754 goto on_off; 755 on_off: 756 dip->type = AUDIO_MIXER_ENUM; 757 dip->un.e.num_mem = 2; 758 strcpy(dip->un.e.member[0].label.name, AudioNoff); 759 dip->un.e.member[0].ord = 0; 760 strcpy(dip->un.e.member[1].label.name, AudioNon); 761 dip->un.e.member[1].ord = 1; 762 return 0; 763 764 case CMPCI_MIC_PREAMP: 765 dip->mixer_class = CMPCI_INPUT_CLASS; 766 dip->prev = CMPCI_MIC_MUTE; 767 strcpy(dip->label.name, AudioNpreamp); 768 goto on_off; 769 case CMPCI_PCSPEAKER: 770 dip->mixer_class = CMPCI_INPUT_CLASS; 771 strcpy(dip->label.name, AudioNspeaker); 772 dip->un.v.num_channels = 1; 773 dip->un.v.delta = 1 << (8 - CMPCI_SB16_MIXER_SPEAKER_VALBITS); 774 goto vol; 775 case CMPCI_RECORD_SOURCE: 776 dip->mixer_class = CMPCI_RECORD_CLASS; 777 strcpy(dip->label.name, AudioNsource); 778 dip->type = AUDIO_MIXER_SET; 779 dip->un.s.num_mem = 7; 780 strcpy(dip->un.s.member[0].label.name, AudioNmicrophone); 781 dip->un.s.member[0].mask = CMPCI_RECORD_SOURCE_MIC; 782 strcpy(dip->un.s.member[1].label.name, AudioNcd); 783 dip->un.s.member[1].mask = CMPCI_RECORD_SOURCE_CD; 784 strcpy(dip->un.s.member[2].label.name, AudioNline); 785 dip->un.s.member[2].mask = CMPCI_RECORD_SOURCE_LINE_IN; 786 strcpy(dip->un.s.member[3].label.name, AudioNaux); 787 dip->un.s.member[3].mask = CMPCI_RECORD_SOURCE_AUX_IN; 788 strcpy(dip->un.s.member[4].label.name, AudioNwave); 789 dip->un.s.member[4].mask = CMPCI_RECORD_SOURCE_WAVE; 790 strcpy(dip->un.s.member[5].label.name, AudioNfmsynth); 791 dip->un.s.member[5].mask = CMPCI_RECORD_SOURCE_FM; 792 strcpy(dip->un.s.member[6].label.name, CmpciNspdif); 793 dip->un.s.member[6].mask = CMPCI_RECORD_SOURCE_SPDIF; 794 return 0; 795 case CMPCI_MIC_RECVOL: 796 dip->mixer_class = CMPCI_RECORD_CLASS; 797 strcpy(dip->label.name, AudioNmicrophone); 798 dip->un.v.num_channels = 1; 799 dip->un.v.delta = 1 << (8 - CMPCI_REG_ADMIC_VALBITS); 800 goto vol; 801 802 case CMPCI_PLAYBACK_MODE: 803 dip->mixer_class = CMPCI_PLAYBACK_CLASS; 804 dip->type = AUDIO_MIXER_ENUM; 805 strcpy(dip->label.name, AudioNmode); 806 dip->un.e.num_mem = 2; 807 strcpy(dip->un.e.member[0].label.name, AudioNdac); 808 dip->un.e.member[0].ord = CMPCI_PLAYBACK_MODE_WAVE; 809 strcpy(dip->un.e.member[1].label.name, CmpciNspdif); 810 dip->un.e.member[1].ord = CMPCI_PLAYBACK_MODE_SPDIF; 811 return 0; 812 case CMPCI_SPDIF_IN_SELECT: 813 dip->mixer_class = CMPCI_SPDIF_CLASS; 814 dip->type = AUDIO_MIXER_ENUM; 815 dip->next = CMPCI_SPDIF_IN_PHASE; 816 strcpy(dip->label.name, AudioNinput); 817 i = 0; 818 strcpy(dip->un.e.member[i].label.name, CmpciNspdin1); 819 dip->un.e.member[i++].ord = CMPCI_SPDIF_IN_SPDIN1; 820 if (CMPCI_ISCAP(sc, 2ND_SPDIN)) { 821 strcpy(dip->un.e.member[i].label.name, CmpciNspdin2); 822 dip->un.e.member[i++].ord = CMPCI_SPDIF_IN_SPDIN2; 823 } 824 strcpy(dip->un.e.member[i].label.name, CmpciNspdout); 825 dip->un.e.member[i++].ord = CMPCI_SPDIF_IN_SPDOUT; 826 dip->un.e.num_mem = i; 827 return 0; 828 case CMPCI_SPDIF_IN_PHASE: 829 dip->mixer_class = CMPCI_SPDIF_CLASS; 830 dip->prev = CMPCI_SPDIF_IN_SELECT; 831 strcpy(dip->label.name, CmpciNphase); 832 dip->type = AUDIO_MIXER_ENUM; 833 dip->un.e.num_mem = 2; 834 strcpy(dip->un.e.member[0].label.name, CmpciNpositive); 835 dip->un.e.member[0].ord = CMPCI_SPDIF_IN_PHASE_POSITIVE; 836 strcpy(dip->un.e.member[1].label.name, CmpciNnegative); 837 dip->un.e.member[1].ord = CMPCI_SPDIF_IN_PHASE_NEGATIVE; 838 return 0; 839 case CMPCI_SPDIF_LOOP: 840 dip->mixer_class = CMPCI_SPDIF_CLASS; 841 dip->next = CMPCI_SPDIF_OUT_PLAYBACK; 842 strcpy(dip->label.name, AudioNoutput); 843 dip->type = AUDIO_MIXER_ENUM; 844 dip->un.e.num_mem = 2; 845 strcpy(dip->un.e.member[0].label.name, CmpciNplayback); 846 dip->un.e.member[0].ord = CMPCI_SPDIF_LOOP_OFF; 847 strcpy(dip->un.e.member[1].label.name, CmpciNspdin); 848 dip->un.e.member[1].ord = CMPCI_SPDIF_LOOP_ON; 849 return 0; 850 case CMPCI_SPDIF_OUT_PLAYBACK: 851 dip->mixer_class = CMPCI_SPDIF_CLASS; 852 dip->prev = CMPCI_SPDIF_LOOP; 853 dip->next = CMPCI_SPDIF_OUT_VOLTAGE; 854 strcpy(dip->label.name, CmpciNplayback); 855 dip->type = AUDIO_MIXER_ENUM; 856 dip->un.e.num_mem = 2; 857 strcpy(dip->un.e.member[0].label.name, AudioNwave); 858 dip->un.e.member[0].ord = CMPCI_SPDIF_OUT_PLAYBACK_WAVE; 859 strcpy(dip->un.e.member[1].label.name, CmpciNlegacy); 860 dip->un.e.member[1].ord = CMPCI_SPDIF_OUT_PLAYBACK_LEGACY; 861 return 0; 862 case CMPCI_SPDIF_OUT_VOLTAGE: 863 dip->mixer_class = CMPCI_SPDIF_CLASS; 864 dip->prev = CMPCI_SPDIF_OUT_PLAYBACK; 865 strcpy(dip->label.name, CmpciNvoltage); 866 dip->type = AUDIO_MIXER_ENUM; 867 dip->un.e.num_mem = 2; 868 strcpy(dip->un.e.member[0].label.name, CmpciNhigh_v); 869 dip->un.e.member[0].ord = CMPCI_SPDIF_OUT_VOLTAGE_HIGH; 870 strcpy(dip->un.e.member[1].label.name, CmpciNlow_v); 871 dip->un.e.member[1].ord = CMPCI_SPDIF_OUT_VOLTAGE_LOW; 872 return 0; 873 case CMPCI_MONITOR_DAC: 874 dip->mixer_class = CMPCI_SPDIF_CLASS; 875 strcpy(dip->label.name, AudioNmonitor); 876 dip->type = AUDIO_MIXER_ENUM; 877 dip->un.e.num_mem = 3; 878 strcpy(dip->un.e.member[0].label.name, AudioNoff); 879 dip->un.e.member[0].ord = CMPCI_MONITOR_DAC_OFF; 880 strcpy(dip->un.e.member[1].label.name, CmpciNspdin); 881 dip->un.e.member[1].ord = CMPCI_MONITOR_DAC_SPDIN; 882 strcpy(dip->un.e.member[2].label.name, CmpciNspdout); 883 dip->un.e.member[2].ord = CMPCI_MONITOR_DAC_SPDOUT; 884 return 0; 885 886 case CMPCI_MASTER_VOL: 887 dip->mixer_class = CMPCI_OUTPUT_CLASS; 888 strcpy(dip->label.name, AudioNmaster); 889 dip->un.v.num_channels = 2; 890 dip->un.v.delta = 1 << (8 - CMPCI_SB16_MIXER_VALBITS); 891 goto vol; 892 case CMPCI_REAR: 893 dip->mixer_class = CMPCI_OUTPUT_CLASS; 894 dip->next = CMPCI_INDIVIDUAL; 895 strcpy(dip->label.name, CmpciNrear); 896 goto on_off; 897 case CMPCI_INDIVIDUAL: 898 dip->mixer_class = CMPCI_OUTPUT_CLASS; 899 dip->prev = CMPCI_REAR; 900 dip->next = CMPCI_REVERSE; 901 strcpy(dip->label.name, CmpciNindividual); 902 goto on_off; 903 case CMPCI_REVERSE: 904 dip->mixer_class = CMPCI_OUTPUT_CLASS; 905 dip->prev = CMPCI_INDIVIDUAL; 906 strcpy(dip->label.name, CmpciNreverse); 907 goto on_off; 908 case CMPCI_SURROUND: 909 dip->mixer_class = CMPCI_OUTPUT_CLASS; 910 strcpy(dip->label.name, CmpciNsurround); 911 goto on_off; 912 } 913 914 return ENXIO; 915} 916 917static int 918cmpci_alloc_dmamem(struct cmpci_softc *sc, size_t size, void **r_addr) 919{ 920 int error; 921 struct cmpci_dmanode *n; 922 923 error = 0; 924 n = kmem_alloc(sizeof(*n), KM_SLEEP); 925 926#define CMPCI_DMABUF_ALIGN 0x4 927#define CMPCI_DMABUF_BOUNDARY 0x0 928 n->cd_tag = sc->sc_dmat; 929 n->cd_size = size; 930 error = bus_dmamem_alloc(n->cd_tag, n->cd_size, 931 CMPCI_DMABUF_ALIGN, CMPCI_DMABUF_BOUNDARY, n->cd_segs, 932 sizeof(n->cd_segs)/sizeof(n->cd_segs[0]), &n->cd_nsegs, 933 BUS_DMA_WAITOK); 934 if (error) 935 goto mfree; 936 error = bus_dmamem_map(n->cd_tag, n->cd_segs, n->cd_nsegs, n->cd_size, 937 &n->cd_addr, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 938 if (error) 939 goto dmafree; 940 error = bus_dmamap_create(n->cd_tag, n->cd_size, 1, n->cd_size, 0, 941 BUS_DMA_WAITOK, &n->cd_map); 942 if (error) 943 goto unmap; 944 error = bus_dmamap_load(n->cd_tag, n->cd_map, n->cd_addr, n->cd_size, 945 NULL, BUS_DMA_WAITOK); 946 if (error) 947 goto destroy; 948 949 n->cd_next = sc->sc_dmap; 950 sc->sc_dmap = n; 951 *r_addr = KVADDR(n); 952 return 0; 953 954 destroy: 955 bus_dmamap_destroy(n->cd_tag, n->cd_map); 956 unmap: 957 bus_dmamem_unmap(n->cd_tag, n->cd_addr, n->cd_size); 958 dmafree: 959 bus_dmamem_free(n->cd_tag, 960 n->cd_segs, sizeof(n->cd_segs)/sizeof(n->cd_segs[0])); 961 mfree: 962 kmem_free(n, sizeof(*n)); 963 return error; 964} 965 966static int 967cmpci_free_dmamem(struct cmpci_softc *sc, void *addr, size_t size) 968{ 969 struct cmpci_dmanode **nnp; 970 971 for (nnp = &sc->sc_dmap; *nnp; nnp= &(*nnp)->cd_next) { 972 if ((*nnp)->cd_addr == addr) { 973 struct cmpci_dmanode *n = *nnp; 974 bus_dmamap_unload(n->cd_tag, n->cd_map); 975 bus_dmamap_destroy(n->cd_tag, n->cd_map); 976 bus_dmamem_unmap(n->cd_tag, n->cd_addr, n->cd_size); 977 bus_dmamem_free(n->cd_tag, n->cd_segs, 978 sizeof(n->cd_segs)/sizeof(n->cd_segs[0])); 979 kmem_free(n, sizeof(*n)); 980 return 0; 981 } 982 } 983 return -1; 984} 985 986static struct cmpci_dmanode * 987cmpci_find_dmamem(struct cmpci_softc *sc, void *addr) 988{ 989 struct cmpci_dmanode *p; 990 991 for (p = sc->sc_dmap; p; p = p->cd_next) 992 if (KVADDR(p) == (void *)addr) 993 break; 994 return p; 995} 996 997#if 0 998static void 999cmpci_print_dmamem(struct cmpci_dmanode *); 1000static void 1001cmpci_print_dmamem(struct cmpci_dmanode *p) 1002{ 1003 1004 DPRINTF(("DMA at virt:%p, dmaseg:%p, mapseg:%p, size:%p\n", 1005 (void *)p->cd_addr, (void *)p->cd_segs[0].ds_addr, 1006 (void *)DMAADDR(p), (void *)p->cd_size)); 1007} 1008#endif /* DEBUG */ 1009 1010static void * 1011cmpci_allocm(void *handle, int direction, size_t size) 1012{ 1013 void *addr; 1014 1015 addr = NULL; /* XXX gcc */ 1016 1017 if (cmpci_alloc_dmamem(handle, size, &addr)) 1018 return NULL; 1019 return addr; 1020} 1021 1022static void 1023cmpci_freem(void *handle, void *addr, size_t size) 1024{ 1025 1026 cmpci_free_dmamem(handle, addr, size); 1027} 1028 1029#define MAXVAL 256 1030static int 1031cmpci_adjust(int val, int mask) 1032{ 1033 1034 val += (MAXVAL - mask) >> 1; 1035 if (val >= MAXVAL) 1036 val = MAXVAL-1; 1037 return val & mask; 1038} 1039 1040static void 1041cmpci_set_mixer_gain(struct cmpci_softc *sc, int port) 1042{ 1043 int src; 1044 int bits, mask; 1045 1046 switch (port) { 1047 case CMPCI_MIC_VOL: 1048 cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_MIC, 1049 CMPCI_ADJUST_MIC_GAIN(sc, sc->sc_gain[port][CMPCI_LR])); 1050 return; 1051 case CMPCI_MASTER_VOL: 1052 src = CMPCI_SB16_MIXER_MASTER_L; 1053 break; 1054 case CMPCI_LINE_IN_VOL: 1055 src = CMPCI_SB16_MIXER_LINE_L; 1056 break; 1057 case CMPCI_AUX_IN_VOL: 1058 bus_space_write_1(sc->sc_iot, sc->sc_ioh, CMPCI_REG_MIXER_AUX, 1059 CMPCI_ADJUST_AUX_GAIN(sc, sc->sc_gain[port][CMPCI_LEFT], 1060 sc->sc_gain[port][CMPCI_RIGHT])); 1061 return; 1062 case CMPCI_MIC_RECVOL: 1063 cmpci_reg_partial_write_1(sc, CMPCI_REG_MIXER25, 1064 CMPCI_REG_ADMIC_SHIFT, CMPCI_REG_ADMIC_MASK, 1065 CMPCI_ADJUST_ADMIC_GAIN(sc, sc->sc_gain[port][CMPCI_LR])); 1066 return; 1067 case CMPCI_DAC_VOL: 1068 src = CMPCI_SB16_MIXER_VOICE_L; 1069 break; 1070 case CMPCI_FM_VOL: 1071 src = CMPCI_SB16_MIXER_FM_L; 1072 break; 1073 case CMPCI_CD_VOL: 1074 src = CMPCI_SB16_MIXER_CDDA_L; 1075 break; 1076 case CMPCI_PCSPEAKER: 1077 cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_SPEAKER, 1078 CMPCI_ADJUST_2_GAIN(sc, sc->sc_gain[port][CMPCI_LR])); 1079 return; 1080 case CMPCI_MIC_PREAMP: 1081 if (sc->sc_gain[port][CMPCI_LR]) 1082 cmpci_reg_clear_1(sc, CMPCI_REG_MIXER25, 1083 CMPCI_REG_MICGAINZ); 1084 else 1085 cmpci_reg_set_1(sc, CMPCI_REG_MIXER25, 1086 CMPCI_REG_MICGAINZ); 1087 return; 1088 1089 case CMPCI_DAC_MUTE: 1090 if (sc->sc_gain[port][CMPCI_LR]) 1091 cmpci_reg_set_1(sc, CMPCI_REG_MIXER24, 1092 CMPCI_REG_WSMUTE); 1093 else 1094 cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24, 1095 CMPCI_REG_WSMUTE); 1096 return; 1097 case CMPCI_FM_MUTE: 1098 if (sc->sc_gain[port][CMPCI_LR]) 1099 cmpci_reg_set_1(sc, CMPCI_REG_MIXER24, 1100 CMPCI_REG_FMMUTE); 1101 else 1102 cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24, 1103 CMPCI_REG_FMMUTE); 1104 return; 1105 case CMPCI_AUX_IN_MUTE: 1106 if (sc->sc_gain[port][CMPCI_LR]) 1107 cmpci_reg_clear_1(sc, CMPCI_REG_MIXER25, 1108 CMPCI_REG_VAUXRM|CMPCI_REG_VAUXLM); 1109 else 1110 cmpci_reg_set_1(sc, CMPCI_REG_MIXER25, 1111 CMPCI_REG_VAUXRM|CMPCI_REG_VAUXLM); 1112 return; 1113 case CMPCI_CD_MUTE: 1114 mask = CMPCI_SB16_SW_CD; 1115 goto sbmute; 1116 case CMPCI_MIC_MUTE: 1117 mask = CMPCI_SB16_SW_MIC; 1118 goto sbmute; 1119 case CMPCI_LINE_IN_MUTE: 1120 mask = CMPCI_SB16_SW_LINE; 1121 sbmute: 1122 bits = cmpci_mixerreg_read(sc, CMPCI_SB16_MIXER_OUTMIX); 1123 if (sc->sc_gain[port][CMPCI_LR]) 1124 bits = bits & ~mask; 1125 else 1126 bits = bits | mask; 1127 cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_OUTMIX, bits); 1128 return; 1129 1130 case CMPCI_SPDIF_IN_SELECT: 1131 case CMPCI_MONITOR_DAC: 1132 case CMPCI_PLAYBACK_MODE: 1133 case CMPCI_SPDIF_LOOP: 1134 case CMPCI_SPDIF_OUT_PLAYBACK: 1135 cmpci_set_out_ports(sc); 1136 return; 1137 case CMPCI_SPDIF_OUT_VOLTAGE: 1138 if (CMPCI_ISCAP(sc, SPDOUT_VOLTAGE)) { 1139 if (sc->sc_gain[CMPCI_SPDIF_OUT_VOLTAGE][CMPCI_LR] 1140 == CMPCI_SPDIF_OUT_VOLTAGE_HIGH) 1141 cmpci_reg_clear_reg_misc(sc, CMPCI_REG_5V); 1142 else 1143 cmpci_reg_set_reg_misc(sc, CMPCI_REG_5V); 1144 } 1145 return; 1146 case CMPCI_SURROUND: 1147 if (CMPCI_ISCAP(sc, SURROUND)) { 1148 if (sc->sc_gain[CMPCI_SURROUND][CMPCI_LR]) 1149 cmpci_reg_set_1(sc, CMPCI_REG_MIXER24, 1150 CMPCI_REG_SURROUND); 1151 else 1152 cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24, 1153 CMPCI_REG_SURROUND); 1154 } 1155 return; 1156 case CMPCI_REAR: 1157 if (CMPCI_ISCAP(sc, REAR)) { 1158 if (sc->sc_gain[CMPCI_REAR][CMPCI_LR]) 1159 cmpci_reg_set_reg_misc(sc, CMPCI_REG_N4SPK3D); 1160 else 1161 cmpci_reg_clear_reg_misc(sc, CMPCI_REG_N4SPK3D); 1162 } 1163 return; 1164 case CMPCI_INDIVIDUAL: 1165 if (CMPCI_ISCAP(sc, INDIVIDUAL_REAR)) { 1166 if (sc->sc_gain[CMPCI_REAR][CMPCI_LR]) 1167 cmpci_reg_set_1(sc, CMPCI_REG_MIXER24, 1168 CMPCI_REG_INDIVIDUAL); 1169 else 1170 cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24, 1171 CMPCI_REG_INDIVIDUAL); 1172 } 1173 return; 1174 case CMPCI_REVERSE: 1175 if (CMPCI_ISCAP(sc, REVERSE_FR)) { 1176 if (sc->sc_gain[CMPCI_REVERSE][CMPCI_LR]) 1177 cmpci_reg_set_1(sc, CMPCI_REG_MIXER24, 1178 CMPCI_REG_REVERSE_FR); 1179 else 1180 cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24, 1181 CMPCI_REG_REVERSE_FR); 1182 } 1183 return; 1184 case CMPCI_SPDIF_IN_PHASE: 1185 if (CMPCI_ISCAP(sc, SPDIN_PHASE)) { 1186 if (sc->sc_gain[CMPCI_SPDIF_IN_PHASE][CMPCI_LR] 1187 == CMPCI_SPDIF_IN_PHASE_POSITIVE) 1188 cmpci_reg_clear_1(sc, CMPCI_REG_CHANNEL_FORMAT, 1189 CMPCI_REG_SPDIN_PHASE); 1190 else 1191 cmpci_reg_set_1(sc, CMPCI_REG_CHANNEL_FORMAT, 1192 CMPCI_REG_SPDIN_PHASE); 1193 } 1194 return; 1195 default: 1196 return; 1197 } 1198 1199 cmpci_mixerreg_write(sc, src, 1200 CMPCI_ADJUST_GAIN(sc, sc->sc_gain[port][CMPCI_LEFT])); 1201 cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_L_TO_R(src), 1202 CMPCI_ADJUST_GAIN(sc, sc->sc_gain[port][CMPCI_RIGHT])); 1203} 1204 1205static void 1206cmpci_set_out_ports(struct cmpci_softc *sc) 1207{ 1208 uint8_t v; 1209 int enspdout; 1210 1211 if (!CMPCI_ISCAP(sc, SPDLOOP)) 1212 return; 1213 1214 /* SPDIF/out select */ 1215 if (sc->sc_gain[CMPCI_SPDIF_LOOP][CMPCI_LR] == CMPCI_SPDIF_LOOP_OFF) { 1216 /* playback */ 1217 cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP); 1218 } else { 1219 /* monitor SPDIF/in */ 1220 cmpci_reg_set_4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP); 1221 } 1222 1223 /* SPDIF in select */ 1224 v = sc->sc_gain[CMPCI_SPDIF_IN_SELECT][CMPCI_LR]; 1225 if (v & CMPCI_SPDIFIN_SPDIFIN2) 1226 cmpci_reg_set_reg_misc(sc, CMPCI_REG_2ND_SPDIFIN); 1227 else 1228 cmpci_reg_clear_reg_misc(sc, CMPCI_REG_2ND_SPDIFIN); 1229 if (v & CMPCI_SPDIFIN_SPDIFOUT) 1230 cmpci_reg_set_reg_misc(sc, CMPCI_REG_SPDFLOOPI); 1231 else 1232 cmpci_reg_clear_reg_misc(sc, CMPCI_REG_SPDFLOOPI); 1233 1234 enspdout = 0; 1235 /* playback to ... */ 1236 if (CMPCI_ISCAP(sc, SPDOUT) && 1237 sc->sc_gain[CMPCI_PLAYBACK_MODE][CMPCI_LR] 1238 == CMPCI_PLAYBACK_MODE_SPDIF && 1239 (sc->sc_play.md_divide == CMPCI_REG_RATE_44100 || 1240 (CMPCI_ISCAP(sc, SPDOUT_48K) && 1241 sc->sc_play.md_divide==CMPCI_REG_RATE_48000))) { 1242 /* playback to SPDIF */ 1243 cmpci_reg_set_4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF0_ENABLE); 1244 enspdout = 1; 1245 if (sc->sc_play.md_divide==CMPCI_REG_RATE_48000) 1246 cmpci_reg_set_reg_misc(sc, 1247 CMPCI_REG_SPDIFOUT_48K | CMPCI_REG_SPDIF48K); 1248 else 1249 cmpci_reg_clear_reg_misc(sc, 1250 CMPCI_REG_SPDIFOUT_48K | CMPCI_REG_SPDIF48K); 1251 } else { 1252 /* playback to DAC */ 1253 cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_1, 1254 CMPCI_REG_SPDIF0_ENABLE); 1255 if (CMPCI_ISCAP(sc, SPDOUT_48K)) 1256 cmpci_reg_clear_reg_misc(sc, 1257 CMPCI_REG_SPDIFOUT_48K | CMPCI_REG_SPDIF48K); 1258 } 1259 1260 /* legacy to SPDIF/out or not */ 1261 if (CMPCI_ISCAP(sc, SPDLEGACY)) { 1262 if (sc->sc_gain[CMPCI_SPDIF_OUT_PLAYBACK][CMPCI_LR] 1263 == CMPCI_SPDIF_OUT_PLAYBACK_WAVE) 1264 cmpci_reg_clear_4(sc, CMPCI_REG_LEGACY_CTRL, 1265 CMPCI_REG_LEGACY_SPDIF_ENABLE); 1266 else { 1267 cmpci_reg_set_4(sc, CMPCI_REG_LEGACY_CTRL, 1268 CMPCI_REG_LEGACY_SPDIF_ENABLE); 1269 enspdout = 1; 1270 } 1271 } 1272 1273 /* enable/disable SPDIF/out */ 1274 if (CMPCI_ISCAP(sc, XSPDOUT) && enspdout) 1275 cmpci_reg_set_4(sc, CMPCI_REG_LEGACY_CTRL, 1276 CMPCI_REG_XSPDIF_ENABLE); 1277 else 1278 cmpci_reg_clear_4(sc, CMPCI_REG_LEGACY_CTRL, 1279 CMPCI_REG_XSPDIF_ENABLE); 1280 1281 /* SPDIF monitor (digital to analog output) */ 1282 if (CMPCI_ISCAP(sc, SPDIN_MONITOR)) { 1283 v = sc->sc_gain[CMPCI_MONITOR_DAC][CMPCI_LR]; 1284 if (!(v & CMPCI_MONDAC_ENABLE)) 1285 cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24, 1286 CMPCI_REG_SPDIN_MONITOR); 1287 if (v & CMPCI_MONDAC_SPDOUT) 1288 cmpci_reg_set_4(sc, CMPCI_REG_FUNC_1, 1289 CMPCI_REG_SPDIFOUT_DAC); 1290 else 1291 cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_1, 1292 CMPCI_REG_SPDIFOUT_DAC); 1293 if (v & CMPCI_MONDAC_ENABLE) 1294 cmpci_reg_set_1(sc, CMPCI_REG_MIXER24, 1295 CMPCI_REG_SPDIN_MONITOR); 1296 } 1297} 1298 1299static int 1300cmpci_set_in_ports(struct cmpci_softc *sc) 1301{ 1302 int mask; 1303 int bitsl, bitsr; 1304 1305 mask = sc->sc_in_mask; 1306 1307 /* 1308 * Note CMPCI_RECORD_SOURCE_CD, CMPCI_RECORD_SOURCE_LINE_IN and 1309 * CMPCI_RECORD_SOURCE_FM are defined to the corresponding bit 1310 * of the mixer register. 1311 */ 1312 bitsr = mask & (CMPCI_RECORD_SOURCE_CD | CMPCI_RECORD_SOURCE_LINE_IN | 1313 CMPCI_RECORD_SOURCE_FM); 1314 1315 bitsl = CMPCI_SB16_MIXER_SRC_R_TO_L(bitsr); 1316 if (mask & CMPCI_RECORD_SOURCE_MIC) { 1317 bitsl |= CMPCI_SB16_MIXER_MIC_SRC; 1318 bitsr |= CMPCI_SB16_MIXER_MIC_SRC; 1319 } 1320 cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_L, bitsl); 1321 cmpci_mixerreg_write(sc, CMPCI_SB16_MIXER_ADCMIX_R, bitsr); 1322 1323 if (mask & CMPCI_RECORD_SOURCE_AUX_IN) 1324 cmpci_reg_set_1(sc, CMPCI_REG_MIXER25, 1325 CMPCI_REG_RAUXREN | CMPCI_REG_RAUXLEN); 1326 else 1327 cmpci_reg_clear_1(sc, CMPCI_REG_MIXER25, 1328 CMPCI_REG_RAUXREN | CMPCI_REG_RAUXLEN); 1329 1330 if (mask & CMPCI_RECORD_SOURCE_WAVE) 1331 cmpci_reg_set_1(sc, CMPCI_REG_MIXER24, 1332 CMPCI_REG_WAVEINL | CMPCI_REG_WAVEINR); 1333 else 1334 cmpci_reg_clear_1(sc, CMPCI_REG_MIXER24, 1335 CMPCI_REG_WAVEINL | CMPCI_REG_WAVEINR); 1336 1337 if (CMPCI_ISCAP(sc, SPDIN) && 1338 (sc->sc_rec.md_divide == CMPCI_REG_RATE_44100 || 1339 (CMPCI_ISCAP(sc, SPDOUT_48K) && 1340 sc->sc_rec.md_divide == CMPCI_REG_RATE_48000/* XXX? */))) { 1341 if (mask & CMPCI_RECORD_SOURCE_SPDIF) { 1342 /* enable SPDIF/in */ 1343 cmpci_reg_set_4(sc, 1344 CMPCI_REG_FUNC_1, 1345 CMPCI_REG_SPDIF1_ENABLE); 1346 } else { 1347 cmpci_reg_clear_4(sc, 1348 CMPCI_REG_FUNC_1, 1349 CMPCI_REG_SPDIF1_ENABLE); 1350 } 1351 } 1352 1353 return 0; 1354} 1355 1356static int 1357cmpci_set_port(void *handle, mixer_ctrl_t *cp) 1358{ 1359 struct cmpci_softc *sc; 1360 int lgain, rgain; 1361 1362 sc = handle; 1363 switch (cp->dev) { 1364 case CMPCI_MIC_VOL: 1365 case CMPCI_PCSPEAKER: 1366 case CMPCI_MIC_RECVOL: 1367 if (cp->un.value.num_channels != 1) 1368 return EINVAL; 1369 /* FALLTHROUGH */ 1370 case CMPCI_DAC_VOL: 1371 case CMPCI_FM_VOL: 1372 case CMPCI_CD_VOL: 1373 case CMPCI_LINE_IN_VOL: 1374 case CMPCI_AUX_IN_VOL: 1375 case CMPCI_MASTER_VOL: 1376 if (cp->type != AUDIO_MIXER_VALUE) 1377 return EINVAL; 1378 switch (cp->un.value.num_channels) { 1379 case 1: 1380 lgain = rgain = 1381 cp->un.value.level[AUDIO_MIXER_LEVEL_MONO]; 1382 break; 1383 case 2: 1384 lgain = cp->un.value.level[AUDIO_MIXER_LEVEL_LEFT]; 1385 rgain = cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT]; 1386 break; 1387 default: 1388 return EINVAL; 1389 } 1390 sc->sc_gain[cp->dev][CMPCI_LEFT] = lgain; 1391 sc->sc_gain[cp->dev][CMPCI_RIGHT] = rgain; 1392 1393 cmpci_set_mixer_gain(sc, cp->dev); 1394 break; 1395 1396 case CMPCI_RECORD_SOURCE: 1397 if (cp->type != AUDIO_MIXER_SET) 1398 return EINVAL; 1399 1400 if (cp->un.mask & ~(CMPCI_RECORD_SOURCE_MIC | 1401 CMPCI_RECORD_SOURCE_CD | CMPCI_RECORD_SOURCE_LINE_IN | 1402 CMPCI_RECORD_SOURCE_AUX_IN | CMPCI_RECORD_SOURCE_WAVE | 1403 CMPCI_RECORD_SOURCE_FM | CMPCI_RECORD_SOURCE_SPDIF)) 1404 return EINVAL; 1405 1406 if (cp->un.mask & CMPCI_RECORD_SOURCE_SPDIF) 1407 cp->un.mask = CMPCI_RECORD_SOURCE_SPDIF; 1408 1409 sc->sc_in_mask = cp->un.mask; 1410 return cmpci_set_in_ports(sc); 1411 1412 /* boolean */ 1413 case CMPCI_DAC_MUTE: 1414 case CMPCI_FM_MUTE: 1415 case CMPCI_CD_MUTE: 1416 case CMPCI_LINE_IN_MUTE: 1417 case CMPCI_AUX_IN_MUTE: 1418 case CMPCI_MIC_MUTE: 1419 case CMPCI_MIC_PREAMP: 1420 case CMPCI_PLAYBACK_MODE: 1421 case CMPCI_SPDIF_IN_PHASE: 1422 case CMPCI_SPDIF_LOOP: 1423 case CMPCI_SPDIF_OUT_PLAYBACK: 1424 case CMPCI_SPDIF_OUT_VOLTAGE: 1425 case CMPCI_REAR: 1426 case CMPCI_INDIVIDUAL: 1427 case CMPCI_REVERSE: 1428 case CMPCI_SURROUND: 1429 if (cp->type != AUDIO_MIXER_ENUM) 1430 return EINVAL; 1431 sc->sc_gain[cp->dev][CMPCI_LR] = cp->un.ord != 0; 1432 cmpci_set_mixer_gain(sc, cp->dev); 1433 break; 1434 1435 case CMPCI_SPDIF_IN_SELECT: 1436 switch (cp->un.ord) { 1437 case CMPCI_SPDIF_IN_SPDIN1: 1438 case CMPCI_SPDIF_IN_SPDIN2: 1439 case CMPCI_SPDIF_IN_SPDOUT: 1440 break; 1441 default: 1442 return EINVAL; 1443 } 1444 goto xenum; 1445 case CMPCI_MONITOR_DAC: 1446 switch (cp->un.ord) { 1447 case CMPCI_MONITOR_DAC_OFF: 1448 case CMPCI_MONITOR_DAC_SPDIN: 1449 case CMPCI_MONITOR_DAC_SPDOUT: 1450 break; 1451 default: 1452 return EINVAL; 1453 } 1454 xenum: 1455 if (cp->type != AUDIO_MIXER_ENUM) 1456 return EINVAL; 1457 sc->sc_gain[cp->dev][CMPCI_LR] = cp->un.ord; 1458 cmpci_set_mixer_gain(sc, cp->dev); 1459 break; 1460 1461 default: 1462 return EINVAL; 1463 } 1464 1465 return 0; 1466} 1467 1468static int 1469cmpci_get_port(void *handle, mixer_ctrl_t *cp) 1470{ 1471 struct cmpci_softc *sc; 1472 1473 sc = handle; 1474 switch (cp->dev) { 1475 case CMPCI_MIC_VOL: 1476 case CMPCI_PCSPEAKER: 1477 case CMPCI_MIC_RECVOL: 1478 if (cp->un.value.num_channels != 1) 1479 return EINVAL; 1480 /*FALLTHROUGH*/ 1481 case CMPCI_DAC_VOL: 1482 case CMPCI_FM_VOL: 1483 case CMPCI_CD_VOL: 1484 case CMPCI_LINE_IN_VOL: 1485 case CMPCI_AUX_IN_VOL: 1486 case CMPCI_MASTER_VOL: 1487 switch (cp->un.value.num_channels) { 1488 case 1: 1489 cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] = 1490 sc->sc_gain[cp->dev][CMPCI_LEFT]; 1491 break; 1492 case 2: 1493 cp->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = 1494 sc->sc_gain[cp->dev][CMPCI_LEFT]; 1495 cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = 1496 sc->sc_gain[cp->dev][CMPCI_RIGHT]; 1497 break; 1498 default: 1499 return EINVAL; 1500 } 1501 break; 1502 1503 case CMPCI_RECORD_SOURCE: 1504 cp->un.mask = sc->sc_in_mask; 1505 break; 1506 1507 case CMPCI_DAC_MUTE: 1508 case CMPCI_FM_MUTE: 1509 case CMPCI_CD_MUTE: 1510 case CMPCI_LINE_IN_MUTE: 1511 case CMPCI_AUX_IN_MUTE: 1512 case CMPCI_MIC_MUTE: 1513 case CMPCI_MIC_PREAMP: 1514 case CMPCI_PLAYBACK_MODE: 1515 case CMPCI_SPDIF_IN_SELECT: 1516 case CMPCI_SPDIF_IN_PHASE: 1517 case CMPCI_SPDIF_LOOP: 1518 case CMPCI_SPDIF_OUT_PLAYBACK: 1519 case CMPCI_SPDIF_OUT_VOLTAGE: 1520 case CMPCI_MONITOR_DAC: 1521 case CMPCI_REAR: 1522 case CMPCI_INDIVIDUAL: 1523 case CMPCI_REVERSE: 1524 case CMPCI_SURROUND: 1525 cp->un.ord = sc->sc_gain[cp->dev][CMPCI_LR]; 1526 break; 1527 1528 default: 1529 return EINVAL; 1530 } 1531 1532 return 0; 1533} 1534 1535/* ARGSUSED */ 1536static size_t 1537cmpci_round_buffersize(void *handle, int direction, 1538 size_t bufsize) 1539{ 1540 1541 if (bufsize > 0x10000) 1542 bufsize = 0x10000; 1543 1544 return bufsize; 1545} 1546 1547/* ARGSUSED */ 1548static int 1549cmpci_get_props(void *handle) 1550{ 1551 1552 return AUDIO_PROP_PLAYBACK | AUDIO_PROP_CAPTURE | 1553 AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1554} 1555 1556static int 1557cmpci_trigger_output(void *handle, void *start, void *end, int blksize, 1558 void (*intr)(void *), void *arg, 1559 const audio_params_t *param) 1560{ 1561 struct cmpci_softc *sc; 1562 struct cmpci_dmanode *p; 1563 int bps; 1564 1565 sc = handle; 1566 sc->sc_play.intr = intr; 1567 sc->sc_play.intr_arg = arg; 1568 bps = param->channels * param->precision / 8; 1569 if (!bps) 1570 return EINVAL; 1571 1572 /* set DMA frame */ 1573 if (!(p = cmpci_find_dmamem(sc, start))) 1574 return EINVAL; 1575 bus_space_write_4(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA0_BASE, 1576 DMAADDR(p)); 1577 delay(10); 1578 bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA0_BYTES, 1579 ((char *)end - (char *)start + 1) / bps - 1); 1580 delay(10); 1581 1582 /* set interrupt count */ 1583 bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA0_SAMPLES, 1584 (blksize + bps - 1) / bps - 1); 1585 delay(10); 1586 1587 /* start DMA */ 1588 cmpci_reg_clear_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR); /* PLAY */ 1589 cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); 1590 cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE); 1591 1592 return 0; 1593} 1594 1595static int 1596cmpci_trigger_input(void *handle, void *start, void *end, int blksize, 1597 void (*intr)(void *), void *arg, 1598 const audio_params_t *param) 1599{ 1600 struct cmpci_softc *sc; 1601 struct cmpci_dmanode *p; 1602 int bps; 1603 1604 sc = handle; 1605 sc->sc_rec.intr = intr; 1606 sc->sc_rec.intr_arg = arg; 1607 bps = param->channels * param->precision / 8; 1608 if (!bps) 1609 return EINVAL; 1610 1611 /* set DMA frame */ 1612 if (!(p=cmpci_find_dmamem(sc, start))) 1613 return EINVAL; 1614 bus_space_write_4(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA1_BASE, 1615 DMAADDR(p)); 1616 delay(10); 1617 bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA1_BYTES, 1618 ((char *)end - (char *)start + 1) / bps - 1); 1619 delay(10); 1620 1621 /* set interrupt count */ 1622 bus_space_write_2(sc->sc_iot, sc->sc_ioh, CMPCI_REG_DMA1_SAMPLES, 1623 (blksize + bps - 1) / bps - 1); 1624 delay(10); 1625 1626 /* start DMA */ 1627 cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR); /* REC */ 1628 cmpci_reg_set_4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); 1629 cmpci_reg_set_4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE); 1630 1631 return 0; 1632} 1633 1634static void 1635cmpci_get_locks(void *addr, kmutex_t **intr, kmutex_t **thread) 1636{ 1637 struct cmpci_softc *sc; 1638 1639 sc = addr; 1640 *intr = &sc->sc_intr_lock; 1641 *thread = &sc->sc_lock; 1642} 1643 1644/* end of file */ 1645