1/* $NetBSD: if_mvxpereg.h,v 1.8 2024/02/02 22:39:10 andvar Exp $ */ 2/* 3 * Copyright (c) 2015 Internet Initiative Japan Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27#ifndef _IF_MVXPEREG_H_ 28#define _IF_MVXPEREG_H_ 29 30#if BYTE_ORDER == BIG_ENDIAN 31#error "BIG ENDIAN not supported" 32#endif 33 34#define MVXPE_SIZE 0x4000 35 36#define MVXPE_NWINDOW 6 37#define MVXPE_NREMAP 4 38 39#define MVXPE_QUEUE_SIZE 8 40#define MVXPE_QUEUE(n) (1 << (n)) 41#define MVXPE_QUEUE_ALL 0xff 42 43/* 44 * Ethernet Unit Registers 45 * GbE0 BASE 0x00007.0000 SIZE 0x4000 46 * GbE1 BASE 0x00007.4000 SIZE 0x4000 47 * 48 * TBD: reasonable bus space submapping.... 49 */ 50/* Address Decoder Registers */ 51#define MVXPE_BASEADDR(n) (0x2200 + ((n) << 3)) /* Base Address */ 52#define MVXPE_S(n) (0x2204 + ((n) << 3)) /* Size */ 53#define MVXPE_HA(n) (0x2280 + ((n) << 2)) /* High Address Remap */ 54#define MVXPE_BARE 0x2290 /* Base Address Enable */ 55#define MVXPE_EPAP 0x2294 /* Ethernet Port Access Protect */ 56 57/* Global Miscellaneous Registers */ 58#define MVXPE_PHYADDR 0x2000 59#define MVXPE_SMI 0x2004 60#define MVXPE_EUDA 0x2008 /* Ethernet Unit Default Address */ 61#define MVXPE_EUDID 0x200c /* Ethernet Unit Default ID */ 62#define MVXPE_EUIC 0x2080 /* Ethernet Unit Interrupt Cause */ 63#define MVXPE_EUIM 0x2084 /* Ethernet Unit Interrupt Mask */ 64#define MVXPE_EUEA 0x2094 /* Ethernet Unit Error Address */ 65#define MVXPE_EUIAE 0x2098 /* Ethernet Unit Internal Addr Error */ 66#define MVXPE_EUC 0x20b0 /* Ethernet Unit Control */ 67 68/* Miscellaneous Registers */ 69#define MVXPE_SDC 0x241c /* SDMA Configuration */ 70 71/* Networking Controller Miscellaneous Registers */ 72#define MVXPE_PACC 0x2500 /* Port Acceleration Mode */ 73#define MVXPE_PV 0x25bc /* Port Version */ 74 75/* Rx DMA Hardware Parser Registers */ 76#define MVXPE_EVLANE 0x2410 /* VLAN EtherType */ 77#define MVXPE_MACAL 0x2414 /* MAC Address Low */ 78#define MVXPE_MACAH 0x2418 /* MAC Address High */ 79#define MVXPE_NDSCP 7 80#define MVXPE_DSCP(n) (0x2420 + ((n) << 2)) 81#define MVXPE_VPT2P 0x2440 /* VLAN Priority Tag to Priority */ 82#define MVXPE_ETP 0x24bc /* Ethernet Type Priority */ 83#define MVXPE_NDFSMT 64 84#define MVXPE_DFSMT(n) (0x3400 + ((n) << 2)) 85 /* Destination Address Filter Special Multicast Table */ 86#define MVXPE_NDFOMT 64 87#define MVXPE_DFOMT(n) (0x3500 + ((n) << 2)) 88 /* Destination Address Filter Other Multicast Table */ 89#define MVXPE_NDFUT 4 90#define MVXPE_DFUT(n) (0x3600 + ((n) << 2)) 91 /* Destination Address Filter Unicast Table */ 92 93/* Rx DMA Miscellaneous Registers */ 94#define MVXPE_PMFS 0x247c /* Port Rx Minimal Frame Size */ 95#define MVXPE_PDFC 0x2484 /* Port Rx Discard Frame Counter */ 96#define MVXPE_POFC 0x2488 /* Port Overrun Frame Counter */ 97#define MVXPE_RQC 0x2680 /* Receive Queue Command */ 98 99/* Rx DMA Networking Controller Miscellaneous Registers */ 100#define MVXPE_PRXC(q) (0x1400 + ((q) << 2)) /*Port RX queues Config*/ 101#define MVXPE_PRXSNP(q) (0x1420 + ((q) << 2)) /* Port RX queues Snoop */ 102#define MVXPE_PRXDQA(q) (0x1480 + ((q) << 2)) /*P RXqueues desc Q Addr*/ 103#define MVXPE_PRXDQS(q) (0x14a0 + ((q) << 2)) /*P RXqueues desc Q Size*/ 104#define MVXPE_PRXDQTH(q) (0x14c0 + ((q) << 2)) /*P RXqueues desc Q Thrs*/ 105#define MVXPE_PRXS(q) (0x14e0 + ((q) << 2)) /*Port RX queues Status */ 106#define MVXPE_PRXSU(q) (0x1500 + ((q) << 2)) /*P RXqueues Stat Update*/ 107#define MVXPE_PRXDI(q) (0x1520 + ((q) << 2)) /*P RXqueues Stat Update*/ 108#define MVXPE_PRXINIT 0x1cc0 /* Port RX Initialization */ 109 110/* Rx DMA Wake on LAN Registers 0x3690 - 0x36b8 */ 111 112/* Tx DMA Miscellaneous Registers */ 113#define MVXPE_TQC 0x2448 /* Transmit Queue Command */ 114#define MVXPE_PXTFTT 0x2478 /* Port Tx FIFO Threshold */ 115#define MVXPE_TXBADFCS 0x3cc0 /*Tx Bad FCS Transmitted Pckts Counter*/ 116#define MVXPE_TXDROPPED 0x3cc4 /* Tx Dropped Packets Counter */ 117 118/* Tx DMA Networking Controller Miscellaneous Registers */ 119#define MVXPE_PTXDQA(q) (0x3c00 + ((q) << 2)) /*P TXqueues desc Q Addr*/ 120#define MVXPE_PTXDQS(q) (0x3c20 + ((q) << 2)) /*P TXqueues desc Q Size*/ 121#define MVXPE_PTXS(q) (0x3c40 + ((q) << 2)) /* Port TX queues Status*/ 122#define MVXPE_PTXSU(q) (0x3c60 + ((q) << 2)) /*P TXqueues Stat Update*/ 123#define MVXPE_PTXDI(q) (0x3c80 + ((q) << 2)) /* P TXqueues Desc Index*/ 124#define MVXPE_TXTBC(q) (0x3ca0 + ((q) << 2)) /* TX Trans-ed Buf Count*/ 125#define MVXPE_PTXINIT 0x3cf0 /* Port TX Initialization */ 126 127/* Tx DMA Packet Modification Registers */ 128#define MVXPE_NMH 15 129#define MVXPE_TXMH(n) (0x3d44 + ((n) << 2)) 130#define MVXPE_TXMTU 0x3d88 131 132/* Tx DMA Queue Arbiter Registers (Version 1) */ 133#define MVXPE_TQFPC_V1 0x24dc /* Transmit Queue Fixed Priority Cfg */ 134#define MVXPE_TQTBC_V1 0x24e0 /* Transmit Queue Token-Bucket Cfg */ 135#define MVXPE_MTU_V1 0x24e8 /* MTU */ 136#define MVXPE_PMTBS_V1 0x24ec /* Port Max Token-Bucket Size */ 137#define MVXPE_TQTBCOUNT_V1(q) (0x2700 + ((q) << 4)) 138 /* Transmit Queue Token-Bucket Counter */ 139#define MVXPE_TQTBCONFIG_V1(q) (0x2704 + ((q) << 4)) 140 /* Transmit Queue Token-Bucket Configuration */ 141#define MVXPE_PTTBC_V1 0x2740 /* Port Transmit Backet Counter */ 142 143/* Tx DMA Queue Arbiter Registers (Version 3) */ 144#define MVXPE_TQC1_V3 0x3e00 /* Transmit Queue Command1 */ 145#define MVXPE_TQFPC_V3 0x3e04 /* Transmit Queue Fixed Priority Cfg */ 146#define MVXPE_BRC_V3 0x3e08 /* Basic Refill No of Clocks */ 147#define MVXPE_MTU_V3 0x3e0c /* MTU */ 148#define MVXPE_PREFILL_V3 0x3e10 /* Port Backet Refill */ 149#define MVXPE_PMTBS_V3 0x3e14 /* Port Max Token-Bucket Size */ 150#define MVXPE_QREFILL_V3(q) (0x3e20 + ((q) << 2)) 151 /* Transmit Queue Refill */ 152#define MVXPE_QMTBS_V3(q) (0x3e40 + ((q) << 2)) 153 /* Transmit Queue Max Token-Bucket Size */ 154#define MVXPE_QTTBC_V3(q) (0x3e60 + ((q) << 2)) 155 /* Transmit Queue Token-Bucket Counter */ 156#define MVXPE_TQAC_V3(q) (0x3e80 + ((q) << 2)) 157 /* Transmit Queue Arbiter Cfg */ 158#define MVXPE_TQIPG_V3(q) (0x3ea0 + ((q) << 2)) 159 /* Transmit Queue IPG(valid q=2..3) */ 160#define MVXPE_HITKNINLOPKT_V3 0x3eb0 /* High Token in Low Packet */ 161#define MVXPE_HITKNINASYNCPKT_V3 0x3eb4 /* High Token in Async Packet */ 162#define MVXPE_LOTKNINASYNCPKT_V3 0x3eb8 /* Low Token in Async Packet */ 163#define MVXPE_TS_V3 0x3ebc /* Token Speed */ 164 165/* RX_TX DMA Registers */ 166#define MVXPE_PXC 0x2400 /* Port Configuration */ 167#define MVXPE_PXCX 0x2404 /* Port Configuration Extend */ 168#define MVXPE_MH 0x2454 /* Marvell Header */ 169 170/* Serial(SMI/MII) Registers */ 171#define MVXPE_PSC0 0x243c /* Port Serial Control0 */ 172#define MVXPE_PS0 0x2444 /* Ethernet Port Status */ 173#define MVXPE_PSERDESCFG 0x24a0 /* Serdes Configuration */ 174#define MVXPE_PSERDESSTS 0x24a4 /* Serdes Status */ 175#define MVXPE_PSOMSCD 0x24f4 /* One mS Clock Divider */ 176#define MVXPE_PSPFCCD 0x24f8 /* Periodic Flow Control Clock Divider*/ 177 178/* Gigabit Ethernet MAC Serial Parameters Configuration Registers */ 179#define MVXPE_PSPC 0x2c14 /* Port Serial Parameters Config */ 180#define MVXPE_PSP1C 0x2c94 /* Port Serial Parameters 1 Config */ 181 182/* Gigabit Ethernet Auto-Negotiation Configuration Registers */ 183#define MVXPE_PANC 0x2c0c /* Port Auto-Negotiation Configuration*/ 184 185/* Gigabit Ethernet MAC Control Registers */ 186#define MVXPE_PMACC0 0x2c00 /* Port MAC Control 0 */ 187#define MVXPE_PMACC1 0x2c04 /* Port MAC Control 1 */ 188#define MVXPE_PMACC2 0x2c08 /* Port MAC Control 2 */ 189#define MVXPE_PMACC3 0x2c48 /* Port MAC Control 3 */ 190#define MVXPE_CCFCPST(p) (0x2c58 + ((p) << 2)) /*CCFC Port Speed Timerp*/ 191#define MVXPE_PMACC4 0x2c90 /* Port MAC Control 4 */ 192 193/* Gigabit Ethernet MAC Interrupt Registers */ 194#define MVXPE_PIC 0x2c20 195#define MVXPE_PIM 0x2c24 196 197/* Gigabit Ethernet Low Power Idle Registers */ 198#define MVXPE_LPIC0 0x2cc0 /* LowPowerIdle control 0 */ 199#define MVXPE_LPIC1 0x2cc4 /* LPI control 1 */ 200#define MVXPE_LPIC2 0x2cc8 /* LPI control 2 */ 201#define MVXPE_LPIS 0x2ccc /* LPI status */ 202#define MVXPE_LPIC 0x2cd0 /* LPI counter */ 203 204/* Gigabit Ethernet MAC PRBS Check Status Registers */ 205#define MVXPE_PPRBSS 0x2c38 /* Port PRBS Status */ 206#define MVXPE_PPRBSEC 0x2c3c /* Port PRBS Error Counter */ 207 208/* Gigabit Ethernet MAC Status Registers */ 209#define MVXPE_PSR 0x2c10 /* Port Status Register0 */ 210 211/* Networking Controller Interrupt Registers */ 212#define MVXPE_PRXITTH(q) (0x2580 + ((q) << 2)) 213 /* Port Rx Interrupt Threshold */ 214#define MVXPE_PRXTXTIC 0x25a0 /*Port RX_TX Threshold Interrupt Cause*/ 215#define MVXPE_PRXTXTIM 0x25a4 /*Port RX_TX Threshold Interrupt Mask */ 216#define MVXPE_PRXTXIC 0x25a8 /* Port RX_TX Interrupt Cause */ 217#define MVXPE_PRXTXIM 0x25ac /* Port RX_TX Interrupt Mask */ 218#define MVXPE_PMIC 0x25b0 /* Port Misc Interrupt Cause */ 219#define MVXPE_PMIM 0x25b4 /* Port Misc Interrupt Mask */ 220#define MVXPE_PIE 0x25b8 /* Port Interrupt Enable */ 221 222/* Miscellaneous Interrupt Registers */ 223#define MVXPE_PEUIAE 0x2494 /* Port Internal Address Error */ 224 225/* SGMII PHY Registers */ 226#define MVXPE_PPLLC 0x2e04 /* Power and PLL Control */ 227#define MVXPE_TESTC0 0x2e54 /* PHY Test Control 0 */ 228#define MVXPE_TESTPRBSEC0 0x2e7c /* PHY Test PRBS Error Counter 0 */ 229#define MVXPE_TESTPRBSEC1 0x2e80 /* PHY Test PRBS Error Counter 1 */ 230#define MVXPE_TESTOOB0 0x2e84 /* PHY Test OOB 0 */ 231#define MVXPE_DLE 0x2e8c /* Digital Loopback Enable */ 232#define MVXPE_RCS 0x2f18 /* Reference Clock Select */ 233#define MVXPE_COMPHYC 0x2f18 /* COMPHY Control */ 234 235/* 236 * Ethernet MAC MIB Registers 237 * GbE0 BASE 0x00007.3000 238 * GbE1 BASE 0x00007.7000 239 */ 240/* MAC MIB Counters 0x3000 - 0x307c */ 241#define MVXPE_PORTMIB_BASE 0x3000 242#define MVXPE_PORTMIB_SIZE 0x0100 243 244/* Rx */ 245#define MVXPE_MIB_RX_GOOD_OCT 0x00 /* 64bit */ 246#define MVXPE_MIB_RX_BAD_OCT 0x08 247#define MVXPE_MIB_TX_MAC_TRNS_ERR 0x0c 248#define MVXPE_MIB_RX_GOOD_FRAME 0x10 249#define MVXPE_MIB_RX_BAD_FRAME 0x14 250#define MVXPE_MIB_RX_BCAST_FRAME 0x18 251#define MVXPE_MIB_RX_MCAST_FRAME 0x1c 252#define MVXPE_MIB_RX_FRAME64_OCT 0x20 253#define MVXPE_MIB_RX_FRAME127_OCT 0x24 254#define MVXPE_MIB_RX_FRAME255_OCT 0x28 255#define MVXPE_MIB_RX_FRAME511_OCT 0x2c 256#define MVXPE_MIB_RX_FRAME1023_OCT 0x30 257#define MVXPE_MIB_RX_FRAMEMAX_OCT 0x34 258 259/* Tx */ 260#define MVXPE_MIB_TX_GOOD_OCT 0x38 /* 64bit */ 261#define MVXPE_MIB_TX_GOOD_FRAME 0x40 262#define MVXPE_MIB_TX_EXCES_COL 0x44 263#define MVXPE_MIB_TX_MCAST_FRAME 0x48 264#define MVXPE_MIB_TX_BCAST_FRAME 0x4c 265#define MVXPE_MIB_TX_MAC_CTL_ERR 0x50 266 267/* Flow Control */ 268#define MVXPE_MIB_FC_SENT 0x54 269#define MVXPE_MIB_FC_GOOD 0x58 270#define MVXPE_MIB_FC_BAD 0x5c 271 272/* Packet Processing */ 273#define MVXPE_MIB_PKT_UNDERSIZE 0x60 274#define MVXPE_MIB_PKT_FRAGMENT 0x64 275#define MVXPE_MIB_PKT_OVERSIZE 0x68 276#define MVXPE_MIB_PKT_JABBER 0x6c 277 278/* MAC Layer Errors */ 279#define MVXPE_MIB_MAC_RX_ERR 0x70 280#define MVXPE_MIB_MAC_CRC_ERR 0x74 281#define MVXPE_MIB_MAC_COL 0x78 282#define MVXPE_MIB_MAC_LATE_COL 0x7c 283 284/* END OF REGISTER NUMBERS */ 285 286/* 287 * 288 * Register Formats 289 * 290 */ 291/* 292 * Address Decoder Registers 293 */ 294/* Base Address (MVXPE_BASEADDR) */ 295#define MVXPE_BASEADDR_TARGET(target) ((target) & 0xf) 296#define MVXPE_BASEADDR_ATTR(attr) (((attr) & 0xff) << 8) 297#define MVXPE_BASEADDR_BASE(base) ((base) & 0xffff0000) 298 299/* Size (MVXPE_S) */ 300#define MVXPE_S_SIZE(size) (((size) - 1) & 0xffff0000) 301 302/* Base Address Enable (MVXPE_BARE) */ 303#define MVXPE_BARE_EN_MASK ((1 << MVXPE_NWINDOW) - 1) 304#define MVXPE_BARE_EN(win) ((1 << (win)) & MVXPE_BARE_EN_MASK) 305 306/* Ethernet Port Access Protect (MVXPE_EPAP) */ 307#define MVXPE_EPAP_AC_NAC 0x0 /* No access allowed */ 308#define MVXPE_EPAP_AC_RO 0x1 /* Read Only */ 309#define MVXPE_EPAP_AC_FA 0x3 /* Full access (r/w) */ 310#define MVXPE_EPAP_EPAR(win, ac) ((ac) << ((win) * 2)) 311 312/* 313 * Global Miscellaneous Registers 314 */ 315/* PHY Address (MVXPE_PHYADDR) */ 316#define MVXPE_PHYADDR_PHYAD(phy) ((phy) & 0x1f) 317#define MVXPE_PHYADDR_GET_PHYAD(reg) ((reg) & 0x1f) 318 319/* SMI register fields (MVXPE_SMI) */ 320#define MVXPE_SMI_DATA_MASK 0x0000ffff 321#define MVXPE_SMI_PHYAD(phy) (((phy) & 0x1f) << 16) 322#define MVXPE_SMI_REGAD(reg) (((reg) & 0x1f) << 21) 323#define MVXPE_SMI_OPCODE_WRITE (0 << 26) 324#define MVXPE_SMI_OPCODE_READ (1 << 26) 325#define MVXPE_SMI_READVALID (1 << 27) 326#define MVXPE_SMI_BUSY (1 << 28) 327 328/* Ethernet Unit Default ID (MVXPE_EUDID) */ 329#define MVXPE_EUDID_DIDR_MASK 0x0000000f 330#define MVXPE_EUDID_DIDR(id) ((id) & 0x0f) 331#define MVXPE_EUDID_DATTR_MASK 0x00000ff0 332#define MVXPE_EUDID_DATTR(attr) (((attr) & 0xff) << 4) 333 334/* Ethernet Unit Interrupt Cause (MVXPE_EUIC) */ 335#define MVXPE_EUIC_ETHERINTSUM (1 << 0) 336#define MVXPE_EUIC_PARITY (1 << 1) 337#define MVXPE_EUIC_ADDRVIOL (1 << 2) 338#define MVXPE_EUIC_ADDRVNOMATCH (1 << 3) 339#define MVXPE_EUIC_SMIDONE (1 << 4) 340#define MVXPE_EUIC_COUNTWA (1 << 5) 341#define MVXPE_EUIC_INTADDRERR (1 << 7) 342#define MVXPE_EUIC_PORT0DPERR (1 << 9) 343#define MVXPE_EUIC_TOPDPERR (1 << 12) 344 345/* Ethernet Unit Internal Addr Error (MVXPE_EUIAE) */ 346#define MVXPE_EUIAE_INTADDR_MASK 0x000001ff 347#define MVXPE_EUIAE_INTADDR(addr) ((addr) & 0x1ff) 348#define MVXPE_EUIAE_GET_INTADDR(addr) ((addr) & 0x1ff) 349 350/* Ethernet Unit Control (MVXPE_EUC) */ 351#define MVXPE_EUC_POLLING (1 << 1) 352#define MVXPE_EUC_PORTRESET (1 << 24) 353#define MVXPE_EUC_RAMSINITIALIZATIONCOMPLETED (1 << 25) 354 355/* 356 * Miscellaneous Registers 357 */ 358/* SDMA Configuration (MVXPE_SDC) */ 359#define MVXPE_SDC_RXBSZ(x) ((x) << 1) 360#define MVXPE_SDC_RXBSZ_MASK MVXPE_SDC_RXBSZ(7) 361#define MVXPE_SDC_RXBSZ_1_64BITWORDS MVXPE_SDC_RXBSZ(0) 362#define MVXPE_SDC_RXBSZ_2_64BITWORDS MVXPE_SDC_RXBSZ(1) 363#define MVXPE_SDC_RXBSZ_4_64BITWORDS MVXPE_SDC_RXBSZ(2) 364#define MVXPE_SDC_RXBSZ_8_64BITWORDS MVXPE_SDC_RXBSZ(3) 365#define MVXPE_SDC_RXBSZ_16_64BITWORDS MVXPE_SDC_RXBSZ(4) 366#define MVXPE_SDC_BLMR (1 << 4) 367#define MVXPE_SDC_BLMT (1 << 5) 368#define MVXPE_SDC_SWAPMODE (1 << 6) 369#define MVXPE_SDC_TXBSZ(x) ((x) << 22) 370#define MVXPE_SDC_TXBSZ_MASK MVXPE_SDC_TXBSZ(7) 371#define MVXPE_SDC_TXBSZ_1_64BITWORDS MVXPE_SDC_TXBSZ(0) 372#define MVXPE_SDC_TXBSZ_2_64BITWORDS MVXPE_SDC_TXBSZ(1) 373#define MVXPE_SDC_TXBSZ_4_64BITWORDS MVXPE_SDC_TXBSZ(2) 374#define MVXPE_SDC_TXBSZ_8_64BITWORDS MVXPE_SDC_TXBSZ(3) 375#define MVXPE_SDC_TXBSZ_16_64BITWORDS MVXPE_SDC_TXBSZ(4) 376 377/* 378 * Networking Controller Miscellaneous Registers 379 */ 380/* Port Acceleration Mode (MVXPE_PACC) */ 381#define MVXPE_PACC_ACCELERATIONMODE_MASK 0x7 382#define MVXPE_PACC_ACCELERATIONMODE_EDM 0x1 /* Enhanced Desc Mode */ 383 384/* Port Version (MVXPE_PV) */ 385#define MVXPE_PV_VERSION_MASK 0xff 386#define MVXPE_PV_VERSION(v) ((v) & 0xff) 387#define MVXPE_PV_GET_VERSION(reg) ((reg) & 0xff) 388 389/* 390 * Rx DMA Hardware Parser Registers 391 */ 392/* Ether Type Priority (MVXPE_ETP) */ 393#define MVXPE_ETP_ETHERTYPEPRIEN (1 << 0) /* EtherType Prio Ena */ 394#define MVXPE_ETP_ETHERTYPEPRIFRSTEN (1 << 1) 395#define MVXPE_ETP_ETHERTYPEPRIQ (0x7 << 2) /*EtherType Prio Queue*/ 396#define MVXPE_ETP_ETHERTYPEPRIVAL (0xffff << 5) /*EtherType Prio Value*/ 397#define MVXPE_ETP_FORCEUNICSTHIT (1 << 21) /* Force Unicast hit */ 398 399/* Destination Address Filter Registers (MVXPE_DF{SM,OM,U}T) */ 400#define MVXPE_DF(n, x) ((x) << (8 * (n))) 401#define MVXPE_DF_PASS (1 << 0) 402#define MVXPE_DF_QUEUE(q) ((q) << 1) 403#define MVXPE_DF_QUEUE_ALL ((7) << 1) 404#define MVXPE_DF_QUEUE_MASK ((7) << 1) 405 406/* 407 * Rx DMA Miscellaneous Registers 408 */ 409/* Port Rx Minimal Frame Size (MVXPE_PMFS) */ 410#define MVXPE_PMFS_RXMFS(rxmfs) (((rxmfs) - 40) & 0x7c) 411 412/* Receive Queue Command (MVXPE_RQC) */ 413#define MVXPE_RQC_EN_MASK (0xff << 0) /* Enable Q */ 414#define MVXPE_RQC_ENQ(q) (1 << (0 + (q))) 415#define MVXPE_RQC_EN(n) ((n) << 0) 416#define MVXPE_RQC_DIS_MASK (0xff << 8) /* Disable Q */ 417#define MVXPE_RQC_DISQ(q) (1 << (8 + (n))) 418#define MVXPE_RQC_DIS(n) ((n) << 8) 419 420/* 421 * Rx DMA Networking Controller Miscellaneous Registers 422 */ 423/* Port RX queues Configuration (MVXPE_PRXC) */ 424#define MVXPE_PRXC_PACKETOFFSET(o) (((o) & 0xf) << 8) 425 426/* Port RX queues Snoop (MVXPE_PRXSNP) */ 427#define MVXPE_PRXSNP_SNOOPNOOFBYTES(b) (((b) & 0x3fff) << 0) 428#define MVXPE_PRXSNP_L2DEPOSITNOOFBYTES(b) (((b) & 0x3fff) << 16) 429 430/* Port RX queues Descriptors Queue Size (MVXPE_PRXDQS) */ 431#define MVXPE_PRXDQS_DESCRIPTORSQUEUESIZE(s) (((s) & 0x3fff) << 0) 432#define MVXPE_PRXDQS_BUFFERSIZE(s) (((s) & 0x1fff) << 19) 433 434/* Port RX queues Descriptors Queue Threshold (MVXPE_PRXDQTH) */ 435 /* Occupied Descriptors Threshold */ 436#define MVXPE_PRXDQTH_ODT(x) (((x) & 0x3fff) << 0) 437 /* Non Occupied Descriptors Threshold */ 438#define MVXPE_PRXDQTH_NODT(x) (((x) & 0x3fff) << 16) 439 440/* Port RX queues Status (MVXPE_PRXS) */ 441 /* Occupied Descriptors Counter */ 442#define MVXPE_PRXS_ODC(x) (((x) & 0x3fff) << 0) 443 /* Non Occupied Descriptors Counter */ 444#define MVXPE_PRXS_NODC(x) (((x) & 0x3fff) << 16) 445#define MVXPE_PRXS_GET_ODC(reg) (((reg) >> 0) & 0x3fff) 446#define MVXPE_PRXS_GET_NODC(reg) (((reg) >> 16) & 0x3fff) 447 448/* Port RX queues Status Update (MVXPE_PRXSU) */ 449#define MVXPE_PRXSU_NOOFPROCESSEDDESCRIPTORS(x) (((x) & 0xff) << 0) 450#define MVXPE_PRXSU_NOOFNEWDESCRIPTORS(x) (((x) & 0xff) << 16) 451 452/* Port RX Initialization (MVXPE_PRXINIT) */ 453#define MVXPE_PRXINIT_RXDMAINIT (1 << 0) 454 455/* 456 * Rx DMA Wake on LAN Registers 457 */ 458/* XXX: not implemented yet */ 459 460/* 461 * Tx DMA Miscellaneous Registers 462 */ 463/* Transmit Queue Command (MVXPE_TQC) */ 464#define MVXPE_TQC_EN_MASK (0xff << 0) 465#define MVXPE_TQC_ENQ(q) (1 << ((q) + 0))/* Enable Q */ 466#define MVXPE_TQC_EN(n) ((n) << 0) 467#define MVXPE_TQC_DIS_MASK (0xff << 8) 468#define MVXPE_TQC_DISQ(q) (1 << ((q) + 8))/* Disable Q */ 469#define MVXPE_TQC_DIS(n) ((n) << 8) 470 471/* 472 * Tx DMA Networking Controller Miscellaneous Registers 473 */ 474/* Port TX queues Descriptors Queue Size (MVXPE_PTXDQS) */ 475 /* Descriptors Queue Size */ 476#define MVXPE_PTXDQS_DQS_MASK (0x3fff << 0) 477#define MVXPE_PTXDQS_DQS(x) (((x) & 0x3fff) << 0) 478 /* Transmitted Buffer Threshold */ 479#define MVXPE_PTXDQS_TBT_MASK (0x3fff << 16) 480#define MVXPE_PTXDQS_TBT(x) (((x) & 0x3fff) << 16) 481 482/* Port TX queues Status (MVXPE_PTXS) */ 483 /* Transmitted Buffer Counter */ 484#define MVXPE_PTXS_TBC(x) (((x) & 0x3fff) << 16) 485 486#define MVXPE_PTXS_GET_TBC(reg) (((reg) >> 16) & 0x3fff) 487 /* Pending Descriptors Counter */ 488#define MVXPE_PTXS_PDC(x) ((x) & 0x3fff) 489#define MVXPE_PTXS_GET_PDC(x) ((x) & 0x3fff) 490 491/* Port TX queues Status Update (MVXPE_PTXSU) */ 492 /* Number Of Written Descriptors */ 493#define MVXPE_PTXSU_NOWD(x) (((x) & 0xff) << 0) 494 /* Number Of Released Buffers */ 495#define MVXPE_PTXSU_NORB(x) (((x) & 0xff) << 16) 496 497/* TX Transmitted Buffers Counter (MVXPE_TXTBC) */ 498 /* Transmitted Buffers Counter */ 499#define MVXPE_TXTBC_TBC(x) (((x) & 0x3fff) << 16) 500 501/* Port TX Initialization (MVXPE_PTXINIT) */ 502#define MVXPE_PTXINIT_TXDMAINIT (1 << 0) 503 504/* 505 * Tx DMA Packet Modification Registers 506 */ 507/* XXX: not implemeted yet */ 508 509/* 510 * Tx DMA Queue Arbiter Registers (Version 1 ) 511 */ 512/* XXX: not implemented yet */ 513/* Transmit Queue Fixed Priority Configuration */ 514#define MVXPE_TQFPC_EN(q) (1 << (q)) 515 516 517/* 518 * RX_TX DMA Registers 519 */ 520/* Port Configuration (MVXPE_PXC) */ 521#define MVXPE_PXC_UPM (1 << 0) /* Uni Promisc mode */ 522#define MVXPE_PXC_RXQ(q) ((q) << 1) 523#define MVXPE_PXC_RXQ_MASK MVXPE_PXC_RXQ(7) 524#define MVXPE_PXC_RXQARP(q) ((q) << 4) 525#define MVXPE_PXC_RXQARP_MASK MVXPE_PXC_RXQARP(7) 526#define MVXPE_PXC_RB (1 << 7) /* Rej mode of MAC */ 527#define MVXPE_PXC_RBIP (1 << 8) 528#define MVXPE_PXC_RBARP (1 << 9) 529#define MVXPE_PXC_AMNOTXES (1 << 12) 530#define MVXPE_PXC_RBARPF (1 << 13) 531#define MVXPE_PXC_TCPCAPEN (1 << 14) 532#define MVXPE_PXC_UDPCAPEN (1 << 15) 533#define MVXPE_PXC_TCPQ(q) ((q) << 16) 534#define MVXPE_PXC_TCPQ_MASK MVXPE_PXC_TCPQ(7) 535#define MVXPE_PXC_UDPQ(q) ((q) << 19) 536#define MVXPE_PXC_UDPQ_MASK MVXPE_PXC_UDPQ(7) 537#define MVXPE_PXC_BPDUQ(q) ((q) << 22) 538#define MVXPE_PXC_BPDUQ_MASK MVXPE_PXC_BPDUQ(7) 539#define MVXPE_PXC_RXCS (1 << 25) 540 541/* Port Configuration Extend (MVXPE_PXCX) */ 542#define MVXPE_PXCX_SPAN (1 << 1) 543#define MVXPE_PXCX_TXCRCDIS (1 << 3) 544 545/* Marvell Header (MVXPE_MH) */ 546#define MVXPE_MH_MHEN (1 << 0) 547#define MVXPE_MH_DAPREFIX (0x3 << 1) 548#define MVXPE_MH_SPID (0xf << 4) 549#define MVXPE_MH_MHMASK (0x3 << 8) 550#define MVXPE_MH_MHMASK_8QUEUES (0x0 << 8) 551#define MVXPE_MH_MHMASK_4QUEUES (0x1 << 8) 552#define MVXPE_MH_MHMASK_2QUEUES (0x3 << 8) 553#define MVXPE_MH_DSAEN_MASK (0x3 << 10) 554#define MVXPE_MH_DSAEN_DISABLE (0x0 << 10) 555#define MVXPE_MH_DSAEN_NONEXTENDED (0x1 << 10) 556#define MVXPE_MH_DSAEN_EXTENDED (0x2 << 10) 557 558/* 559 * Serial(SMI/MII) Registers 560 */ 561/* Port Serial Control0 (MVXPE_PSC0) */ 562#define MVXPE_PSC0_FORCE_FC_MASK (0x3 << 5) 563#define MVXPE_PSC0_FORCE_FC(fc) (((fc) & 0x3) << 5) 564#define MVXPE_PSC0_FORCE_FC_PAUSE MVXPE_PSC0_FORCE_FC(0x1) 565#define MVXPE_PSC0_FORCE_FC_NO_PAUSE MVXPE_PSC0_FORCE_FC(0x0) 566#define MVXPE_PSC0_FORCE_BP_MASK (0x3 << 7) 567#define MVXPE_PSC0_FORCE_BP(fc) (((fc) & 0x3) << 5) 568#define MVXPE_PSC0_FORCE_BP_JAM MVXPE_PSC0_FORCE_BP(0x1) 569#define MVXPE_PSC0_FORCE_BP_NO_JAM MVXPE_PSC0_FORCE_BP(0x0) 570#define MVXPE_PSC0_DTE_ADV (1 << 14) 571#define MVXPE_PSC0_IGN_RXERR (1 << 28) 572#define MVXPE_PSC0_IGN_COLLISION (1 << 29) 573#define MVXPE_PSC0_IGN_CARRIER (1 << 30) 574 575/* Ethernet Port Status0 (MVXPE_PS0) */ 576#define MVXPE_PS0_TXINPROG (1 << 0) 577#define MVXPE_PS0_TXFIFOEMP (1 << 8) 578#define MVXPE_PS0_RXFIFOEMPTY (1 << 16) 579 580/* 581 * Gigabit Ethernet MAC Serial Parameters Configuration Registers 582 */ 583#define MVXPE_PSPC_MUST_SET (1 << 3 | 1 << 4 | 1 << 5 | 0x23 << 6) 584#define MVXPE_PSP1C_MUST_SET (1 << 0 | 1 << 1 | 1 << 2) 585 586/* 587 * Gigabit Ethernet Auto-Negotiation Configuration Registers 588 */ 589/* Port Auto-Negotiation Configuration (MVXPE_PANC) */ 590#define MVXPE_PANC_FORCELINKFAIL (1 << 0) 591#define MVXPE_PANC_FORCELINKPASS (1 << 1) 592#define MVXPE_PANC_INBANDANEN (1 << 2) 593#define MVXPE_PANC_INBANDANBYPASSEN (1 << 3) 594#define MVXPE_PANC_INBANDRESTARTAN (1 << 4) 595#define MVXPE_PANC_SETMIISPEED (1 << 5) 596#define MVXPE_PANC_SETGMIISPEED (1 << 6) 597#define MVXPE_PANC_ANSPEEDEN (1 << 7) 598#define MVXPE_PANC_SETFCEN (1 << 8) 599#define MVXPE_PANC_PAUSEADV (1 << 9) 600#define MVXPE_PANC_ANFCEN (1 << 11) 601#define MVXPE_PANC_SETFULLDX (1 << 12) 602#define MVXPE_PANC_ANDUPLEXEN (1 << 13) 603#define MVXPE_PANC_MUSTSET (1 << 15) 604 605/* 606 * Gigabit Ethernet MAC Control Registers 607 */ 608/* Port MAC Control 0 (MVXPE_PMACC0) */ 609#define MVXPE_PMACC0_PORTEN (1 << 0) 610#define MVXPE_PMACC0_PORTTYPE (1 << 1) 611#define MVXPE_PMACC0_FRAMESIZELIMIT(x) ((((x) >> 1) & 0x1fff) << 2) 612#define MVXPE_PMACC0_MUSTSET (1 << 15) 613 614/* Port MAC Control 1 (MVXPE_PMACC1) */ 615#define MVXPE_PMACC1_PCSLB (1 << 6) 616 617/* Port MAC Control 2 (MVXPE_PMACC2) */ 618#define MVXPE_PMACC2_PCSEN (1 << 3) 619#define MVXPE_PMACC2_RGMIIEN (1 << 4) 620#define MVXPE_PMACC2_PADDINGDIS (1 << 5) 621#define MVXPE_PMACC2_PORTMACRESET (1 << 6) 622#define MVXPE_PMACC2_PRBSCHECKEN (1 << 10) 623#define MVXPE_PMACC2_PRBSGENEN (1 << 11) 624#define MVXPE_PMACC2_SDTT_MASK (3 << 12) /* Select Data To Transmit */ 625#define MVXPE_PMACC2_SDTT_RM (0 << 12) /* Regular Mode */ 626#define MVXPE_PMACC2_SDTT_PRBS (1 << 12) /* PRBS Mode */ 627#define MVXPE_PMACC2_SDTT_ZC (2 << 12) /* Zero Constant */ 628#define MVXPE_PMACC2_SDTT_OC (3 << 12) /* One Constant */ 629#define MVXPE_PMACC2_MUSTSET (3 << 14) 630 631/* Port MAC Control 3 (MVXPE_PMACC3) */ 632#define MVXPE_PMACC3_IPG_MASK 0x7f80 633 634/* 635 * Gigabit Ethernet MAC Interrupt Registers 636 */ 637/* Port Interrupt Cause/Mask (MVXPE_PIC/MVXPE_PIM) */ 638#define MVXPE_PI_INTSUM (1 << 0) 639#define MVXPE_PI_LSC (1 << 1) /* LinkStatus Change */ 640#define MVXPE_PI_ACOP (1 << 2) /* AnCompleted OnPort */ 641#define MVXPE_PI_AOOR (1 << 5) /* AddressOut Of Range */ 642#define MVXPE_PI_SSC (1 << 6) /* SyncStatus Change */ 643#define MVXPE_PI_PRBSEOP (1 << 7) /* QSGMII PRBS error */ 644#define MVXPE_PI_MIBCWA (1 << 15) /* MIB counter wrap around */ 645#define MVXPE_PI_QSGMIIPRBSE (1 << 10) /* QSGMII PRBS error */ 646#define MVXPE_PI_PCSRXPRLPI (1 << 11) /* PCS Rx path received LPI*/ 647#define MVXPE_PI_PCSTXPRLPI (1 << 12) /* PCS Tx path received LPI*/ 648#define MVXPE_PI_MACRXPRLPI (1 << 13) /* MAC Rx path received LPI*/ 649#define MVXPE_PI_MIBCCD (1 << 14) /* MIB counters copy done */ 650 651/* 652 * Gigabit Ethernet MAC Low Power Idle Registers 653 */ 654/* LPI Control 0 (MVXPE_LPIC0) */ 655#define MVXPE_LPIC0_LILIMIT(x) (((x) & 0xff) << 0) 656#define MVXPE_LPIC0_TSLIMIT(x) (((x) & 0xff) << 8) 657 658/* LPI Control 1 (MVXPE_LPIC1) */ 659#define MVXPE_LPIC1_LPIRE (1 << 0) /* LPI request enable */ 660#define MVXPE_LPIC1_LPIRF (1 << 1) /* LPI request force */ 661#define MVXPE_LPIC1_LPIMM (1 << 2) /* LPI manual mode */ 662#define MVXPE_LPIC1_TWLIMIT(x) (((x) & 0xfff) << 4) 663 664/* LPI Control 2 (MVXPE_LPIC2) */ 665#define MVXPE_LPIC2_MUSTSET 0x17d 666 667/* LPI Status (MVXPE_LPIS) */ 668#define MVXPE_LPIS_PCSRXPLPIS (1 << 0) /* PCS Rx path LPI status */ 669#define MVXPE_LPIS_PCSTXPLPIS (1 << 1) /* PCS Tx path LPI status */ 670#define MVXPE_LPIS_MACRXPLPIS (1 << 2)/* MAC Rx path LP idle status */ 671#define MVXPE_LPIS_MACTXPLPWS (1 << 3)/* MAC Tx path LP wait status */ 672#define MVXPE_LPIS_MACTXPLPIS (1 << 4)/* MAC Tx path LP idle status */ 673 674/* 675 * Gigabit Ethernet MAC PRBS Check Status Registers 676 */ 677/* Port PRBS Status (MVXPE_PPRBSS) */ 678#define MVXPE_PPRBSS_PRBSCHECKLOCKED (1 << 0) 679#define MVXPE_PPRBSS_PRBSCHECKRDY (1 << 1) 680 681/* 682 * Gigabit Ethernet MAC Status Registers 683 */ 684/* Port Status Register (MVXPE_PSR) */ 685#define MVXPE_PSR_LINKUP (1 << 0) 686#define MVXPE_PSR_GMIISPEED (1 << 1) 687#define MVXPE_PSR_MIISPEED (1 << 2) 688#define MVXPE_PSR_FULLDX (1 << 3) 689#define MVXPE_PSR_RXFCEN (1 << 4) 690#define MVXPE_PSR_TXFCEN (1 << 5) 691#define MVXPE_PSR_PRP (1 << 6) /* Port Rx Pause */ 692#define MVXPE_PSR_PTP (1 << 7) /* Port Tx Pause */ 693#define MVXPE_PSR_PDP (1 << 8) /*Port is Doing Back-Pressure*/ 694#define MVXPE_PSR_SYNCFAIL10MS (1 << 10) 695#define MVXPE_PSR_ANDONE (1 << 11) 696#define MVXPE_PSR_IBANBA (1 << 12) /* InBand AutoNeg BypassAct */ 697#define MVXPE_PSR_SYNCOK (1 << 14) 698 699/* 700 * Networking Controller Interrupt Registers 701 */ 702/* Port RX_TX Interrupt Threshold */ 703#define MVXPE_PRXITTH_RITT(t) ((t) & 0xffffff) 704 705/* Port RX_TX Threshold Interrupt Cause/Mask (MVXPE_PRXTXTIC/MVXPE_PRXTXTIM) */ 706#define MVXPE_PRXTXTI_TBTCQ(q) (1 << ((q) + 0)) 707#define MVXPE_PRXTXTI_TBTCQ_MASK (0xff << 0) 708#define MVXPE_PRXTXTI_GET_TBTCQ(reg) (((reg) >> 0) & 0xff) 709 /* Tx Buffer Threshold Cross Queue*/ 710#define MVXPE_PRXTXTI_RBICTAPQ(q) (1 << ((q) + 8)) 711#define MVXPE_PRXTXTI_RBICTAPQ_MASK (0xff << 8) 712#define MVXPE_PRXTXTI_GET_RBICTAPQ(reg) (((reg) >> 8) & 0xff) 713 /* Rx Buffer Int. Coaleasing Th. Pri. Alrt Q */ 714#define MVXPE_PRXTXTI_RDTAQ(q) (1 << ((q) + 16)) 715#define MVXPE_PRXTXTI_RDTAQ_MASK (0xff << 16) 716#define MVXPE_PRXTXTI_GET_RDTAQ(reg) (((reg) >> 16) & 0xff) 717 /* Rx Descriptor Threshold Alert Queue*/ 718#define MVXPE_PRXTXTI_PRXTXICSUMMARY (1 << 29) /* PRXTXI summary */ 719#define MVXPE_PRXTXTI_PTXERRORSUMMARY (1 << 30) /* PTEXERROR summary */ 720#define MVXPE_PRXTXTI_PMISCICSUMMARY (1 << 31) /* PMISCIC summary */ 721 722/* Port RX_TX Interrupt Cause/Mask (MVXPE_PRXTXIC/MVXPE_PRXTXIM) */ 723#define MVXPE_PRXTXI_TBRQ(q) (1 << ((q) + 0)) 724#define MVXPE_PRXTXI_TBRQ_MASK (0xff << 0) 725#define MVXPE_PRXTXI_GET_TBRQ(reg) (((reg) >> 0) & 0xff) 726#define MVXPE_PRXTXI_RPQ(q) (1 << ((q) + 8)) 727#define MVXPE_PRXTXI_RPQ_MASK (0xff << 8) 728#define MVXPE_PRXTXI_GET_RPQ(reg) (((reg) >> 8) & 0xff) 729#define MVXPE_PRXTXI_RREQ(q) (1 << ((q) + 16)) 730#define MVXPE_PRXTXI_RREQ_MASK (0xff << 16) 731#define MVXPE_PRXTXI_GET_RREQ(reg) (((reg) >> 16) & 0xff) 732#define MVXPE_PRXTXI_PRXTXTHICSUMMARY (1 << 29) 733#define MVXPE_PRXTXI_PTXERRORSUMMARY (1 << 30) 734#define MVXPE_PRXTXI_PMISCICSUMMARY (1 << 31) 735 736/* Port Misc Interrupt Cause/Mask (MVXPE_PMIC/MVXPE_PMIM) */ 737#define MVXPE_PMI_PHYSTATUSCHNG (1 << 0) 738#define MVXPE_PMI_LINKCHANGE (1 << 1) 739#define MVXPE_PMI_IAE (1 << 7) /* Internal Address Error */ 740#define MVXPE_PMI_RXOVERRUN (1 << 8) 741#define MVXPE_PMI_RXCRCERROR (1 << 9) 742#define MVXPE_PMI_RXLARGEPACKET (1 << 10) 743#define MVXPE_PMI_TXUNDRN (1 << 11) 744#define MVXPE_PMI_PRBSERROR (1 << 12) 745#define MVXPE_PMI_SRSE (1 << 14) /* SerdesRealignSyncError */ 746#define MVXPE_PMI_TREQ(q) (1 << ((q) + 24)) /* TxResourceErrorQ */ 747#define MVXPE_PMI_TREQ_MASK (0xff << 24) /* TxResourceErrorQ */ 748 749/* Port Interrupt Enable (MVXPE_PIE) */ 750#define MVXPE_PIE_RXPKTINTRPTENB(q) (1 << ((q) + 0)) 751#define MVXPE_PIE_TXPKTINTRPTENB(q) (1 << ((q) + 8)) 752#define MVXPE_PIE_RXPKTINTRPTENB_MASK (0xff << 0) 753#define MVXPE_PIE_TXPKTINTRPTENB_MASK (0xff << 8) 754 755/* 756 * Miscellaneous Interrupt Registers 757 */ 758#define MVXPE_PEUIAE_ADDR_MASK (0x3fff) 759#define MVXPE_PEUIAE_ADDR(addr) ((addr) & 0x3fff) 760#define MVXPE_PEUIAE_GET_ADDR(reg) ((reg) & 0x3fff) 761 762/* 763 * SGMII PHY Registers 764 */ 765/* Power and PLL Control (MVXPE_PPLLC) */ 766#define MVXPE_PPLLC_REF_FREF_SEL_MASK (0xf << 0) 767#define MVXPE_PPLLC_PHY_MODE_MASK (7 << 5) 768#define MVXPE_PPLLC_PHY_MODE_SATA (0 << 5) 769#define MVXPE_PPLLC_PHY_MODE_SAS (1 << 5) 770#define MVXPE_PPLLC_PLL_LOCK (1 << 8) 771#define MVXPE_PPLLC_PU_DFE (1 << 10) 772#define MVXPE_PPLLC_PU_TX_INTP (1 << 11) 773#define MVXPE_PPLLC_PU_TX (1 << 12) 774#define MVXPE_PPLLC_PU_RX (1 << 13) 775#define MVXPE_PPLLC_PU_PLL (1 << 14) 776 777/* Digital Loopback Enable (MVXPE_DLE) */ 778#define MVXPE_DLE_LOCAL_SEL_BITS_MASK (3 << 10) 779#define MVXPE_DLE_LOCAL_SEL_BITS_10BITS (0 << 10) 780#define MVXPE_DLE_LOCAL_SEL_BITS_20BITS (1 << 10) 781#define MVXPE_DLE_LOCAL_SEL_BITS_40BITS (2 << 10) 782#define MVXPE_DLE_LOCAL_RXPHER_TO_TX_EN (1 << 12) 783#define MVXPE_DLE_LOCAL_ANA_TX2RX_LPBK_EN (1 << 13) 784#define MVXPE_DLE_LOCAL_DIG_TX2RX_LPBK_EN (1 << 14) 785#define MVXPE_DLE_LOCAL_DIG_RX2TX_LPBK_EN (1 << 15) 786 787/* Reference Clock Select (MVXPE_RCS) */ 788#define MVXPE_RCS_REFCLK_SEL (1 << 10) 789 790/* 791 * DMA descriptors 792 */ 793struct mvxpe_tx_desc { 794 /* LITTLE_ENDIAN */ 795 uint32_t command; /* off 0x00: commands */ 796 uint16_t l4ichk; /* initial checksum */ 797 uint16_t bytecnt; /* 0ff 0x04: buffer byte count */ 798 uint32_t bufptr; /* off 0x08: buffer ptr(PA) */ 799 uint32_t flags; /* off 0x0c: flags */ 800 uint32_t reserved0; /* off 0x10 */ 801 uint32_t reserved1; /* off 0x14 */ 802 uint32_t reserved2; /* off 0x18 */ 803 uint32_t reserved3; /* off 0x1c */ 804}; 805 806struct mvxpe_rx_desc { 807 /* LITTLE_ENDIAN */ 808 uint32_t status; /* status and flags */ 809 uint16_t reserved0; 810 uint16_t bytecnt; /* buffer byte count */ 811 uint32_t bufptr; /* packet buffer pointer */ 812 uint32_t reserved1; 813 uint32_t reserved2; 814 uint16_t reserved3; 815 uint16_t l4chk; /* L4 checksum */ 816 uint32_t reserved4; 817 uint32_t reserved5; 818}; 819 820/* 821 * Received packet command header: 822 * network controller => software 823 * the controller parse the packet and set some flags. 824 */ 825#define MVXPE_RX_IPV4_FRAGMENT (1 << 31) /* Fragment Indicator */ 826#define MVXPE_RX_L4_CHECKSUM_OK (1 << 30) /* L4 Checksum */ 827/* bit 29 reserved */ 828#define MVXPE_RX_U (1 << 28) /* Unknown Destination */ 829#define MVXPE_RX_F (1 << 27) /* First buffer */ 830#define MVXPE_RX_L (1 << 26) /* Last buffer */ 831#define MVXPE_RX_IP_HEADER_OK (1 << 25) /* IP Header is OK */ 832#define MVXPE_RX_L3_IP (1 << 24) /* IP Type 0:IP6 1:IP4 */ 833#define MVXPE_RX_L2_EV2 (1 << 23) /* Ethernet v2 frame */ 834#define MVXPE_RX_L4_MASK (3 << 21) /* L4 Type */ 835#define MVXPE_RX_L4_TCP (0x00 << 21) 836#define MVXPE_RX_L4_UDP (0x01 << 21) 837#define MVXPE_RX_L4_OTH (0x10 << 21) 838#define MVXPE_RX_BPDU (1 << 20) /* BPDU frame */ 839#define MVXPE_RX_VLAN (1 << 19) /* VLAN tag found */ 840#define MVXPE_RX_EC_MASK (3 << 17) /* Error code */ 841#define MVXPE_RX_EC_CE (0x00 << 17) /* CRC error */ 842#define MVXPE_RX_EC_OR (0x01 << 17) /* FIFO overrun */ 843#define MVXPE_RX_EC_MF (0x10 << 17) /* Max. frame len */ 844#define MVXPE_RX_EC_RE (0x11 << 17) /* Resource error */ 845#define MVXPE_RX_ES (1 << 16) /* Error summary */ 846/* bit 15:0 reserved */ 847 848/* 849 * Transmit packet command header: 850 * software => network controller 851 */ 852#define MVXPE_TX_CMD_L4_CHECKSUM_MASK (0x3 << 30) /* Do L4 Checksum */ 853#define MVXPE_TX_CMD_L4_CHECKSUM_FRAG (0x0 << 30) 854#define MVXPE_TX_CMD_L4_CHECKSUM_NOFRAG (0x1 << 30) 855#define MVXPE_TX_CMD_L4_CHECKSUM_NONE (0x2 << 30) 856#define MVXPE_TX_CMD_PACKET_OFFSET_MASK (0x7f << 23) /* Payload offset */ 857#define MVXPE_TX_CMD_W_PACKET_OFFSET(v) (((v) & 0x7f) << 23) 858/* bit 22 reserved */ 859#define MVXPE_TX_CMD_F (1 << 21) /* First buffer */ 860#define MVXPE_TX_CMD_L (1 << 20) /* Last buffer */ 861#define MVXPE_TX_CMD_PADDING (1 << 19) /* Pad short frame */ 862#define MVXPE_TX_CMD_IP4_CHECKSUM (1 << 18) /* Do IPv4 Checksum */ 863#define MVXPE_TX_CMD_L3_IP4 (0 << 17) 864#define MVXPE_TX_CMD_L3_IP6 (1 << 17) 865#define MVXPE_TX_CMD_L4_TCP (0 << 16) 866#define MVXPE_TX_CMD_L4_UDP (1 << 16) 867/* bit 15:13 reserved */ 868#define MVXPE_TX_CMD_IP_HEADER_LEN_MASK (0x1f << 8) /* IP header len >> 2 */ 869#define MVXPE_TX_CMD_IP_HEADER_LEN(v) (((v) & 0x1f) << 8) 870/* bit 7 reserved */ 871#define MVXPE_TX_CMD_L3_OFFSET_MASK (0x7f << 0) /* offset of L3 hdr. */ 872#define MVXPE_TX_CMD_L3_OFFSET(v) (((v) & 0x7f) << 0) 873 874/* 875 * Transmit packet extra attributes 876 * and error status returned from network controller. 877 */ 878#define MVXPE_TX_F_DSA_TAG (3 << 30) /* DSA Tag */ 879/* bit 29:8 reserved */ 880#define MVXPE_TX_F_MH_SEL (0xf << 4) /* Marvell Header */ 881/* bit 3 reserved */ 882#define MVXPE_TX_F_EC_MASK (3 << 1) /* Error code */ 883#define MVXPE_TX_F_EC_LC (0x00 << 1) /* Late Collision */ 884#define MVXPE_TX_F_EC_UR (0x01 << 1) /* Underrun */ 885#define MVXPE_TX_F_EC_RL (0x10 << 1) /* Excess. Collision */ 886#define MVXPE_TX_F_EC_RESERVED (0x11 << 1) 887#define MVXPE_TX_F_ES (1 << 0) /* Error summary */ 888 889#define MVXPE_ERROR_SUMMARY (1 << 0) 890#define MVXPE_BUFFER_OWNED_MASK (1 << 31) 891#define MVXPE_BUFFER_OWNED_BY_HOST (0 << 31) 892#define MVXPE_BUFFER_OWNED_BY_DMA (1 << 31) 893 894#endif /* _IF_MVXPEREG_H_ */ 895