1/* $NetBSD: if_ix.c,v 1.40 2024/02/10 09:21:53 andvar Exp $ */ 2 3/*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Rafal K. Boni. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#include <sys/cdefs.h> 33__KERNEL_RCSID(0, "$NetBSD: if_ix.c,v 1.40 2024/02/10 09:21:53 andvar Exp $"); 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/mbuf.h> 38#include <sys/errno.h> 39#include <sys/device.h> 40#include <sys/protosw.h> 41#include <sys/socket.h> 42 43#include <net/if.h> 44#include <net/if_dl.h> 45#include <net/if_types.h> 46#include <net/if_media.h> 47#include <net/if_ether.h> 48 49#include <sys/cpu.h> 50#include <sys/bus.h> 51#include <sys/intr.h> 52 53#include <dev/isa/isareg.h> 54#include <dev/isa/isavar.h> 55 56#include <dev/ic/i82586reg.h> 57#include <dev/ic/i82586var.h> 58#include <dev/isa/if_ixreg.h> 59 60#ifdef IX_DEBUG 61#define DPRINTF(x) printf x 62#else 63#define DPRINTF(x) 64#endif 65 66static int ix_media[] = { 67 IFM_ETHER | IFM_10_5, 68 IFM_ETHER | IFM_10_2, 69 IFM_ETHER | IFM_10_T, 70}; 71#define NIX_MEDIA __arraycount(ix_media) 72 73struct ix_softc { 74 struct ie_softc sc_ie; 75 76 bus_space_tag_t sc_regt; /* space tag for registers */ 77 bus_space_handle_t sc_regh; /* space handle for registers */ 78 79 uint8_t use_pio; /* use PIO rather than shared mem */ 80 uint16_t irq_encoded; /* encoded IRQ */ 81 void *sc_ih; /* interrupt handle */ 82}; 83 84static void ix_reset(struct ie_softc *, int); 85static void ix_atten(struct ie_softc *, int); 86static int ix_intrhook(struct ie_softc *, int); 87 88static void ix_copyin(struct ie_softc *, void *, int, size_t); 89static void ix_copyout(struct ie_softc *, const void *, int, size_t); 90 91static uint16_t ix_read_16(struct ie_softc *, int); 92static void ix_write_16(struct ie_softc *, int, uint16_t); 93static void ix_write_24(struct ie_softc *, int, int); 94static void ix_zeromem(struct ie_softc *, int, int); 95 96static void ix_mediastatus(struct ie_softc *, struct ifmediareq *); 97 98static uint16_t ix_read_eeprom(bus_space_tag_t, bus_space_handle_t, int); 99static void ix_eeprom_outbits(bus_space_tag_t, bus_space_handle_t, int, 100 int); 101static int ix_eeprom_inbits(bus_space_tag_t, bus_space_handle_t); 102static void ix_eeprom_clock(bus_space_tag_t, bus_space_handle_t, int); 103 104static int ix_match(device_t, cfdata_t, void *); 105static void ix_attach(device_t, device_t, void *); 106 107/* 108 * EtherExpress/16 support routines 109 */ 110static void 111ix_reset(struct ie_softc *sc, int why) 112{ 113 struct ix_softc *isc = (struct ix_softc *)sc; 114 115 switch (why) { 116 case CHIP_PROBE: 117 bus_space_write_1(isc->sc_regt, isc->sc_regh, IX_ECTRL, 118 IX_RESET_586); 119 delay(100); 120 bus_space_write_1(isc->sc_regt, isc->sc_regh, IX_ECTRL, 0); 121 delay(100); 122 break; 123 124 case CARD_RESET: 125 break; 126 } 127} 128 129static void 130ix_atten(struct ie_softc *sc, int why) 131{ 132 struct ix_softc *isc = (struct ix_softc *)sc; 133 134 bus_space_write_1(isc->sc_regt, isc->sc_regh, IX_ATTN, 0); 135} 136 137static uint16_t 138ix_read_eeprom(bus_space_tag_t iot, bus_space_handle_t ioh, int location) 139{ 140 int ectrl, edata; 141 142 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 143 ectrl &= IX_ECTRL_MASK; 144 ectrl |= IX_ECTRL_EECS; 145 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 146 147 ix_eeprom_outbits(iot, ioh, IX_EEPROM_READ, IX_EEPROM_OPSIZE1); 148 ix_eeprom_outbits(iot, ioh, location, IX_EEPROM_ADDR_SIZE); 149 edata = ix_eeprom_inbits(iot, ioh); 150 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 151 ectrl &= ~(IX_RESET_ASIC | IX_ECTRL_EEDI | IX_ECTRL_EECS); 152 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 153 ix_eeprom_clock(iot, ioh, 1); 154 ix_eeprom_clock(iot, ioh, 0); 155 return edata; 156} 157 158static void 159ix_eeprom_outbits(bus_space_tag_t iot, bus_space_handle_t ioh, int edata, 160 int count) 161{ 162 int ectrl, i; 163 164 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 165 ectrl &= ~IX_RESET_ASIC; 166 for (i = count - 1; i >= 0; i--) { 167 ectrl &= ~IX_ECTRL_EEDI; 168 if (edata & (1 << i)) { 169 ectrl |= IX_ECTRL_EEDI; 170 } 171 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 172 delay(1); /* eeprom data must be setup for 0.4 uSec */ 173 ix_eeprom_clock(iot, ioh, 1); 174 ix_eeprom_clock(iot, ioh, 0); 175 } 176 ectrl &= ~IX_ECTRL_EEDI; 177 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 178 delay(1); /* eeprom data must be held for 0.4 uSec */ 179} 180 181static int 182ix_eeprom_inbits(bus_space_tag_t iot, bus_space_handle_t ioh) 183{ 184 int ectrl, edata, i; 185 186 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 187 ectrl &= ~IX_RESET_ASIC; 188 for (edata = 0, i = 0; i < 16; i++) { 189 edata = edata << 1; 190 ix_eeprom_clock(iot, ioh, 1); 191 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 192 if (ectrl & IX_ECTRL_EEDO) { 193 edata |= 1; 194 } 195 ix_eeprom_clock(iot, ioh, 0); 196 } 197 return edata; 198} 199 200static void 201ix_eeprom_clock(bus_space_tag_t iot, bus_space_handle_t ioh, int state) 202{ 203 int ectrl; 204 205 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 206 ectrl &= ~(IX_RESET_ASIC | IX_ECTRL_EESK); 207 if (state) { 208 ectrl |= IX_ECTRL_EESK; 209 } 210 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 211 delay(9); /* EESK must be stable for 8.38 uSec */ 212} 213 214static int 215ix_intrhook(struct ie_softc *sc, int where) 216{ 217 struct ix_softc *isc = (struct ix_softc *)sc; 218 219 switch (where) { 220 case INTR_ENTER: 221 /* Entering ISR: disable card interrupts */ 222 bus_space_write_1(isc->sc_regt, isc->sc_regh, 223 IX_IRQ, isc->irq_encoded); 224 break; 225 226 case INTR_EXIT: 227 /* Exiting ISR: re-enable card interrupts */ 228 bus_space_write_1(isc->sc_regt, isc->sc_regh, IX_IRQ, 229 isc->irq_encoded | IX_IRQ_ENABLE); 230 break; 231 } 232 233 return 1; 234} 235 236 237static void 238ix_copyin(struct ie_softc *sc, void *dst, int offset, size_t size) 239{ 240 int i, dribble; 241 uint8_t *bptr = dst; 242 uint16_t *wptr = dst; 243 struct ix_softc *isc = (struct ix_softc *)sc; 244 245 if (isc->use_pio) { 246 /* Reset read pointer to the specified offset */ 247 bus_space_write_2(sc->bt, sc->bh, IX_READPTR, offset); 248 } 249 250 if (offset % 2) { 251 if (isc->use_pio) 252 *bptr = bus_space_read_1(sc->bt, sc->bh, IX_DATAPORT); 253 else 254 *bptr = bus_space_read_1(sc->bt, sc->bh, offset); 255 offset++; bptr++; size--; 256 } 257 258 dribble = size % 2; 259 wptr = (uint16_t*)bptr; 260 261 if (isc->use_pio) { 262 for (i = 0; i < size / 2; i++) { 263 *wptr = bus_space_read_2(sc->bt, sc->bh, IX_DATAPORT); 264 wptr++; 265 } 266 } else 267 bus_space_read_region_2(sc->bt, sc->bh, offset, 268 (uint16_t *)bptr, size / 2); 269 270 if (dribble) { 271 bptr += size - 1; 272 offset += size - 1; 273 274 if (isc->use_pio) 275 *bptr = bus_space_read_1(sc->bt, sc->bh, IX_DATAPORT); 276 else 277 *bptr = bus_space_read_1(sc->bt, sc->bh, offset); 278 } 279} 280 281static void 282ix_copyout(struct ie_softc *sc, const void *src, int offset, size_t size) 283{ 284 int i, dribble; 285 const uint8_t *bptr = src; 286 const uint16_t *wptr = src; 287 struct ix_softc *isc = (struct ix_softc *)sc; 288 289 if (isc->use_pio) { 290 /* Reset write pointer to the specified offset */ 291 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); 292 } 293 294 if (offset % 2) { 295 if (isc->use_pio) 296 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, *bptr); 297 else 298 bus_space_write_1(sc->bt, sc->bh, offset, *bptr); 299 offset++; bptr++; size--; 300 } 301 302 dribble = size % 2; 303 wptr = (const uint16_t*)bptr; 304 305 if (isc->use_pio) { 306 for (i = 0; i < size / 2; i++) { 307 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, *wptr); 308 wptr++; 309 } 310 } else 311 bus_space_write_region_2(sc->bt, sc->bh, offset, 312 (const uint16_t *)bptr, size / 2); 313 314 if (dribble) { 315 bptr += size - 1; 316 offset += size - 1; 317 318 if (isc->use_pio) 319 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, *bptr); 320 else 321 bus_space_write_1(sc->bt, sc->bh, offset, *bptr); 322 } 323} 324 325static uint16_t 326ix_read_16(struct ie_softc *sc, int offset) 327{ 328 struct ix_softc *isc = (struct ix_softc *)sc; 329 330 if (isc->use_pio) { 331 /* Reset read pointer to the specified offset */ 332 bus_space_write_2(sc->bt, sc->bh, IX_READPTR, offset); 333 334 return bus_space_read_2(sc->bt, sc->bh, IX_DATAPORT); 335 } else { 336 return bus_space_read_2(sc->bt, sc->bh, offset); 337 } 338} 339 340static void 341ix_write_16(struct ie_softc *sc, int offset, uint16_t value) 342{ 343 struct ix_softc *isc = (struct ix_softc *)sc; 344 345 if (isc->use_pio) { 346 /* Reset write pointer to the specified offset */ 347 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); 348 349 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, value); 350 } else { 351 bus_space_write_2(sc->bt, sc->bh, offset, value); 352 } 353} 354 355static void 356ix_write_24 (struct ie_softc *sc, int offset, int addr) 357{ 358 char *ptr; 359 struct ix_softc *isc = (struct ix_softc *)sc; 360 int val = addr + (u_long)sc->sc_maddr - (u_long)sc->sc_iobase; 361 362 if (isc->use_pio) { 363 /* Reset write pointer to the specified offset */ 364 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); 365 366 ptr = (char*)&val; 367 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, 368 *((uint16_t *)ptr)); 369 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, 370 *((uint16_t *)(ptr + 2))); 371 } else { 372 bus_space_write_4(sc->bt, sc->bh, offset, val); 373 } 374} 375 376static void 377ix_zeromem(struct ie_softc *sc, int offset, int count) 378{ 379 int i; 380 int dribble; 381 struct ix_softc *isc = (struct ix_softc *)sc; 382 383 if (isc->use_pio) { 384 /* Reset write pointer to the specified offset */ 385 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); 386 387 if (offset % 2) { 388 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, 0); 389 count--; 390 } 391 392 dribble = count % 2; 393 for (i = 0; i < count / 2; i++) 394 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, 0); 395 396 if (dribble) 397 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, 0); 398 } else { 399 bus_space_set_region_1(sc->bt, sc->bh, offset, 0, count); 400 } 401} 402 403static void 404ix_mediastatus(struct ie_softc *sc, struct ifmediareq *ifmr) 405{ 406 struct ifmedia *ifm = &sc->sc_media; 407 408 /* The currently selected media is always the active media. */ 409 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 410} 411 412int 413ix_match(device_t parent, cfdata_t cf, void *aux) 414{ 415 int i; 416 int rv = 0; 417 bus_addr_t maddr; 418 bus_size_t msiz; 419 u_short checksum = 0; 420 bus_space_handle_t ioh; 421 bus_space_tag_t iot; 422 uint8_t val, bart_config; 423 uint16_t pg, adjust, decode, edecode; 424 uint16_t board_id, id_var1, id_var2, irq, irq_encoded; 425 struct isa_attach_args * const ia = aux; 426 short irq_translate[] = {0, 0x09, 0x03, 0x04, 0x05, 0x0a, 0x0b, 0}; 427 428 if (ia->ia_nio < 1) 429 return 0; 430 if (ia->ia_niomem < 1) 431 return 0; 432 if (ia->ia_nirq < 1) 433 return 0; 434 435 if (ISA_DIRECT_CONFIG(ia)) 436 return 0; 437 438 iot = ia->ia_iot; 439 440 if (ia->ia_io[0].ir_addr == ISA_UNKNOWN_PORT) 441 return 0; 442 443 if (bus_space_map(iot, ia->ia_io[0].ir_addr, 444 IX_IOSIZE, 0, &ioh) != 0) { 445 DPRINTF(("Can't map io space at 0x%x\n", 446 ia->ia_io[0].ir_addr)); 447 return 0; 448 } 449 450 /* XXX: reset any ee16 at the current iobase */ 451 bus_space_write_1(iot, ioh, IX_ECTRL, IX_RESET_ASIC); 452 bus_space_write_1(iot, ioh, IX_ECTRL, 0); 453 delay(240); 454 455 /* Now look for ee16. */ 456 board_id = id_var1 = id_var2 = 0; 457 for (i = 0; i < 4 ; i++) { 458 id_var1 = bus_space_read_1(iot, ioh, IX_ID_PORT); 459 id_var2 = ((id_var1 & 0x03) << 2); 460 board_id |= (( id_var1 >> 4) << id_var2); 461 } 462 463 if (board_id != IX_ID) { 464 DPRINTF(("BART ID mismatch (got 0x%04x, expected 0x%04x)\n", 465 board_id, IX_ID)); 466 goto out; 467 } 468 469 /* 470 * The shared RAM size and location of the EE16 is encoded into 471 * EEPROM location 6. The location of the first set bit tells us 472 * the memory address (0xc0000 + (0x4000 * FSB)), where FSB is the 473 * number of the first set bit. The zeroes are then shifted out, 474 * and the results is the memory size (1 = 16k, 3 = 32k, 7 = 48k, 475 * 0x0f = 64k). 476 * 477 * Examples: 478 * 0x3c -> 64k@0xc8000, 0x70 -> 48k@0xd0000, 0xc0 -> 32k@0xd8000 479 * 0x80 -> 16k@0xdc000. 480 * 481 * Side note: this comes from reading the old driver rather than 482 * from a more definitive source, so it could be out-of-whack 483 * with what the card can do... 484 */ 485 486 val = ix_read_eeprom(iot, ioh, 6) & 0xff; 487 for (pg = 0; pg < 8; pg++) { 488 if (val & 1) 489 break; 490 val >>= 1; 491 } 492 493 maddr = 0xc0000 + (pg * 0x4000); 494 495 switch (val) { 496 case 0x00: 497 maddr = 0; 498 msiz = 0; 499 break; 500 501 case 0x01: 502 msiz = 16 * 1024; 503 break; 504 505 case 0x03: 506 msiz = 32 * 1024; 507 break; 508 509 case 0x07: 510 msiz = 48 * 1024; 511 break; 512 513 case 0x0f: 514 msiz = 64 * 1024; 515 break; 516 517 default: 518 DPRINTF(("invalid memory size %02x\n", val)); 519 goto out; 520 } 521 522 if (ia->ia_iomem[0].ir_addr != ISA_UNKNOWN_IOMEM && 523 ia->ia_iomem[0].ir_addr != maddr) { 524 DPRINTF(( 525 "ix_match: memaddr of board @ 0x%x doesn't match config\n", 526 ia->ia_iomem[0].ir_addr)); 527 goto out; 528 } 529 530 if (ia->ia_iomem[0].ir_size != ISA_UNKNOWN_IOSIZ && 531 ia->ia_iomem[0].ir_size != msiz) { 532 DPRINTF(( 533 "ix_match: memsize of board @ 0x%x doesn't match config\n", 534 ia->ia_iomem[0].ir_addr)); 535 goto out; 536 } 537 538 /* Need to put the 586 in RESET, and leave it */ 539 bus_space_write_1(iot, ioh, IX_ECTRL, IX_RESET_586); 540 541 /* Read the eeprom and checksum it, should == IX_ID */ 542 for (i = 0; i < 0x40; i++) 543 checksum += ix_read_eeprom(iot, ioh, i); 544 545 if (checksum != IX_ID) { 546 DPRINTF(("checksum mismatch (got 0x%04x, expected 0x%04x\n", 547 checksum, IX_ID)); 548 goto out; 549 } 550 551 /* 552 * Only do the following bit if using memory-mapped access. For 553 * boards with no mapped memory, we use PIO. We also use PIO for 554 * boards with 16K of mapped memory, as those setups don't seem 555 * to work otherwise. 556 */ 557 if (msiz != 0 && msiz != 16384) { 558 /* Set board up with memory-mapping info */ 559 adjust = IX_MCTRL_FMCS16 | (pg & 0x3) << 2; 560 decode = ((1 << (ia->ia_iomem[0].ir_size / 16384)) - 1) << pg; 561 edecode = ((~decode >> 4) & 0xF0) | (decode >> 8); 562 563 bus_space_write_1(iot, ioh, IX_MEMDEC, decode & 0xFF); 564 bus_space_write_1(iot, ioh, IX_MCTRL, adjust); 565 bus_space_write_1(iot, ioh, IX_MPCTRL, (~decode & 0xFF)); 566 567 /* XXX disable Exxx */ 568 bus_space_write_1(iot, ioh, IX_MECTRL, edecode); 569 } 570 571 /* 572 * Get the encoded interrupt number from the EEPROM, check it 573 * against the passed in IRQ. Issue a warning if they do not 574 * match, and fail the probe. If irq is 'ISA_UNKNOWN_IRQ' then we 575 * use the EEPROM irq, and continue. 576 */ 577 irq_encoded = ix_read_eeprom(iot, ioh, IX_EEPROM_CONFIG1); 578 irq_encoded = (irq_encoded & IX_EEPROM_IRQ) >> IX_EEPROM_IRQ_SHIFT; 579 irq = irq_translate[irq_encoded]; 580 if (ia->ia_irq[0].ir_irq != ISA_UNKNOWN_IRQ && 581 irq != ia->ia_irq[0].ir_irq) { 582 DPRINTF(("board IRQ %d does not match config\n", irq)); 583 goto out; 584 } 585 586 /* Disable the board interrupts */ 587 bus_space_write_1(iot, ioh, IX_IRQ, irq_encoded); 588 589 bart_config = bus_space_read_1(iot, ioh, IX_CONFIG); 590 bart_config |= IX_BART_LOOPBACK; 591 bart_config |= IX_BART_MCS16_TEST; /* inb doesn't get bit! */ 592 bus_space_write_1(iot, ioh, IX_CONFIG, bart_config); 593 bart_config = bus_space_read_1(iot, ioh, IX_CONFIG); 594 595 bus_space_write_1(iot, ioh, IX_ECTRL, 0); 596 delay(100); 597 598 rv = 1; 599 600 ia->ia_nio = 1; 601 ia->ia_io[0].ir_size = IX_IOSIZE; 602 603 ia->ia_niomem = 1; 604 ia->ia_iomem[0].ir_addr = maddr; 605 ia->ia_iomem[0].ir_size = msiz; 606 607 ia->ia_nirq = 1; 608 ia->ia_irq[0].ir_irq = irq; 609 610 DPRINTF(("ix_match: found board @ 0x%x\n", ia->ia_iomem[0].ir_addr)); 611 612out: 613 bus_space_unmap(iot, ioh, IX_IOSIZE); 614 return rv; 615} 616 617static void 618ix_attach(device_t parent, device_t self, void *aux) 619{ 620 struct ix_softc *isc = device_private(self); 621 struct ie_softc *sc = &isc->sc_ie; 622 struct isa_attach_args *ia = aux; 623 624 int media; 625 int i, memsize; 626 uint8_t bart_config; 627 bus_space_tag_t iot; 628 uint8_t bpat, bval; 629 uint16_t wpat, wval; 630 bus_space_handle_t ioh, memh; 631 uint16_t irq_encoded; 632 uint8_t ethaddr[ETHER_ADDR_LEN]; 633 634 sc->sc_dev = self; 635 iot = ia->ia_iot; 636 637 /* 638 * Shared memory access seems to fail on 16K mapped boards, so 639 * disable shared memory access if the board is in 16K mode. If 640 * no memory is mapped, we have no choice but to use PIO 641 */ 642 isc->use_pio = (ia->ia_iomem[0].ir_size <= (16 * 1024)); 643 644 if (bus_space_map(iot, ia->ia_io[0].ir_addr, 645 ia->ia_io[0].ir_size, 0, &ioh) != 0) { 646 647 DPRINTF(("\n%s: can't map i/o space 0x%x-0x%x\n", 648 device_xname(self), ia->ia_io[0].ir_addr, 649 ia->ia_io[0].ir_addr + ia->ia_io[0].ir_size - 1)); 650 return; 651 } 652 653 /* We map memory even if using PIO so something else doesn't grab it */ 654 if (ia->ia_iomem[0].ir_size) { 655 if (bus_space_map(ia->ia_memt, ia->ia_iomem[0].ir_addr, 656 ia->ia_iomem[0].ir_size, 0, &memh) != 0) { 657 DPRINTF(("\n%s: can't map iomem space 0x%x-0x%x\n", 658 device_xname(self), ia->ia_iomem[0].ir_addr, 659 ia->ia_iomem[0].ir_addr 660 + ia->ia_iomem[0].ir_size - 1)); 661 bus_space_unmap(iot, ioh, ia->ia_io[0].ir_size); 662 return; 663 } 664 } 665 666 isc->sc_regt = iot; 667 isc->sc_regh = ioh; 668 669 /* 670 * Get the hardware ethernet address from the EEPROM and 671 * save it in the softc for use by the 586 setup code. 672 */ 673 wval = ix_read_eeprom(iot, ioh, IX_EEPROM_ENET_HIGH); 674 ethaddr[1] = wval & 0xFF; 675 ethaddr[0] = wval >> 8; 676 wval = ix_read_eeprom(iot, ioh, IX_EEPROM_ENET_MID); 677 ethaddr[3] = wval & 0xFF; 678 ethaddr[2] = wval >> 8; 679 wval = ix_read_eeprom(iot, ioh, IX_EEPROM_ENET_LOW); 680 ethaddr[5] = wval & 0xFF; 681 ethaddr[4] = wval >> 8; 682 683 sc->hwinit = NULL; 684 sc->hwreset = ix_reset; 685 sc->chan_attn = ix_atten; 686 sc->intrhook = ix_intrhook; 687 688 sc->memcopyin = ix_copyin; 689 sc->memcopyout = ix_copyout; 690 691 sc->ie_bus_read16 = ix_read_16; 692 sc->ie_bus_write16 = ix_write_16; 693 sc->ie_bus_write24 = ix_write_24; 694 695 sc->do_xmitnopchain = 0; 696 697 sc->sc_mediachange = NULL; 698 sc->sc_mediastatus = ix_mediastatus; 699 700 if (isc->use_pio) { 701 sc->bt = iot; 702 sc->bh = ioh; 703 704 /* 705 * If using PIO, the memory size is bounded by on-card memory, 706 * not by how much is mapped into the memory-mapped region, so 707 * determine how much total memory we have to play with here. 708 */ 709 for (memsize = 64 * 1024; memsize; memsize -= 16 * 1024) { 710 /* warm up shared memory, the zero it all out */ 711 ix_zeromem(sc, 0, 32); 712 ix_zeromem(sc, 0, memsize); 713 714 /* Reset write pointer to the start of RAM */ 715 bus_space_write_2(iot, ioh, IX_WRITEPTR, 0); 716 717 /* Write test pattern */ 718 for (i = 0, wpat = 1; i < memsize; i += 2) { 719 bus_space_write_2(iot, ioh, IX_DATAPORT, wpat); 720 wpat += 3; 721 } 722 723 /* Reset read pointer to beginning of card RAM */ 724 bus_space_write_2(iot, ioh, IX_READPTR, 0); 725 726 /* Read and verify test pattern */ 727 for (i = 0, wpat = 1; i < memsize; i += 2) { 728 wval = bus_space_read_2(iot, ioh, IX_DATAPORT); 729 730 if (wval != wpat) 731 break; 732 733 wpat += 3; 734 } 735 736 /* If we failed, try next size down */ 737 if (i != memsize) 738 continue; 739 740 /* Now try it all with byte reads/writes */ 741 ix_zeromem(sc, 0, 32); 742 ix_zeromem(sc, 0, memsize); 743 744 /* Reset write pointer to start of card RAM */ 745 bus_space_write_2(iot, ioh, IX_WRITEPTR, 0); 746 747 /* Write out test pattern */ 748 for (i = 0, bpat = 1; i < memsize; i++) { 749 bus_space_write_1(iot, ioh, IX_DATAPORT, bpat); 750 bpat += 3; 751 } 752 753 /* Reset read pointer to beginning of card RAM */ 754 bus_space_write_2(iot, ioh, IX_READPTR, 0); 755 756 /* Read and verify test pattern */ 757 for (i = 0, bpat = 1; i < memsize; i++) { 758 bval = bus_space_read_1(iot, ioh, IX_DATAPORT); 759 760 if (bval != bpat) 761 bpat += 3; 762 } 763 764 /* If we got through all of memory, we're done! */ 765 if (i == memsize) 766 break; 767 } 768 769 /* Memory tests failed, punt... */ 770 if (memsize == 0) { 771 DPRINTF(("\n%s: can't determine size of on-card RAM\n", 772 device_xname(self))); 773 bus_space_unmap(iot, ioh, ia->ia_io[0].ir_size); 774 return; 775 } 776 777 sc->bt = iot; 778 sc->bh = ioh; 779 780 sc->sc_msize = memsize; 781 sc->sc_maddr = (void*)0; 782 } else { 783 sc->bt = ia->ia_memt; 784 sc->bh = memh; 785 786 sc->sc_msize = ia->ia_iomem[0].ir_size; 787 sc->sc_maddr = (void *)memh; 788 } 789 790 /* Map i/o space. */ 791 sc->sc_iobase = (char *)sc->sc_maddr + sc->sc_msize - (1 << 24); 792 793 /* Set up pointers to important on-card control structures */ 794 sc->iscp = 0; 795 sc->scb = IE_ISCP_SZ; 796 sc->scp = sc->sc_msize + IE_SCP_ADDR - (1 << 24); 797 798 sc->buf_area = sc->scb + IE_SCB_SZ; 799 sc->buf_area_sz = sc->sc_msize - IE_ISCP_SZ - IE_SCB_SZ - IE_SCP_SZ; 800 801 /* Zero card memory */ 802 ix_zeromem(sc, 0, 32); 803 ix_zeromem(sc, 0, sc->sc_msize); 804 805 /* Set card to 16-bit bus mode */ 806 if (isc->use_pio) { 807 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, 808 IE_SCP_BUS_USE((u_long)sc->scp)); 809 810 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, 811 IE_SYSBUS_16BIT); 812 } else 813 bus_space_write_1(sc->bt, sc->bh, 814 IE_SCP_BUS_USE((u_long)sc->scp), IE_SYSBUS_16BIT); 815 816 /* Set up pointers to key structures */ 817 ix_write_24(sc, IE_SCP_ISCP((u_long)sc->scp), (u_long)sc->iscp); 818 ix_write_16(sc, IE_ISCP_SCB((u_long)sc->iscp), (u_long)sc->scb); 819 ix_write_24(sc, IE_ISCP_BASE((u_long)sc->iscp), (u_long)sc->iscp); 820 821 /* Flush setup of pointers, check if chip answers */ 822 if (!i82586_proberam(sc)) { 823 DPRINTF(("\n%s: Can't talk to i82586!\n", 824 device_xname(self))); 825 bus_space_unmap(iot, ioh, ia->ia_io[0].ir_size); 826 827 if (ia->ia_iomem[0].ir_size) 828 bus_space_unmap(ia->ia_memt, memh, 829 ia->ia_iomem[0].ir_size); 830 return; 831 } 832 833 /* Figure out which media is being used... */ 834 if (ix_read_eeprom(iot, ioh, IX_EEPROM_CONFIG1) & 835 IX_EEPROM_MEDIA_EXT) { 836 if (ix_read_eeprom(iot, ioh, IX_EEPROM_MEDIA) & 837 IX_EEPROM_MEDIA_TP) 838 media = IFM_ETHER | IFM_10_T; 839 else 840 media = IFM_ETHER | IFM_10_2; 841 } else 842 media = IFM_ETHER | IFM_10_5; 843 844 /* Take the card out of loopback */ 845 bart_config = bus_space_read_1(iot, ioh, IX_CONFIG); 846 bart_config &= ~IX_BART_LOOPBACK; 847 bart_config |= IX_BART_MCS16_TEST; /* inb doesn't get bit! */ 848 bus_space_write_1(iot, ioh, IX_CONFIG, bart_config); 849 bart_config = bus_space_read_1(iot, ioh, IX_CONFIG); 850 851 irq_encoded = ix_read_eeprom(iot, ioh, IX_EEPROM_CONFIG1); 852 irq_encoded = (irq_encoded & IX_EEPROM_IRQ) >> IX_EEPROM_IRQ_SHIFT; 853 854 /* Enable interrupts */ 855 bus_space_write_1(iot, ioh, IX_IRQ, irq_encoded | IX_IRQ_ENABLE); 856 857 isc->irq_encoded = irq_encoded; 858 859 i82586_attach(sc, "EtherExpress/16", ethaddr, 860 ix_media, NIX_MEDIA, media); 861 862 if (isc->use_pio) 863 aprint_error_dev(self, "unsupported memory config, using PIO " 864 "to access %d bytes of memory\n", sc->sc_msize); 865 866 isc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq[0].ir_irq, 867 IST_EDGE, IPL_NET, i82586_intr, sc); 868 if (isc->sc_ih == NULL) { 869 DPRINTF(("\n%s: can't establish interrupt\n", 870 device_xname(self))); 871 } 872} 873 874CFATTACH_DECL_NEW(ix, sizeof(struct ix_softc), 875 ix_match, ix_attach, NULL, NULL); 876