essreg.h revision 1.1
1/* 2 * Copyright 1997 3 * Digital Equipment Corporation. All rights reserved. 4 * 5 * This software is furnished under license and may be used and 6 * copied only in accordance with the following terms and conditions. 7 * Subject to these conditions, you may download, copy, install, 8 * use, modify and distribute this software in source and/or binary 9 * form. No title or ownership is transferred hereby. 10 * 11 * 1) Any source code used, modified or distributed must reproduce 12 * and retain this copyright notice and list of conditions as 13 * they appear in the source file. 14 * 15 * 2) No right is granted to use any trade name, trademark, or logo of 16 * Digital Equipment Corporation. Neither the "Digital Equipment 17 * Corporation" name nor any trademark or logo of Digital Equipment 18 * Corporation may be used to endorse or promote products derived 19 * from this software without the prior written permission of 20 * Digital Equipment Corporation. 21 * 22 * 3) This software is provided "AS-IS" and any express or implied 23 * warranties, including but not limited to, any implied warranties 24 * of merchantability, fitness for a particular purpose, or 25 * non-infringement are disclaimed. In no event shall DIGITAL be 26 * liable for any damages whatsoever, and in particular, DIGITAL 27 * shall not be liable for special, indirect, consequential, or 28 * incidental damages or damages for lost profits, loss of 29 * revenue or loss of use, whether such damages arise in contract, 30 * negligence, tort, under statute, in equity, at law or otherwise, 31 * even if advised of the possibility of such damage. 32 */ 33 34/* 35** @(#) $RCSfile: essreg.h,v $ $Revision: 1.1 $ (SHARK) $Date: 1998/06/29 20:56:21 $ 36** 37**++ 38** 39** essreg.h 40** 41** FACILITY: 42** 43** DIGITAL Network Appliance Reference Design (DNARD) 44** 45** MODULE DESCRIPTION: 46** 47** This module contains the constant definitions for the device 48** registers on the ESS Technologies 1888/1887/888 sound chip. 49** 50** AUTHORS: 51** 52** Blair Fidler Software Engineering Australia 53** Gold Coast, Australia. 54** 55** CREATION DATE: 56** 57** March 10, 1997. 58** 59** MODIFICATION HISTORY: 60** 61**-- 62*/ 63 64/* 65 * DSP commands. This unit handles MIDI and audio capabilities. 66 * The DSP can be reset, data/commands can be read or written to it, 67 * and it can generate interrupts. Interrupts are generated for MIDI 68 * input or DMA completion. They seem to have neglected the fact 69 * that it would be nice to have a MIDI transmission complete interrupt. 70 * Worse, the DMA engine is half-duplex. This means you need to do 71 * (timed) programmed I/O to be able to record and play simulataneously. 72 */ 73#define ESS_ACMD_DAC8WRITE 0x10 /* direct-mode 8-bit DAC write */ 74#define ESS_ACMD_DAC16WRITE 0x11 /* direct-mode 16-bit DAC write */ 75#define ESS_ACMD_DMA8OUT 0x14 /* 8-bit linear DMA output */ 76#define ESS_ACMD_DMA16OUT 0x15 /* 16-bit linear DMA output */ 77#define ESS_ACMD_AUTODMA8OUT 0x1C /* auto-init 8-bit linear DMA output */ 78#define ESS_ACMD_AUTODMA16OUT 0x1D /* auto-init 16-bit linear DMA output */ 79#define ESS_ACMD_ADC8READ 0x20 /* direct-mode 8-bit ADC read */ 80#define ESS_ACMD_ADC16READ 0x21 /* direct-mode 16-bit ADC read */ 81#define ESS_ACMD_DMA8IN 0x24 /* 8-bit linear DMA input */ 82#define ESS_ACMD_DMA16IN 0x25 /* 16-bit linear DMA input */ 83#define ESS_ACMD_AUTODMA8IN 0x2C /* auto-init 8-bit linear DMA input */ 84#define ESS_ACMD_AUTODMA16IN 0x2D /* auto-init 16-bit linear DMA input */ 85#define ESS_ACMD_SETTIMECONST1 0x40 /* set time constant (1MHz base) */ 86#define ESS_ACMD_SETTIMECONST15 0x41 /* set time constant (1.5MHz base) */ 87#define ESS_ACMD_SETFILTER 0x42 /* set filter clock independently */ 88#define ESS_ACMD_BLOCKSIZE 0x48 /* set blk size for high speed xfer */ 89 90#define ESS_ACMD_DMA4OUT 0x74 /* 4-bit ADPCM DMA output */ 91#define ESS_ACMD_DMA4OUTREF 0x75 /* 4-bit ADPCM DMA output with ref */ 92#define ESS_ACMD_DMA2_6OUT 0x76 /* 2.6-bit ADPCM DMA output */ 93#define ESS_ACMD_DMA2_6OUTREF 0x77 /* 2.6-bit ADPCM DMA output with ref */ 94#define ESS_ACMD_DMA2OUT 0x7A /* 2-bit ADPCM DMA output */ 95#define ESS_ACMD_DMA2OUTREF 0x7B /* 2-bit ADPCM DMA output with ref */ 96#define ESS_ACMD_SILENCEOUT 0x80 /* output a block of silence */ 97#define ESS_ACMD_START_AUTO_OUT 0x90 /* start auto-init 8-bit DMA output */ 98#define ESS_ACMD_START_OUT 0x91 /* start 8-bit DMA output */ 99#define ESS_ACMD_START_AUTO_IN 0x98 /* start auto-init 8-bit DMA input */ 100#define ESS_ACMD_START_IN 0x99 /* start 8-bit DMA input */ 101 102#define ESS_XCMD_SAMPLE_RATE 0xA1 /* sample rate for Audio1 channel */ 103#define ESS_XCMD_FILTER_CLOCK 0xA2 /* filter clock for Audio1 channel*/ 104#define ESS_XCMD_XFER_COUNTLO 0xA4 /* */ 105#define ESS_XCMD_XFER_COUNTHI 0xA5 /* */ 106#define ESS_XCMD_AUDIO_CTRL 0xA8 /* */ 107#define ESS_AUDIO_CTRL_MONITOR 0x08 /* 0=disable/1=enable */ 108#define ESS_AUDIO_CTRL_MONO 0x02 /* 0=disable/1=enable */ 109#define ESS_AUDIO_CTRL_STEREO 0x01 /* 0=disable/1=enable */ 110#define ESS_XCMD_PREAMP_CTRL 0xA9 /* */ 111#define ESS_PREAMP_CTRL_ENABLE 0x04 112 113#define ESS_XCMD_IRQ_CTRL 0xB1 /* legacy audio interrupt control */ 114#define ESS_XCMD_DRQ_CTRL 0xB2 /* audio DRQ control */ 115#define ESS_XCMD_VOLIN_CTRL 0xB4 /* stereo input volume control */ 116#define ESS_XCMD_AUDIO1_CTRL1 0xB7 /* */ 117#define ESS_AUDIO1_CTRL1_FIFO_SIGNED 0x20 /* 0=unsigned/1=signed */ 118#define ESS_AUDIO1_CTRL1_FIFO_SIZE 0x04 /* 0=8-bit/1=16-bit */ 119#define ESS_XCMD_AUDIO1_CTRL2 0xB8 /* */ 120#define ESS_AUDIO1_CTRL2_FIFO_ENABLE 0x01 /* 0=disable/1=enable */ 121#define ESS_AUDIO1_CTRL2_DMA_READ 0x02 /* 0=DMA write/1=DMA read */ 122#define ESS_AUDIO1_CTRL2_ADC_ENABLE 0x08 /* 0=DAC mode/1=ADC mode */ 123#define ESS_XCMD_DEMAND_CTRL 0xB9 /* */ 124 125#define ESS_ACMD_ENABLE_EXT 0xC6 /* enable ESS extension commands */ 126#define ESS_ACMD_DISABLE_EXT 0xC7 /* enable ESS extension commands */ 127 128#define ESS_ACMD_PAUSE_DMA 0xD0 /* pause DMA */ 129#define ESS_ACMD_ENABLE_SPKR 0xD1 /* enable Audio1 DAC input to mixer */ 130#define ESS_ACMD_DISABLE_SPKR 0xD3 /* disable Audio1 DAC input to mixer */ 131#define ESS_ACMD_CONT_DMA 0xD4 /* continue paused DMA */ 132#define ESS_ACMD_SPKR_STATUS 0xD8 /* return Audio1 DAC status: */ 133#define ESS_SPKR_OFF 0x00 134#define ESS_SPKR_ON 0xFF 135#define ESS_ACMD_VERSION 0xE1 /* get version number */ 136#define ESS_ACMD_LEGACY_ID 0xE7 /* get legacy ES688/ES1688 ID bytes */ 137 138#define ESS_MINRATE 5000 /* XXX */ 139#define ESS_MAXRATE 50000 /* XXX */ 140 141/* 142 * Macros to detect valid hardware configuration data. 143 */ 144#define ESS_IRQ1_VALID(irq, model) ((irq) == 5 || (irq) == 7 || (irq) == 9 || (irq) == 10 || ((model) == ESS_1887 && (irq) == 15)) 145 146#define ESS_IRQ2_VALID(irq, model) (((model) != ESS_1887) ? ((irq) == 15) : ((irq) == 5 || (irq) == 7 || (irq) == 9 || (irq) == 10) || (irq) == 15) 147 148#define ESS_DRQ1_VALID(chan, model) ((chan) == 0 || (chan) == 1 || (chan) == 3 || ((model) == ESS_1887 && (chan) == 5)) 149 150#define ESS_DRQ2_VALID(chan, model) (((model) != ESS_1887) ? ((chan) == 5) : ((chan) == 0 || (chan) == 1 || (chan) == 3 || (chan) == 5)) 151 152#define ESS_BASE_VALID(base) ((base) == 0x220 || (base) == 0x230 || (base) == 0x240 || (base) == 0x250) 153 154#define ESS_DMA_SIZE(chan) ((chan & 4) ? ESS_MODE_16BIT: ESS_MODE_8BIT) 155 156/* 157 * Macros to manipulate gain values 158 */ 159#define ESS_4BIT_GAIN(x) ((x) & 0xf0) 160#define ESS_3BIT_GAIN(x) (((x) & 0xe0) >> 1) 161#define ESS_STEREO_GAIN(l, r) ((l) | ((r) >> 4)) 162#define ESS_MONO_GAIN(x) ((x) >> 4) 163 164#ifdef ESS_AMODE_LOW 165/* 166 * Registers used to configure ESS chip via Read Key Sequence 167 */ 168#define ESS_CONFIG_KEY_BASE 0x229 169#define ESS_CONFIG_KEY_PORTS 3 170#else 171/* 172 * Registers used to configure ESS chip via System Control Register (SCR) 173 */ 174#define ESS_SCR_ACCESS_BASE 0xF9 175#define ESS_SCR_ACCESS_PORTS 3 176#define ESS_SCR_LOCK 0 177#define ESS_SCR_UNLOCK 2 178 179#define ESS_SCR_BASE 0xE0 180#define ESS_SCR_PORTS 2 181#define ESS_SCR_INDEX 0 182#define ESS_SCR_DATA 1 183 184/* 185 * Bit definitions for SCR 186 */ 187#define ESS_SCR_AUDIO_ENABLE 0x04 188#define ESS_SCR_AUDIO_220 0x00 189#define ESS_SCR_AUDIO_230 0x01 190#define ESS_SCR_AUDIO_240 0x02 191#define ESS_SCR_AUDIO_250 0x03 192#endif 193 194/*****************************************************************************/ 195/* DSP Timeout Definitions */ 196/*****************************************************************************/ 197#define ESS_RESET_TIMEOUT 5000 /* ??? */ 198#define ESS_READ_TIMEOUT 5000 /* number of times to try a read */ 199#define ESS_WRITE_TIMEOUT 5000 /* number of times to try a write */ 200 201 202#define ESS_NPORT 16 203#define ESS_DSP_RESET 0x06 204#define ESS_MAGIC 0xAA /* response to successful reset */ 205 206#define ESS_DSP_READ 0x0A 207#define ESS_DSP_WRITE 0x0C 208 209#define ESS_DSP_RW_STATUS 0x0C 210#define ESS_CLEAR_INTR 0x0E 211 212#define ESS_DSP_READ_STATUS 0x0C 213#define ESS_DSP_READ_MASK 0x40 214#define ESS_DSP_READ_READY 0x40 215 216#define ESS_DSP_WRITE_STATUS 0x0C 217#define ESS_DSP_WRITE_MASK 0x80 218#define ESS_DSP_WRITE_READY 0x00 219 220 221#define ESS_MIX_REG_SELECT 0x04 222#define ESS_MIX_REG_DATA 0x05 223#define ESS_MIX_RESET 0x00 /* mixer reset port and value */ 224 225 226/* 227 * ESS Mixer registers 228 */ 229#define ESS_MREG_SAMPLE_RATE 0x70 /* sample rate for Audio2 channel */ 230#define ESS_MREG_FILTER_CLOCK 0x72 /* filter clock for Audio2 channel */ 231#define ESS_MREG_XFER_COUNTLO 0x74 /* low-byte of DMA transfer size */ 232#define ESS_MREG_XFER_COUNTHI 0x76 /* high-byte of DMA transfer size */ 233#define ESS_MREG_AUDIO2_CTRL1 0x78 /* control register 1 for Audio2: */ 234#define ESS_AUDIO2_CTRL1_XFER_SIZE 0x20 /* 0=8-bit/1=16-bit */ 235#define ESS_AUDIO2_CTRL1_FIFO_ENABLE 0x02 /* 0=disable/1=enable */ 236#define ESS_AUDIO2_CTRL1_DAC_ENABLE 0x01 /* 0=disable/1=enable */ 237#define ESS_MREG_AUDIO2_CTRL2 0x7A /* control register 2 for Audio2: */ 238#define ESS_AUDIO2_CTRL2_FIFO_SIZE 0x01 /* 0=8-bit/1=16-bit */ 239#define ESS_AUDIO2_CTRL2_CHANNELS 0x02 /* 0=mono/1=stereo */ 240#define ESS_AUDIO2_CTRL2_FIFO_SIGNED 0x04 /* 0=unsigned/1=signed */ 241#define ESS_AUDIO2_CTRL2_DMA_ENABLE 0x20 /* 0=disable/1=enable */ 242