1/* $NetBSD: essreg.h,v 1.18 2024/02/09 22:08:35 andvar Exp $ */ 2/* 3 * Copyright 1997 4 * Digital Equipment Corporation. All rights reserved. 5 * 6 * This software is furnished under license and may be used and 7 * copied only in accordance with the following terms and conditions. 8 * Subject to these conditions, you may download, copy, install, 9 * use, modify and distribute this software in source and/or binary 10 * form. No title or ownership is transferred hereby. 11 * 12 * 1) Any source code used, modified or distributed must reproduce 13 * and retain this copyright notice and list of conditions as 14 * they appear in the source file. 15 * 16 * 2) No right is granted to use any trade name, trademark, or logo of 17 * Digital Equipment Corporation. Neither the "Digital Equipment 18 * Corporation" name nor any trademark or logo of Digital Equipment 19 * Corporation may be used to endorse or promote products derived 20 * from this software without the prior written permission of 21 * Digital Equipment Corporation. 22 * 23 * 3) This software is provided "AS-IS" and any express or implied 24 * warranties, including but not limited to, any implied warranties 25 * of merchantability, fitness for a particular purpose, or 26 * non-infringement are disclaimed. In no event shall DIGITAL be 27 * liable for any damages whatsoever, and in particular, DIGITAL 28 * shall not be liable for special, indirect, consequential, or 29 * incidental damages or damages for lost profits, loss of 30 * revenue or loss of use, whether such damages arise in contract, 31 * negligence, tort, under statute, in equity, at law or otherwise, 32 * even if advised of the possibility of such damage. 33 */ 34 35/* 36** @(#) $RCSfile: essreg.h,v $ $Revision: 1.18 $ (SHARK) $Date: 2024/02/09 22:08:35 $ 37** 38**++ 39** 40** essreg.h 41** 42** FACILITY: 43** 44** DIGITAL Network Appliance Reference Design (DNARD) 45** 46** MODULE DESCRIPTION: 47** 48** This module contains the constant definitions for the device 49** registers on the ESS Technologies 1888/1887/888 sound chip. 50** 51** AUTHORS: 52** 53** Blair Fidler Software Engineering Australia 54** Gold Coast, Australia. 55** 56** CREATION DATE: 57** 58** March 10, 1997. 59** 60** MODIFICATION HISTORY: 61** 62**-- 63*/ 64 65/* 66 * DSP commands. This unit handles MIDI and audio capabilities. 67 * The DSP can be reset, data/commands can be read or written to it, 68 * and it can generate interrupts. Interrupts are generated for MIDI 69 * input or DMA completion. They seem to have neglected the fact 70 * that it would be nice to have a MIDI transmission complete interrupt. 71 * Worse, the DMA engine is half-duplex. This means you need to do 72 * (timed) programmed I/O to be able to record and play simultaneously. 73 */ 74#define ESS_ACMD_DAC8WRITE 0x10 /* direct-mode 8-bit DAC write */ 75#define ESS_ACMD_DAC16WRITE 0x11 /* direct-mode 16-bit DAC write */ 76#define ESS_ACMD_DMA8OUT 0x14 /* 8-bit linear DMA output */ 77#define ESS_ACMD_DMA16OUT 0x15 /* 16-bit linear DMA output */ 78#define ESS_ACMD_AUTODMA8OUT 0x1C /* auto-init 8-bit linear DMA output */ 79#define ESS_ACMD_AUTODMA16OUT 0x1D /* auto-init 16-bit linear DMA output */ 80#define ESS_ACMD_ADC8READ 0x20 /* direct-mode 8-bit ADC read */ 81#define ESS_ACMD_ADC16READ 0x21 /* direct-mode 16-bit ADC read */ 82#define ESS_ACMD_DMA8IN 0x24 /* 8-bit linear DMA input */ 83#define ESS_ACMD_DMA16IN 0x25 /* 16-bit linear DMA input */ 84#define ESS_ACMD_AUTODMA8IN 0x2C /* auto-init 8-bit linear DMA input */ 85#define ESS_ACMD_AUTODMA16IN 0x2D /* auto-init 16-bit linear DMA input */ 86#define ESS_ACMD_SETTIMECONST1 0x40 /* set time constant (1MHz base) */ 87#define ESS_ACMD_SETTIMECONST15 0x41 /* set time constant (1.5MHz base) */ 88#define ESS_ACMD_SETFILTER 0x42 /* set filter clock independently */ 89#define ESS_ACMD_BLOCKSIZE 0x48 /* set blk size for high speed xfer */ 90 91#define ESS_ACMD_DMA4OUT 0x74 /* 4-bit ADPCM DMA output */ 92#define ESS_ACMD_DMA4OUTREF 0x75 /* 4-bit ADPCM DMA output with ref */ 93#define ESS_ACMD_DMA2_6OUT 0x76 /* 2.6-bit ADPCM DMA output */ 94#define ESS_ACMD_DMA2_6OUTREF 0x77 /* 2.6-bit ADPCM DMA output with ref */ 95#define ESS_ACMD_DMA2OUT 0x7A /* 2-bit ADPCM DMA output */ 96#define ESS_ACMD_DMA2OUTREF 0x7B /* 2-bit ADPCM DMA output with ref */ 97#define ESS_ACMD_SILENCEOUT 0x80 /* output a block of silence */ 98#define ESS_ACMD_START_AUTO_OUT 0x90 /* start auto-init 8-bit DMA output */ 99#define ESS_ACMD_START_OUT 0x91 /* start 8-bit DMA output */ 100#define ESS_ACMD_START_AUTO_IN 0x98 /* start auto-init 8-bit DMA input */ 101#define ESS_ACMD_START_IN 0x99 /* start 8-bit DMA input */ 102 103#define ESS_XCMD_SAMPLE_RATE 0xA1 /* sample rate for Audio1 channel */ 104#define ESS_XCMD_FILTER_CLOCK 0xA2 /* filter clock for Audio1 channel*/ 105#define ESS_XCMD_XFER_COUNTLO 0xA4 /* */ 106#define ESS_XCMD_XFER_COUNTHI 0xA5 /* */ 107#define ESS_XCMD_AUDIO_CTRL 0xA8 /* */ 108#define ESS_AUDIO_CTRL_MONITOR 0x08 /* 0=disable/1=enable */ 109#define ESS_AUDIO_CTRL_MONO 0x02 /* 0=disable/1=enable */ 110#define ESS_AUDIO_CTRL_STEREO 0x01 /* 0=disable/1=enable */ 111#define ESS_XCMD_PREAMP_CTRL 0xA9 /* */ 112#define ESS_PREAMP_CTRL_ENABLE 0x04 113 114#define ESS_XCMD_IRQ_CTRL 0xB1 /* legacy audio interrupt control */ 115#define ESS_IRQ_CTRL_INTRA 0x00 116#define ESS_IRQ_CTRL_INTRB 0x04 117#define ESS_IRQ_CTRL_INTRC 0x08 118#define ESS_IRQ_CTRL_INTRD 0x0C 119#define ESS_IRQ_CTRL_MASK 0x10 120#define ESS_IRQ_CTRL_EXT 0x40 121#define ESS_XCMD_DRQ_CTRL 0xB2 /* audio DRQ control */ 122#define ESS_DRQ_CTRL_DRQA 0x04 123#define ESS_DRQ_CTRL_DRQB 0x08 124#define ESS_DRQ_CTRL_DRQC 0x0C 125#define ESS_DRQ_CTRL_PU 0x10 126#define ESS_DRQ_CTRL_EXT 0x40 127#define ESS_XCMD_VOLIN_CTRL 0xB4 /* stereo input volume control */ 128#define ESS_1788_XCMD_AUDIO_CTRL0 0xB6 129#define ESS_CTRL0_SIGNED 0x00 130#define ESS_CTRL0_UNSIGNED 0x80 131#define ESS_XCMD_AUDIO1_CTRL1 0xB7 /* */ 132#define ESS_AUDIO1_CTRL1_FIFO_CONNECT 0x80 /* 1=connected */ 133#define ESS_AUDIO1_CTRL1_FIFO_MONO 0x40 /* 0=stereo/1=mono */ 134#define ESS_AUDIO1_CTRL1_FIFO_SIGNED 0x20 /* 0=unsigned/1=signed */ 135#define ESS_AUDIO1_CTRL1_FIFO_STEREO 0x08 /* 0=mono/1=stereo */ 136#define ESS_AUDIO1_CTRL1_FIFO_SIZE 0x04 /* 0=8-bit/1=16-bit */ 137#define ESS_XCMD_AUDIO1_CTRL2 0xB8 /* */ 138#define ESS_AUDIO1_CTRL2_FIFO_ENABLE 0x01 /* 0=disable/1=enable */ 139#define ESS_AUDIO1_CTRL2_DMA_READ 0x02 /* 0=DMA write/1=DMA read */ 140#define ESS_AUDIO1_CTRL2_AUTO_INIT 0x04 141#define ESS_AUDIO1_CTRL2_ADC_ENABLE 0x08 /* 0=DAC mode/1=ADC mode */ 142#define ESS_XCMD_DEMAND_CTRL 0xB9 /* */ 143#define ESS_DEMAND_CTRL_SINGLE 0x00 /* 1-byte transfers */ 144#define ESS_DEMAND_CTRL_DEMAND_2 0x01 /* 2-byte transfers */ 145#define ESS_DEMAND_CTRL_DEMAND_4 0x02 /* 4-byte transfers */ 146 147#define ESS_ACMD_ENABLE_EXT 0xC6 /* enable ESS extension commands */ 148#define ESS_ACMD_DISABLE_EXT 0xC7 /* enable ESS extension commands */ 149 150#define ESS_ACMD_PAUSE_DMA 0xD0 /* pause DMA */ 151#define ESS_ACMD_ENABLE_SPKR 0xD1 /* enable Audio1 DAC input to mixer */ 152#define ESS_ACMD_DISABLE_SPKR 0xD3 /* disable Audio1 DAC input to mixer */ 153#define ESS_ACMD_CONT_DMA 0xD4 /* continue paused DMA */ 154#define ESS_ACMD_SPKR_STATUS 0xD8 /* return Audio1 DAC status: */ 155#define ESS_SPKR_OFF 0x00 156#define ESS_SPKR_ON 0xFF 157#define ESS_ACMD_VERSION 0xE1 /* get version number */ 158#define ESS_ACMD_LEGACY_ID 0xE7 /* get legacy ES688/ES1688 ID bytes */ 159 160#define ESS_MINRATE 4000 161#define ESS_MAXRATE 44100 162 163/* 164 * Macros to detect valid hardware configuration data. 165 */ 166#define ESS_BASE_VALID(base) ((base) == 0x220 || (base) == 0x230 || (base) == 0x240 || (base) == 0x250) 167 168#define ESS_IRQ1_VALID(irq) ((irq) == 5 || (irq) == 7 || (irq) == 9 || (irq) == 10) 169 170#define ESS_IRQ2_VALID(irq) ((irq) == 15) 171 172#define ESS_IRQ12_VALID(irq) ((irq) == 5 || (irq) == 7 || (irq) == 9 || (irq) == 10 || (irq) == 15) 173 174#define ESS_DRQ1_VALID(chan) ((chan) == 0 || (chan) == 1 || (chan) == 3) 175 176#define ESS_DRQ2_VALID(chan) ((chan) == 0 || (chan) == 1 || (chan) == 3 || (chan) == 5) 177 178#define ESS_USE_AUDIO1(model) ((model) <= ESS_1879) 179#define ESS_IS_ES18X9(model) (((model) == ESS_1869) || ((model) == ESS_1879)) 180 181/* 182 * Macros to manipulate gain values 183 */ 184#define ESS_6BIT_GAIN(x) ((x) & 0xfc) 185#define ESS_4BIT_GAIN(x) ((x) & 0xf0) 186#define ESS_3BIT_GAIN(x) (((x) & 0xe0) >> 1) 187#define ESS_STEREO_GAIN(l, r) ((l) | ((r) >> 4)) 188#define ESS_MONO_GAIN(x) ((x) >> 4) 189#define ESS_SPATIAL_GAIN(x) ((x) >> 2) 190 191#ifdef ESS_AMODE_LOW 192/* 193 * Registers used to configure ESS chip via Read Key Sequence 194 */ 195#define ESS_CONFIG_KEY_BASE 0x229 196#define ESS_CONFIG_KEY_PORTS 3 197#else 198/* 199 * Registers used to configure ESS chip via System Control Register (SCR) 200 */ 201#define ESS_SCR_ACCESS_BASE 0xF9 202#define ESS_SCR_ACCESS_PORTS 3 203#define ESS_SCR_LOCK 0 204#define ESS_SCR_UNLOCK 2 205 206#define ESS_SCR_BASE 0xE0 207#define ESS_SCR_PORTS 2 208#define ESS_SCR_INDEX 0 209#define ESS_SCR_DATA 1 210 211/* 212 * Bit definitions for SCR 213 */ 214#define ESS_SCR_AUDIO_ENABLE 0x04 215#define ESS_SCR_AUDIO_220 0x00 216#define ESS_SCR_AUDIO_230 0x01 217#define ESS_SCR_AUDIO_240 0x02 218#define ESS_SCR_AUDIO_250 0x03 219#endif 220 221/*****************************************************************************/ 222/* DSP Timeout Definitions */ 223/*****************************************************************************/ 224#define ESS_READ_TIMEOUT 5000 /* number of times to try a read, 5ms*/ 225#define ESS_WRITE_TIMEOUT 5000 /* number of times to try a write, 5ms */ 226 227 228#define ESS_NPORT 16 229#define ESS_DSP_RESET 0x06 230#define ESS_RESET_EXT 0x03 /* reset and use second DMA */ 231#define ESS_MAGIC 0xAA /* response to successful reset */ 232 233#define ESS_DSP_READ 0x0A 234#define ESS_DSP_WRITE 0x0C 235 236#define ESS_CLEAR_INTR 0x0E 237 238#define ESS_FIFO_WRITE 0x0F 239 240#define ESS_DSP_RW_STATUS 0x0C 241#define ESS_DSP_WRITE_BUSY 0x80 242#define ESS_DSP_READ_READY 0x40 243#define ESS_DSP_READ_FULL 0x20 /* FIFO full */ 244#define ESS_DSP_READ_EMPTY 0x10 /* FIFO empty */ 245#define ESS_DSP_READ_HALF 0x08 /* FIFO half-empty */ 246#define ESS_DSP_READ_IRQ 0x04 /* IRQ generated */ 247#define ESS_DSP_READ_HALF_IRQ 0x02 /* " from half-empty flag change */ 248#define ESS_DSP_READ_OFLOW 0x01 /* " from DMA counter overflow */ 249#define ESS_DSP_READ_ANYIRQ (ESS_DSP_READ_IRQ | \ 250 ESS_DSP_READ_HALF_IRQ | \ 251 ESS_DSP_READ_OFLOW) 252 253#define ESS_MIX_REG_SELECT 0x04 254#define ESS_MIX_REG_DATA 0x05 255#define ESS_MIX_RESET 0x00 /* mixer reset port and value */ 256 257 258/* 259 * ESS Mixer registers 260 */ 261#define ESS_MREG_VOLUME_VOICE 0x14 262#define ESS_MREG_VOLUME_MIC 0x1A 263#define ESS_MREG_ADC_SOURCE 0x1C 264#define ESS_SOURCE_MIC 0x00 265#define ESS_SOURCE_CD 0x02 266#define ESS_SOURCE_LINE 0x06 267#define ESS_SOURCE_MIXER 0x07 268#define ESS_MREG_VOLUME_MASTER 0x32 269#define ESS_MREG_VOLUME_SYNTH 0x36 270#define ESS_MREG_VOLUME_CD 0x38 271#define ESS_MREG_VOLUME_AUXB 0x3A 272#define ESS_MREG_VOLUME_PCSPKR 0x3C 273#define ESS_MREG_VOLUME_LINE 0x3E 274#define ESS_MREG_SPATIAL_CTRL 0x50 275#define ESS_SPATIAL_CTRL_MONO 0x02 276#define ESS_SPATIAL_CTRL_RESET 0x04 277#define ESS_SPATIAL_CTRL_ENABLE 0x08 278#define ESS_MREG_SPATIAL_LEVEL 0x52 279#define ESS_MREG_VOLUME_LEFT 0x60 280#define ESS_MREG_VOLUME_RIGHT 0x62 281#define ESS_VOLUME_MUTE 0x40 282#define ESS_MREG_VOLUME_CTRL 0x64 283#define ESS_MREG_SAMPLE_RATE 0x70 /* sample rate for Audio2 channel */ 284#define ESS_MREG_MODE 0x71 /* mode for Audio2 channel */ 285#define ESS_MODE_FM_MIX 0x01 286#define ESS_MODE_ASYNC_MODE 0x02 287#define ESS_MODE_SCF1_BYPASS 0x04 288#define ESS_MODE_SCF2_BYPASS 0x08 289#define ESS_MODE_4X_MODE 0x10 290#define ESS_MODE_NEWREG 0x20 291#define ESS_MREG_FILTER_CLOCK 0x72 /* filter clock for Audio2 channel */ 292#define ESS_MREG_XFER_COUNTLO 0x74 /* low-byte of DMA transfer size */ 293#define ESS_MREG_XFER_COUNTHI 0x76 /* high-byte of DMA transfer size */ 294#define ESS_MREG_AUDIO2_CTRL1 0x78 /* control register 1 for Audio2: */ 295#define ESS_AUDIO2_CTRL1_SINGLE 0x00 296#define ESS_AUDIO2_CTRL1_DEMAND_2 0x40 297#define ESS_AUDIO2_CTRL1_DEMAND_4 0x80 298#define ESS_AUDIO2_CTRL1_DEMAND_8 0xC0 299#define ESS_AUDIO2_CTRL1_XFER_SIZE 0x20 /* 0=8-bit/1=16-bit */ 300#define ESS_AUDIO2_CTRL1_AUTO_INIT 0x10 301#define ESS_AUDIO2_CTRL1_FIFO_ENABLE 0x02 /* 0=disable/1=enable */ 302#define ESS_AUDIO2_CTRL1_DAC_ENABLE 0x01 /* 0=disable/1=enable */ 303#define ESS_MREG_AUDIO2_CTRL2 0x7A /* control register 2 for Audio2: */ 304#define ESS_AUDIO2_CTRL2_FIFO_SIZE 0x01 /* 0=8-bit/1=16-bit */ 305#define ESS_AUDIO2_CTRL2_CHANNELS 0x02 /* 0=mono/1=stereo */ 306#define ESS_AUDIO2_CTRL2_FIFO_SIGNED 0x04 /* 0=unsigned/1=signed */ 307#define ESS_AUDIO2_CTRL2_DMA_ENABLE 0x20 /* 0=disable/1=enable */ 308#define ESS_AUDIO2_CTRL2_IRQ2_ENABLE 0x40 309#define ESS_AUDIO2_CTRL2_IRQ_LATCH 0x80 310#define ESS_MREG_AUDIO2_CTRL3 0x7D 311#define ESS_AUDIO2_CTRL3_DRQA 0x00 312#define ESS_AUDIO2_CTRL3_DRQB 0x01 313#define ESS_AUDIO2_CTRL3_DRQC 0x02 314#define ESS_AUDIO2_CTRL3_DRQD 0x03 315#define ESS_AUDIO2_CTRL3_DRQ_PD 0x04 316#define ESS_MREG_INTR_ST 0x7F 317#define ESS_IS_SELECT_IRQ 0x01 318#define ESS_IS_ES1888 0x00 319#define ESS_IS_INTRA 0x02 320#define ESS_IS_INTRB 0x04 321#define ESS_IS_INTRC 0x06 322#define ESS_IS_INTRD 0x08 323#define ESS_IS_INTRE 0x0A 324