1/* $NetBSD: mfireg.h,v 1.25 2024/02/13 14:56:52 msaitoh Exp $ */ 2/* $OpenBSD: mfireg.h,v 1.24 2006/06/19 19:05:45 marco Exp $ */ 3/* 4 * Copyright (c) 2006 Marco Peereboom <marco@peereboom.us> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19/*- 20 * Copyright (c) 2007 LSI Corp. 21 * Copyright (c) 2007 Rajesh Prabhakaran. 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 36 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 43 * SUCH DAMAGE. 44 */ 45 46#ifndef _DEV_IC_MFIREG_H_ 47#define _DEV_IC_MFIREG_H_ 48 49/* management interface constants */ 50#define MFI_MGMT_VD 0x01 51#define MFI_MGMT_SD 0x02 52 53/* generic constants */ 54#define MFI_FRAME_SIZE 64 55#define MFI_SENSE_SIZE 128 56#define MFI_OSTS_INTR_VALID 0x00000002 /* valid interrupt */ 57#define MFI_OSTS_PPC_INTR_VALID 0x80000000 58#define MFI_OSTS_GEN2_INTR_VALID (0x00000001 | 0x00000004) 59#define MFI_INVALID_CTX 0xffffffff 60#define MFI_ENABLE_INTR 0x01 61#define MFI_MAXFER MAXPHYS /* XXX bogus */ 62#define MFI_SECTOR_LEN 512 63 64/* register offsets */ 65#define MFI_IMSG0 0x10 /* inbound msg 0 */ 66#define MFI_IMSG1 0x14 /* inbound msg 1 */ 67#define MFI_OMSG0 0x18 /* outbound msg 0 */ 68#define MFI_OMSG1 0x1c /* outbound msg 1 */ 69#define MFI_IDB 0x20 /* inbound doorbell */ 70#define MFI_ISTS 0x24 /* inbound intr stat */ 71#define MFI_IMSK 0x28 /* inbound intr mask */ 72#define MFI_ODB 0x2c /* outbound doorbell */ 73#define MFI_OSTS 0x30 /* outbound intr stat */ 74#define MFI_OMSK 0x34 /* outbound inter mask */ 75#define MFI_IQP 0x40 /* inbound queue port */ 76#define MFI_OQP 0x44 /* outbound queue port */ 77#define MFI_ODC 0xa0 /* outbound doorbell clr */ 78#define MFI_OSP 0xb0 /* outbound scratch pad */ 79 80/* ThunderBolt specific Register */ 81#define MFI_RPI 0x6c /* reply_post_host_index */ 82#define MFI_ILQP 0xc0 /* inbound_low_queue_port */ 83#define MFI_IHQP 0xc4 /* inbound_high_queue_port */ 84 85/* Aero specific Register */ 86#define MFI_ISQP 0xc8 /* inbound_single_queue_port */ 87 88/* OCR registers */ 89#define MFI_WSR 0x004 /* write sequence register */ 90#define MFI_HDR 0x008 /* host diagnostic register */ 91#define MFI_RSR 0x3c3 /* Reset Status Register */ 92 93/* OCR specific flags */ 94#define MFI_FIRMWARE_STATE_CHANGE 0x00000002 95#define MFI_STATE_CHANGE_INTERRUPT 0x00000004 96 97/* 98 * skinny specific changes 99*/ 100#define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */ 101#define MFI_IQPL 0x000000c0 102#define MFI_IQPH 0x000000c4 103#define MFI_OSTS_SKINNY_INTR_VALID 0x00000001 104 105/* * firmware states */ 106#define MFI_STATE_MASK 0xf0000000 107#define MFI_STATE_UNDEFINED 0x00000000 108#define MFI_STATE_BB_INIT 0x10000000 109#define MFI_STATE_FW_INIT 0x40000000 110#define MFI_STATE_WAIT_HANDSHAKE 0x60000000 111#define MFI_STATE_FW_INIT_2 0x70000000 112#define MFI_STATE_DEVICE_SCAN 0x80000000 113#define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 114#define MFI_STATE_FLUSH_CACHE 0xa0000000 115#define MFI_STATE_READY 0xb0000000 116#define MFI_STATE_OPERATIONAL 0xc0000000 117#define MFI_STATE_FAULT 0xf0000000 118#define MFI_STATE_MAXSGL_MASK 0x00ff0000 119#define MFI_STATE_MAXCMD_MASK 0x0000ffff 120#define MFI_STATE_HOSTMEMREQD_MASK 0x08000000 121#define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 122#define MFI_RESET_REQUIRED 0x00000001 123 124/* ThunderBolt Support */ 125#define MFI_STATE_TB_MASK 0xf0000000 126#define MFI_STATE_TB_RESET 0x00000000 127#define MFI_STATE_TB_READY 0x10000000 128#define MFI_STATE_TB_OPERATIONAL 0x20000000 129#define MFI_STATE_TB_FAULT 0x40000000 130 131/* Aero Support */ 132#define MFI_STATE_ATOMIC_DESCRIPTOR 0x01000000 133 134/* command reset register */ 135#define MFI_INIT_ABORT 0x00000001 136#define MFI_INIT_READY 0x00000002 137#define MFI_INIT_MFIMODE 0x00000004 138#define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 139#define MFI_INIT_HOTPLUG 0x00000010 140#define MFI_RESET_FLAGS MFI_INIT_READY | MFI_INIT_MFIMODE | \ 141 MFI_INIT_ABORT 142#define MFI_INIT_HOTPLUG 0x00000010 143 144/* ADP reset flags */ 145#define MFI_STOP_ADP 0x00000020 146#define MFI_ADP_RESET 0x00000040 147#define DIAG_WRITE_ENABLE 0x00000080 148#define DIAG_RESET_ADAPTER 0x00000004 149 150/* mfi Frame flags */ 151#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 152#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 153#define MFI_FRAME_SGL32 0x0000 154#define MFI_FRAME_SGL64 0x0002 155#define MFI_FRAME_SENSE32 0x0000 156#define MFI_FRAME_SENSE64 0x0004 157#define MFI_FRAME_DIR_NONE 0x0000 158#define MFI_FRAME_DIR_WRITE 0x0008 159#define MFI_FRAME_DIR_READ 0x0010 160#define MFI_FRAME_DIR_BOTH 0x0018 161#define MFI_FRAME_IEEE_SGL 0x0020 162 163/* ThunderBolt Specific */ 164 165/* 166 * Pre-TB command size and TB command size. 167 * We will be checking it at the load time for the time being 168 */ 169#define MR_COMMAND_SIZE (MFI_FRAME_SIZE*20) /* 1280 bytes */ 170 171#define MEGASAS_THUNDERBOLT_MSG_ALIGNMENT 256 172/* 173 * We are defining only 128 byte message to reduce memory move over head 174 * and also it will reduce the SRB extension size by 128byte compared with 175 * 256 message size 176 */ 177#define MEGASAS_THUNDERBOLT_NEW_MSG_SIZE 256 178#define MEGASAS_THUNDERBOLT_MAX_COMMANDS 1024 179#define MEGASAS_THUNDERBOLT_MAX_REPLY_COUNT 1024 180#define MEGASAS_THUNDERBOLT_REPLY_SIZE 8 181#define MEGASAS_THUNDERBOLT_MAX_CHAIN_COUNT 1 182#define MEGASAS_MAX_SZ_CHAIN_FRAME 1024 183 184/* 185 * Calculating how many SGEs allowed in an allocated main message 186 * (size of the Message - Raid SCSI IO message size(except SGE)) 187 * / size of SGE 188 * (0x100 - (0x90 - 0x10)) / 0x10 = 8 189 */ 190#define MEGASAS_THUNDERBOLT_MAX_SGE_IN_MAINMSG \ 191 ((MEGASAS_THUNDERBOLT_NEW_MSG_SIZE - \ 192 (sizeof(struct mfi_mpi2_request_raid_scsi_io) - sizeof(mpi2_sge_io_union))\ 193 ) / sizeof(mpi2_sge_io_union)) 194 195/* 196 * (Command frame size allocated in SRB ext - Raid SCSI IO message size) 197 * / size of SGL ; 198 * (1280 - 256) / 16 = 64 199 */ 200#define MEGASAS_THUNDERBOLT_MAX_SGE_IN_CHAINMSG \ 201 ((MR_COMMAND_SIZE - MEGASAS_THUNDERBOLT_NEW_MSG_SIZE) / \ 202 sizeof(mpi2_sge_io_union)) 203 204/* 205 * This is the offset in number of 4 * 32bit words to the next chain 206 * (0x100 - 0x10)/0x10 = 0xF(15) 207 */ 208#define MEGASAS_THUNDERBOLT_CHAIN_OFF_MAINMSG \ 209 ((MEGASAS_THUNDERBOLT_NEW_MSG_SIZE - sizeof(mpi2_sge_io_union)) / 16) 210 211#define MEGASAS_THUNDERBOLT_CHAIN_OFF_MPT_PTMSG \ 212 (offsetof(struct mfi_mpi2_request_raid_scsi_io, SGL) / 16) 213 214#define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 215#define MPI2_FUNCTION_LD_IO_REQUEST 0xF1 216 217#define MR_INTERNAL_MFI_FRAMES_SMID 1 218#define MR_CTRL_EVENT_WAIT_SMID 2 219#define MR_INTERNAL_DRIVER_RESET_SMID 3 220 221/* mfi command opcodes */ 222#define MFI_CMD_INIT 0x00 223#define MFI_CMD_LD_READ 0x01 224#define MFI_CMD_LD_WRITE 0x02 225#define MFI_CMD_LD_SCSI_IO 0x03 226#define MFI_CMD_PD_SCSI_IO 0x04 227#define MFI_CMD_DCMD 0x05 228#define MFI_CMD_ABORT 0x06 229#define MFI_CMD_SMP 0x07 230#define MFI_CMD_STP 0x08 231 232/* direct commands */ 233#define MR_DCMD_CTRL_GET_INFO 0x01010000 234#define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 235#define MR_FLUSH_CTRL_CACHE 0x01 236#define MR_FLUSH_DISK_CACHE 0x02 237#define MR_DCMD_CTRL_HOST_MEM_ALLOC 0x0100e100 238#define MR_DCMD_CTRL_SHUTDOWN 0x01050000 239#define MR_ENABLE_DRIVE_SPINDOWN 0x01 240#define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 241#define MR_DCMD_CTRL_EVENT_GET 0x01040300 242#define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 243#define MR_DCMD_PD_GET_LIST 0x02010000 244#define MR_DCMD_PD_LIST_QUERY 0x02010100 245#define MR_DCMD_PD_GET_INFO 0x02020000 246#define MR_DCMD_PD_SET_STATE 0x02030100 247#define MR_DCMD_PD_REBUILD 0x02040100 248#define MR_DCMD_PD_BLINK 0x02070100 249#define MR_DCMD_PD_UNBLINK 0x02070200 250#define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 251#define MR_DCMD_LD_SYNC 0x0300e102 252#define MR_DCMD_LD_GET_LIST 0x03010000 253#define MR_DCMD_LD_GET_INFO 0x03020000 254#define MR_DCMD_LD_GET_PROPERTIES 0x03030000 255#define MR_DCMD_CONF_GET 0x04010000 256#define MR_DCMD_CFG_ADD 0x04020000 257#define MR_DCMD_CFG_CLEAR 0x04030000 258#define MR_DCMD_CFG_MAKE_SPARE 0x04040000 259#define MR_DCMD_CFG_FOREIGN_SCAN 0x04060100 260#define MR_DCMD_CFG_FOREIGN_CLEAR 0x04060500 261#define MR_DCMD_BBU_GET_STATUS 0x05010000 262#define MR_DCMD_BBU_GET_CAPACITY_INFO 0x05020000 263#define MR_DCMD_BBU_GET_DESIGN_INFO 0x05030000 264#define MR_DCMD_CLUSTER 0x08000000 265#define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 266#define MR_DCMD_CLUSTER_RESET_LD 0x08010200 267 268#define MR_DCMD_SPEAKER_GET 0x01030100 269#define MR_DCMD_SPEAKER_ENABLE 0x01030200 270#define MR_DCMD_SPEAKER_DISABLE 0x01030300 271#define MR_DCMD_SPEAKER_SILENCE 0x01030400 272#define MR_DCMD_SPEAKER_TEST 0x01030500 273 274/* mailbox bytes in direct command */ 275#define MFI_MBOX_SIZE 12 276 277union mfi_mbox { 278 uint8_t b[MFI_MBOX_SIZE]; 279 uint16_t s[6]; 280 uint32_t w[3]; 281}; 282 283/* mfi completion codes */ 284typedef enum { 285 MFI_STAT_OK = 0x00, 286 MFI_STAT_INVALID_CMD = 0x01, 287 MFI_STAT_INVALID_DCMD = 0x02, 288 MFI_STAT_INVALID_PARAMETER = 0x03, 289 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 290 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 291 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 292 MFI_STAT_APP_IN_USE = 0x07, 293 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 294 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 295 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 296 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 297 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 298 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 299 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 300 MFI_STAT_FLASH_BUSY = 0x0f, 301 MFI_STAT_FLASH_ERROR = 0x10, 302 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 303 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 304 MFI_STAT_FLASH_NOT_OPEN = 0x13, 305 MFI_STAT_FLASH_NOT_STARTED = 0x14, 306 MFI_STAT_FLUSH_FAILED = 0x15, 307 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 308 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 309 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 310 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 311 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 312 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 313 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 314 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 315 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 316 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 317 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 318 MFI_STAT_MFC_HW_ERROR = 0x21, 319 MFI_STAT_NO_HW_PRESENT = 0x22, 320 MFI_STAT_NOT_FOUND = 0x23, 321 MFI_STAT_NOT_IN_ENCL = 0x24, 322 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 323 MFI_STAT_PD_TYPE_WRONG = 0x26, 324 MFI_STAT_PR_DISABLED = 0x27, 325 MFI_STAT_ROW_INDEX_INVALID = 0x28, 326 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 327 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 328 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 329 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 330 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 331 MFI_STAT_SCSI_IO_FAILED = 0x2e, 332 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 333 MFI_STAT_SHUTDOWN_FAILED = 0x30, 334 MFI_STAT_TIME_NOT_SET = 0x31, 335 MFI_STAT_WRONG_STATE = 0x32, 336 MFI_STAT_LD_OFFLINE = 0x33, 337 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 338 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 339 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 340 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 341 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 342 MFI_STAT_INVALID_STATUS = 0xff 343} mfi_status_t; 344 345typedef enum { 346 MFI_EVT_CLASS_DEBUG = -2, 347 MFI_EVT_CLASS_PROGRESS = -1, 348 MFI_EVT_CLASS_INFO = 0, 349 MFI_EVT_CLASS_WARNING = 1, 350 MFI_EVT_CLASS_CRITICAL = 2, 351 MFI_EVT_CLASS_FATAL = 3, 352 MFI_EVT_CLASS_DEAD = 4 353} mfi_evt_class_t; 354 355typedef enum { 356 MFI_EVT_LOCALE_LD = 0x0001, 357 MFI_EVT_LOCALE_PD = 0x0002, 358 MFI_EVT_LOCALE_ENCL = 0x0004, 359 MFI_EVT_LOCALE_BBU = 0x0008, 360 MFI_EVT_LOCALE_SAS = 0x0010, 361 MFI_EVT_LOCALE_CTRL = 0x0020, 362 MFI_EVT_LOCALE_CONFIG = 0x0040, 363 MFI_EVT_LOCALE_CLUSTER = 0x0080, 364 MFI_EVT_LOCALE_ALL = 0xffff 365} mfi_evt_locale_t; 366 367typedef enum { 368 MR_EVT_ARGS_NONE = 0x00, 369 MR_EVT_ARGS_CDB_SENSE, 370 MR_EVT_ARGS_LD, 371 MR_EVT_ARGS_LD_COUNT, 372 MR_EVT_ARGS_LD_LBA, 373 MR_EVT_ARGS_LD_OWNER, 374 MR_EVT_ARGS_LD_LBA_PD_LBA, 375 MR_EVT_ARGS_LD_PROG, 376 MR_EVT_ARGS_LD_STATE, 377 MR_EVT_ARGS_LD_STRIP, 378 MR_EVT_ARGS_PD, 379 MR_EVT_ARGS_PD_ERR, 380 MR_EVT_ARGS_PD_LBA, 381 MR_EVT_ARGS_PD_LBA_LD, 382 MR_EVT_ARGS_PD_PROG, 383 MR_EVT_ARGS_PD_STATE, 384 MR_EVT_ARGS_PCI, 385 MR_EVT_ARGS_RATE, 386 MR_EVT_ARGS_STR, 387 MR_EVT_ARGS_TIME, 388 MR_EVT_ARGS_ECC 389} mfi_evt_args; 390 391/* XXX should be in mfi_evt_args ? */ 392#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 393#define MR_EVT_ARGS_PD_ADDRESS 0x1d 394#define MR_EVT_PD_INSERTED 0x005b 395#define MR_EVT_PD_REMOVED 0x0070 396#define MR_EVT_PD_STATE_CHANGE 0x0072 397#define MR_EVT_LD_CHANGE 0x0051 398#define MR_EVT_LD_CREATED 0x008a 399#define MR_EVT_LD_DELETED 0x008b 400#define MR_EVT_PD_REMOVED_EXT 0x00f8 401#define MR_EVT_PD_INSERTED_EXT 0x00f7 402 403 404 405typedef enum { 406 MR_PD_QUERY_TYPE_ALL = 0, 407 MR_PD_QUERY_TYPE_STATE = 1, 408 MR_PD_QUERY_TYPE_POWER_STATE = 2, 409 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 410 MR_PD_QUERY_TYPE_SPEED = 4, 411 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5 /*query for system drives */ 412} mfi_pd_query_type; 413 414/* driver definitions */ 415#define MFI_MAX_PD_CHANNELS 2 416#define MFI_MAX_PD_ARRAY 32 417#define MFI_MAX_LD_CHANNELS 2 418#define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 419#define MFI_MAX_CHANNEL_DEVS 128 420#define MFI_DEFAULT_ID -1 421#define MFI_MAX_LUN 8 422#define MFI_MAX_LD 64 423#define MFI_MAX_SPAN 8 424#define MFI_MAX_ARRAY_DEDICATED 16 425#define MFI_MAX_PD 256 426 427/* sense buffer */ 428struct mfi_sense { 429 uint8_t mse_data[MFI_SENSE_SIZE]; 430}; 431 432/* scatter gather elements */ 433struct mfi_sg32 { 434 uint32_t addr; 435 uint32_t len; 436}; 437 438struct mfi_sg64 { 439 uint64_t addr; 440 uint32_t len; 441} __packed; 442 443struct mfi_sg_ieee { 444 uint64_t addr; 445 uint32_t len; 446 uint32_t flags; 447}; 448 449 450union mfi_sgl { 451 struct mfi_sg32 sg32[1]; 452 struct mfi_sg64 sg64[1]; 453 struct mfi_sg_ieee sg_ieee[1]; 454}; 455 456/* message frame */ 457struct mfi_frame_header { 458 uint8_t mfh_cmd; 459 uint8_t mfh_sense_len; 460 uint8_t mfh_cmd_status; 461 uint8_t mfh_scsi_status; 462 uint8_t mfh_target_id; 463 uint8_t mfh_lun_id; 464 uint8_t mfh_cdb_len; 465 uint8_t mfh_sg_count; 466 uint32_t mfh_context; 467 uint32_t mfh_pad0; 468 uint16_t mfh_flags; 469 uint16_t mfh_timeout; 470 uint32_t mfh_data_len; 471}; 472 473union mfi_sgl_frame { 474 struct mfi_sg32 sge32[8]; 475 struct mfi_sg64 sge64[5]; 476 477} __packed; 478 479struct mfi_init_frame { 480 struct mfi_frame_header mif_header; 481 uint32_t mif_qinfo_new_addr_lo; 482 uint32_t mif_qinfo_new_addr_hi; 483 uint32_t mif_qinfo_old_addr_lo; 484 uint32_t mif_qinfo_old_addr_hi; 485 uint32_t driver_ver_lo; /* 0x28 */ 486 uint32_t driver_ver_hi; /* 0x2c */ 487 uint32_t reserved[4]; 488} __packed; 489 490/* queue init structure */ 491struct mfi_init_qinfo { 492 uint32_t miq_flags; 493 uint32_t miq_rq_entries; 494 uint32_t miq_rq_addr_lo; 495 uint32_t miq_rq_addr_hi; 496 uint32_t miq_pi_addr_lo; 497 uint32_t miq_pi_addr_hi; 498 uint32_t miq_ci_addr_lo; 499 uint32_t miq_ci_addr_hi; 500} __packed; 501 502#define MFI_IO_FRAME_SIZE 40 503struct mfi_io_frame { 504 struct mfi_frame_header mif_header; 505 uint32_t mif_sense_addr_lo; 506 uint32_t mif_sense_addr_hi; 507 uint32_t mif_lba_lo; 508 uint32_t mif_lba_hi; 509 union mfi_sgl mif_sgl; 510} __packed; 511 512#define MFI_PASS_FRAME_SIZE 48 513struct mfi_pass_frame { 514 struct mfi_frame_header mpf_header; 515 uint32_t mpf_sense_addr_lo; 516 uint32_t mpf_sense_addr_hi; 517 uint8_t mpf_cdb[16]; 518 union mfi_sgl mpf_sgl; 519} __packed; 520 521#define MFI_DCMD_FRAME_SIZE 40 522struct mfi_dcmd_frame { 523 struct mfi_frame_header mdf_header; 524 uint32_t mdf_opcode; 525 union mfi_mbox mdf_mbox; 526 union mfi_sgl mdf_sgl; 527}; 528#define MFI_DCMD_MBOX_PEND_FLAG 0x1 529 530struct mfi_abort_frame { 531 struct mfi_frame_header maf_header; 532 uint32_t maf_abort_context; 533 uint32_t maf_pad; 534 uint32_t maf_abort_mfi_addr_lo; 535 uint32_t maf_abort_mfi_addr_hi; 536 uint32_t maf_reserved[6]; 537}; 538 539struct mfi_smp_frame { 540 struct mfi_frame_header msf_header; 541 uint64_t msf_sas_addr; 542 union { 543 struct mfi_sg32 sg32[2]; 544 struct mfi_sg64 sg64[2]; 545 } msf_sgl; 546} __packed; 547 548struct mfi_stp_frame { 549 struct mfi_frame_header msf_header; 550 uint16_t msf_fis[10]; 551 uint32_t msf_stp_flags; 552 union { 553 struct mfi_sg32 sg32[2]; 554 struct mfi_sg64 sg64[2]; 555 } msf_sgl; 556} __packed; 557 558union mfi_frame { 559 struct mfi_frame_header mfr_header; 560 struct mfi_init_frame mfr_init; 561 struct mfi_io_frame mfr_io; 562 struct mfi_pass_frame mfr_pass; 563 struct mfi_dcmd_frame mfr_dcmd; 564 struct mfi_abort_frame mfr_abort; 565 struct mfi_smp_frame mfr_smp; 566 struct mfi_stp_frame mfr_stp; 567 uint8_t mfr_bytes[MFI_FRAME_SIZE]; 568}; 569 570union mfi_evt_class_locale { 571 struct { 572 uint16_t locale; 573 uint8_t reserved; 574 int8_t class; 575 } mec_members; 576 uint32_t mec_word; 577}; 578 579struct mfi_evt_log_info { 580 uint32_t mel_newest_seq_num; 581 uint32_t mel_oldest_seq_num; 582 uint32_t mel_clear_seq_num; 583 uint32_t mel_shutdown_seq_num; 584 uint32_t mel_boot_seq_num; 585}; 586 587struct mfi_progress { 588 uint16_t mp_progress; 589 uint16_t mp_elapsed_seconds; 590}; 591 592struct mfi_evtarg_ld { 593 uint16_t mel_target_id; 594 uint8_t mel_ld_index; 595 uint8_t mel_reserved; 596}; 597 598struct mfi_evtarg_pd { 599 uint16_t mep_device_id; 600 uint8_t mep_encl_index; 601 uint8_t mep_slot_number; 602}; 603 604struct mfi_evtarg_pd_state { 605 struct mfi_evtarg_pd pd; 606 uint32_t prev_state; 607 uint32_t new_state; 608}; 609 610struct mfi_evtarg_pd_address { 611 uint16_t device_id; 612 uint16_t encl_id; 613 614 union { 615 struct { 616 uint8_t encl_index; 617 uint8_t slot_number; 618 } pd_address; 619 struct { 620 uint8_t encl_position; 621 uint8_t encl_connector_index; 622 } encl_address; 623 } address; 624 625 uint8_t scsi_dev_type; 626 627 union { 628 uint8_t port_bitmap; 629 uint8_t port_numbers; 630 } connected; 631 632 uint64_t sas_addr[2]; 633}; 634 635struct mfi_evt_detail { 636 uint32_t med_seq_num; 637 uint32_t med_time_stamp; 638 uint32_t med_code; 639 union mfi_evt_class_locale med_cl; 640 uint8_t med_arg_type; 641 uint8_t med_reserved1[15]; 642 643 union { 644 struct { 645 struct mfi_evtarg_pd pd; 646 uint8_t cdb_length; 647 uint8_t sense_length; 648 uint8_t reserved[2]; 649 uint8_t cdb[16]; 650 uint8_t sense[64]; 651 } __packed cdb_sense; 652 653 struct mfi_evtarg_ld ld; 654 655 struct { 656 struct mfi_evtarg_ld ld; 657 uint64_t count; 658 } __packed ld_count; 659 660 struct { 661 uint64_t lba; 662 struct mfi_evtarg_ld ld; 663 } __packed ld_lba; 664 665 struct { 666 struct mfi_evtarg_ld ld; 667 uint32_t prev_owner; 668 uint32_t new_owner; 669 } __packed ld_owner; 670 671 struct { 672 uint64_t ld_lba; 673 uint64_t pd_lba; 674 struct mfi_evtarg_ld ld; 675 struct mfi_evtarg_pd pd; 676 } __packed ld_lba_pd_lba; 677 678 struct { 679 struct mfi_evtarg_ld ld; 680 struct mfi_progress prog; 681 } __packed ld_prog; 682 683 struct { 684 struct mfi_evtarg_ld ld; 685 uint32_t prev_state; 686 uint32_t new_state; 687 } __packed ld_state; 688 689 struct { 690 uint64_t strip; 691 struct mfi_evtarg_ld ld; 692 } __packed ld_strip; 693 694 struct mfi_evtarg_pd pd; 695 696 struct { 697 struct mfi_evtarg_pd pd; 698 uint32_t err; 699 } __packed pd_err; 700 701 struct { 702 uint64_t lba; 703 struct mfi_evtarg_pd pd; 704 } __packed pd_lba; 705 706 struct { 707 uint64_t lba; 708 struct mfi_evtarg_pd pd; 709 struct mfi_evtarg_ld ld; 710 } __packed pd_lba_ld; 711 712 struct { 713 struct mfi_evtarg_pd pd; 714 struct mfi_progress prog; 715 } __packed pd_prog; 716 717 struct mfi_evtarg_pd_state pd_state; 718 719 struct { 720 uint16_t vendor_id; 721 uint16_t device_id; 722 uint16_t subvendor_id; 723 uint16_t subdevice_id; 724 } __packed pci; 725 726 uint32_t rate; 727 char str[96]; 728 729 struct { 730 uint32_t rtc; 731 uint32_t elapsed_seconds; 732 } __packed time; 733 734 struct { 735 uint32_t ecar; 736 uint32_t elog; 737 char str[64]; 738 } __packed ecc; 739 740 struct mfi_evtarg_pd_address pd_address; 741 742 uint8_t b[96]; 743 uint16_t s[48]; 744 uint32_t w[24]; 745 uint64_t d[12]; 746 } args; 747 748 char med_description[128]; 749} __packed; 750 751/* controller properties from mfi_ctrl_info */ 752struct mfi_ctrl_props { 753 uint16_t mcp_seq_num; 754 uint16_t mcp_pred_fail_poll_interval; 755 uint16_t mcp_intr_throttle_cnt; 756 uint16_t mcp_intr_throttle_timeout; 757 uint8_t mcp_rebuild_rate; 758 uint8_t mcp_patrol_read_rate; 759 uint8_t mcp_bgi_rate; 760 uint8_t mcp_cc_rate; 761 uint8_t mcp_recon_rate; 762 uint8_t mcp_cache_flush_interval; 763 uint8_t mcp_spinup_drv_cnt; 764 uint8_t mcp_spinup_delay; 765 uint8_t mcp_cluster_enable; 766 uint8_t mcp_coercion_mode; 767 uint8_t mcp_alarm_enable; 768 uint8_t mcp_disable_auto_rebuild; 769 uint8_t mcp_disable_battery_warn; 770 uint8_t mcp_ecc_bucket_size; 771 uint16_t mcp_ecc_bucket_leak_rate; 772 uint8_t mcp_restore_hotspare_on_insertion; 773 uint8_t mcp_expose_encl_devices; 774 uint8_t maintainPdFailHistory; 775 uint8_t disallowHostRequestReordering; 776 /* set TRUE to abort CC on detecting an inconsistency */ 777 uint8_t abortCCOnError; 778 /* load balance mode (MR_LOAD_BALANCE_MODE) */ 779 uint8_t loadBalanceMode; 780 /* 781 * 0 - use auto detect logic of backplanes like SGPIO, i2c SEP using 782 * h/w mechanism like GPIO pins 783 * 1 - disable auto detect SGPIO, 784 * 2 - disable i2c SEP auto detect 785 * 3 - disable both auto detect 786 */ 787 uint8_t disableAutoDetectBackplane; 788 /* 789 * % of source LD to be reserved for a VDs snapshot in snapshot 790 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so on 791 */ 792 uint8_t snapVDSpace; 793 794 /* 795 * Add properties that can be controlled by a bit in the following 796 * structure. 797 */ 798 struct { 799 /* set TRUE to disable copyBack (0=copback enabled) */ 800 uint32_t copyBackDisabled :1; 801 uint32_t SMARTerEnabled :1; 802 uint32_t prCorrectUnconfiguredAreas :1; 803 uint32_t useFdeOnly :1; 804 uint32_t disableNCQ :1; 805 uint32_t SSDSMARTerEnabled :1; 806 uint32_t SSDPatrolReadEnabled :1; 807 uint32_t enableSpinDownUnconfigured :1; 808 uint32_t autoEnhancedImport :1; 809 uint32_t enableSecretKeyControl :1; 810 uint32_t disableOnlineCtrlReset :1; 811 uint32_t allowBootWithPinnedCache :1; 812 uint32_t disableSpinDownHS :1; 813 uint32_t enableJBOD :1; 814 uint32_t disableCacheBypass :1; 815 uint32_t useDiskActivityForLocate :1; 816 uint32_t enablePI :1; 817 uint32_t preventPIImport :1; 818 uint32_t useGlobalSparesForEmergency :1; 819 uint32_t useUnconfGoodForEmergency :1; 820 uint32_t useEmergencySparesforSMARTer :1; 821 uint32_t forceSGPIOForQuadOnly :1; 822 uint32_t enableConfigAutoBalance :1; 823 uint32_t enableVirtualCache :1; 824 uint32_t enableAutoLockRecovery :1; 825 uint32_t disableImmediateIO :1; 826 uint32_t disableT10RebuildAssist :1; 827 uint32_t ignore64ldRestriction :1; 828 uint32_t enableSwZone :1; 829 uint32_t limitMaxRateSATA3G :1; 830 uint32_t reserved :2; 831 } OnOffProperties; 832 /* 833 * % of source LD to be reserved for auto snapshot in snapshot 834 * repository, for metadata and user data: 1=5%, 2=10%, 3=15% and so 835 * on. 836 */ 837 uint8_t autoSnapVDSpace; 838 /* 839 * Snapshot writeable VIEWs capacity as a % of source LD capacity: 840 * 0=READ only, 1=5%, 2=10%, 3=15% and so on. 841 */ 842 uint8_t viewSpace; 843 /* # of idle minutes before device is spun down (0=use FW defaults) */ 844 uint16_t spinDownTime; 845 uint8_t reserved[24]; 846} __packed; 847 848/* pci info */ 849struct mfi_info_pci { 850 uint16_t mip_vendor; 851 uint16_t mip_device; 852 uint16_t mip_subvendor; 853 uint16_t mip_subdevice; 854 uint8_t mip_reserved[24]; 855} __packed; 856 857/* host interface info */ 858struct mfi_info_host { 859 uint8_t mih_type; 860#define MFI_INFO_HOST_PCIX 0x01 861#define MFI_INFO_HOST_PCIE 0x02 862#define MFI_INFO_HOST_ISCSI 0x04 863#define MFI_INFO_HOST_SAS3G 0x08 864 uint8_t mih_reserved[6]; 865 uint8_t mih_port_count; 866 uint64_t mih_port_addr[8]; 867} __packed; 868 869/* device interface info */ 870struct mfi_info_device { 871 uint8_t mid_type; 872#define MFI_INFO_DEV_SPI 0x01 873#define MFI_INFO_DEV_SAS3G 0x02 874#define MFI_INFO_DEV_SATA1 0x04 875#define MFI_INFO_DEV_SATA3G 0x08 876 uint8_t mid_reserved[6]; 877 uint8_t mid_port_count; 878 uint64_t mid_port_addr[8]; 879} __packed; 880 881/* firmware component info */ 882struct mfi_info_component { 883 char mic_name[8]; 884 char mic_version[32]; 885 char mic_build_date[16]; 886 char mic_build_time[16]; 887} __packed; 888 889/* controller info from MFI_DCMD_CTRL_GETINFO. */ 890struct mfi_ctrl_info { 891 struct mfi_info_pci mci_pci; 892 struct mfi_info_host mci_host; 893 struct mfi_info_device mci_device; 894 895 /* Firmware components that are present and active. */ 896 uint32_t mci_image_check_word; 897 uint32_t mci_image_component_count; 898 struct mfi_info_component mci_image_component[8]; 899 900 /* Firmware components that have been flashed but are inactive */ 901 uint32_t mci_pending_image_component_count; 902 struct mfi_info_component mci_pending_image_component[8]; 903 904 uint8_t mci_max_arms; 905 uint8_t mci_max_spans; 906 uint8_t mci_max_arrays; 907 uint8_t mci_max_lds; 908 char mci_product_name[80]; 909 char mci_serial_number[32]; 910 uint32_t mci_hw_present; 911#define MFI_INFO_HW_BBU 0x01 912#define MFI_INFO_HW_ALARM 0x02 913#define MFI_INFO_HW_NVRAM 0x04 914#define MFI_INFO_HW_UART 0x08 915 uint32_t mci_current_fw_time; 916 uint16_t mci_max_cmds; 917 uint16_t mci_max_sg_elements; 918 uint32_t mci_max_request_size; 919 uint16_t mci_lds_present; 920 uint16_t mci_lds_degraded; 921 uint16_t mci_lds_offline; 922 uint16_t mci_pd_present; 923 uint16_t mci_pd_disks_present; 924 uint16_t mci_pd_disks_pred_failure; 925 uint16_t mci_pd_disks_failed; 926 uint16_t mci_nvram_size; 927 uint16_t mci_memory_size; 928 uint16_t mci_flash_size; 929 uint16_t mci_ram_correctable_errors; 930 uint16_t mci_ram_uncorrectable_errors; 931 uint8_t mci_cluster_allowed; 932 uint8_t mci_cluster_active; 933 uint16_t mci_max_strips_per_io; 934 935 uint32_t mci_raid_levels; 936#define MFI_INFO_RAID_0 0x01 937#define MFI_INFO_RAID_1 0x02 938#define MFI_INFO_RAID_5 0x04 939#define MFI_INFO_RAID_1E 0x08 940#define MFI_INFO_RAID_6 0x10 941 942 uint32_t mci_adapter_ops; 943#define MFI_INFO_AOPS_RBLD_RATE 0x0001 944#define MFI_INFO_AOPS_CC_RATE 0x0002 945#define MFI_INFO_AOPS_BGI_RATE 0x0004 946#define MFI_INFO_AOPS_RECON_RATE 0x0008 947#define MFI_INFO_AOPS_PATROL_RATE 0x0010 948#define MFI_INFO_AOPS_ALARM_CONTROL 0x0020 949#define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040 950#define MFI_INFO_AOPS_BBU 0x0080 951#define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100 952#define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200 953#define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400 954#define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800 955#define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000 956#define MFI_INFO_AOPS_MIXED_ARRAY 0x2000 957#define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000 958 959 uint32_t mci_ld_ops; 960#define MFI_INFO_LDOPS_READ_POLICY 0x01 961#define MFI_INFO_LDOPS_WRITE_POLICY 0x02 962#define MFI_INFO_LDOPS_IO_POLICY 0x04 963#define MFI_INFO_LDOPS_ACCESS_POLICY 0x08 964#define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10 965 966 struct { 967 uint8_t min; 968 uint8_t max; 969 uint8_t reserved[2]; 970 } __packed mci_stripe_sz_ops; 971 972 uint32_t mci_pd_ops; 973#define MFI_INFO_PDOPS_FORCE_ONLINE 0x01 974#define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02 975#define MFI_INFO_PDOPS_FORCE_REBUILD 0x04 976 977 uint32_t mci_pd_mix_support; 978#define MFI_INFO_PDMIX_SAS 0x01 979#define MFI_INFO_PDMIX_SATA 0x02 980#define MFI_INFO_PDMIX_ENCL 0x04 981#define MFI_INFO_PDMIX_LD 0x08 982#define MFI_INFO_PDMIX_SATA_CLUSTER 0x10 983 984 uint8_t mci_ecc_bucket_count; 985 uint8_t mci_reserved2[11]; 986 struct mfi_ctrl_props mci_properties; 987 char mci_package_version[0x60]; 988 989 uint64_t mci_dev_iface_port_addr2[8]; 990 uint8_t mci_reserved3[128]; 991 992 struct { 993 uint16_t raid_level_0; 994 uint16_t raid_level_1; 995 uint16_t raid_level_5; 996 uint16_t raid_level_1e; 997 uint16_t raid_level_6; 998 uint16_t raid_level_10; 999 uint16_t raid_level_50; 1000 uint16_t raid_level_60; 1001 uint16_t raid_level_1e_rlq0; 1002 uint16_t raid_level_1e0_rlq0; 1003 uint16_t reserved[6]; 1004 } __packed mci_pds_for_raid_levels; 1005 1006 uint16_t mci_max_pds; 1007 uint16_t mci_max_ded_hsps; 1008 uint16_t mci_max_global_hsps; 1009 uint16_t mci_ddf_size; 1010 uint8_t mci_max_lds_per_array; 1011 uint8_t mci_partitions_in_ddf; 1012 uint8_t mci_lock_key_binding; 1013 uint8_t mci_max_pits_per_ld; 1014 uint8_t mci_max_views_per_ld; 1015 uint8_t mci_max_target_id; 1016 uint16_t mci_max_bvl_vd_size; 1017 1018 uint16_t mci_max_configurable_ssc_size; 1019 uint16_t mci_current_ssc_size; 1020 1021 char mci_expander_fw_version[12]; 1022 1023 uint16_t mci_pfk_trial_time_remaining; 1024 uint16_t mci_cache_memory_size; 1025 1026 uint32_t mci_adapter_ops2; 1027#define MFI_INFO_AOPS2_SUPP_PI_CTRL 0x00000001 1028#define MFI_INFO_AOPS2_SUPP_LD_PIT1 0x00000002 1029#define MFI_INFO_AOPS2_SUPP_LD_PIT2 0x00000004 1030#define MFI_INFO_AOPS2_SUPP_LD_PIT3 0x00000008 1031#define MFI_INFO_AOPS2_SUPP_LD_BBMI 0x00000010 1032#define MFI_INFO_AOPS2_SUPP_SHIELD_STAT 0x00000020 1033#define MFI_INFO_AOPS2_BLK_SSD_WC_CNG 0x00000040 1034#define MFI_INFO_AOPS2_SUPP_SUSPRES_BGO 0x00000080 1035#define MFI_INFO_AOPS2_SUPP_EMERG_SPARE 0x00000100 1036#define MFI_INFO_AOPS2_SUPP_SET_LNKSPD 0x00000200 1037#define MFI_INFO_AOPS2_SUPP_BT_PFK_CNG 0x00000400 1038#define MFI_INFO_AOPS2_SUPP_JBOD 0x00000800 1039#define MFI_INFO_AOPS2_DIS_ONLN_PFK_CNG 0x00001000 1040#define MFI_INFO_AOPS2_SUPP_PERF_TUNE 0x00002000 1041#define MFI_INFO_AOPS2_SUPP_SSD_PREAD 0x00004000 1042#define MFI_INFO_AOPS2_RT_SCHED 0x00008000 1043#define MFI_INFO_AOPS2_SUPP_RESET_NOW 0x00010000 1044#define MFI_INFO_AOPS2_SUPP_EMU_DRIVE 0x00020000 1045#define MFI_INFO_AOPS2_HEADLESS_MODE 0x00040000 1046#define MFI_INFO_AOPS2_DEDIC_HSPARE_LIM 0x00080000 1047#define MFI_INFO_AOPS2_SUPP_UNEVEN_SPAN 0x00100000 1048 1049 uint8_t mci_drv_version[32]; 1050 uint8_t mci_max_da_pd_count_spinup_60; 1051 uint8_t mci_temperature_roc; 1052 uint8_t mci_temperature_ctrl; 1053 uint8_t mci_reserved4; 1054 uint16_t mci_max_configurable_pds; 1055 uint8_t mci_reserved5[2]; 1056 1057 uint32_t cluster; 1058 1059 char cluster_id[16]; 1060 char reserved6[4]; 1061 1062 uint32_t mci_adapter_ops3; 1063#define MFI_INFO_AOPS3_SUPP_PERSONALTY_CHANGE 0x00000003 1064#define MFI_INFO_AOPS3_SUPP_THERMAL_POLL_INTVL 0x00000004 1065#define MFI_INFO_AOPS3_SUPP_DIS_IMMEDIATE_IO 0x00000008 1066#define MFI_INFO_AOPS3_SUPP_T10_REBUILD_ASSIST 0x00000010 1067#define MFI_INFO_AOPS3_SUPP_MAX_EXT_LDS 0x00000020 1068#define MFI_INFO_AOPS3_SUPP_CRASH_DUMP 0x00000040 1069#define MFI_INFO_AOPS3_SUPP_SW_SONE 0x00000080 1070#define MFI_INFO_AOPS3_SUPP_DEBUG_QUEUE 0x00000100 1071#define MFI_INFO_AOPS3_SUPP_NVCACHE_ERASE 0x00000200 1072#define MFI_INFO_AOPS3_SUPP_FORCE_TO_512E 0x00000400 1073#define MFI_INFO_AOPS3_SUPP_HOQ_REBUILD 0x00000800 1074#define MFI_INFO_AOPS3_SUPP_ALLOWED_OPS_DRVRMVL 0x00001000 1075#define MFI_INFO_AOPS3_SUPP_DRV_ACTIVITY_LEDSET 0x00002000 1076#define MFI_INFO_AOPS3_SUPP_NVDRAM 0x00004000 1077#define MFI_INFO_AOPS3_SUPP_FORCE_FLASH 0x00008000 1078#define MFI_INFO_AOPS3_SUPP_DIS_SES_MONITOR 0x00010000 1079#define MFI_INFO_AOPS3_SUPP_CACHE_BYPASS_MODE 0x00020000 1080#define MFI_INFO_AOPS3_SUPP_SECURITY_ON_JBOD 0x00040000 1081#define MFI_INFO_AOPS3_DISCARD_CACHE_DUR_LD_DEL 0x00080000 1082#define MFI_INFO_AOPS3_SUPP_TTY_LOG_COMPRESS 0x00100000 1083#define MFI_INFO_AOPS3_SUPP_CPLD_UPDATE 0x00200000 1084#define MFI_INFO_AOPS3_SUPP_DISK_CACHE_SYS_PD 0x00400000 1085#define MFI_INFO_AOPS3_SUPP_EXTENDED_SSC_SIZE 0x00800000 1086#define MFI_INFO_AOPS3_USE_SEQNUM_JBOD_FP 0x01000000 1087 1088 uint8_t mci_pad_cpld[16]; 1089 1090 uint16_t mci_adapter_ops4; 1091 1092 uint8_t mci_pad[0x800 - 0x7fe]; 1093} __packed; 1094 1095/* logical disk info from MR_DCMD_LD_GET_LIST */ 1096struct mfi_ld { 1097 uint8_t mld_target; 1098 uint8_t mld_res; 1099 uint16_t mld_seq; 1100} __packed; 1101 1102struct mfi_ld_list { 1103 uint32_t mll_no_ld; 1104 uint32_t mll_res; 1105 struct { 1106 struct mfi_ld mll_ld; 1107 uint8_t mll_state; 1108#define MFI_LD_OFFLINE 0x00 1109#define MFI_LD_PART_DEGRADED 0x01 1110#define MFI_LD_DEGRADED 0x02 1111#define MFI_LD_ONLINE 0x03 1112 uint8_t mll_res2; 1113 uint8_t mll_res3; 1114 uint8_t mll_res4; 1115 uint64_t mll_size; 1116 } mll_list[MFI_MAX_LD]; 1117} __packed; 1118 1119/* logical disk details from MR_DCMD_LD_GET_INFO */ 1120struct mfi_ld_prop { 1121 struct mfi_ld mlp_ld; 1122 char mlp_name[16]; 1123 uint8_t mlp_cache_policy; 1124 uint8_t mlp_acces_policy; 1125 uint8_t mlp_diskcache_policy; 1126 uint8_t mlp_cur_cache_policy; 1127 uint8_t mlp_disable_bgi; 1128 uint8_t mlp_res[7]; 1129} __packed; 1130 1131struct mfi_ld_parm { 1132 uint8_t mpa_pri_raid; /* SNIA DDF PRL */ 1133#define MFI_DDF_PRL_RAID0 0x00 1134#define MFI_DDF_PRL_RAID1 0x01 1135#define MFI_DDF_PRL_RAID3 0x03 1136#define MFI_DDF_PRL_RAID4 0x04 1137#define MFI_DDF_PRL_RAID5 0x05 1138#define MFI_DDF_PRL_RAID1E 0x11 1139#define MFI_DDF_PRL_JBOD 0x0f 1140#define MFI_DDF_PRL_CONCAT 0x1f 1141#define MFI_DDF_PRL_RAID5E 0x15 1142#define MFI_DDF_PRL_RAID5EE 0x25 1143#define MFI_DDF_PRL_RAID6 0x16 1144 uint8_t mpa_raid_qual; /* SNIA DDF RLQ */ 1145 uint8_t mpa_sec_raid; /* SNIA DDF SRL */ 1146#define MFI_DDF_SRL_STRIPED 0x00 1147#define MFI_DDF_SRL_MIRRORED 0x01 1148#define MFI_DDF_SRL_CONCAT 0x02 1149#define MFI_DDF_SRL_SPANNED 0x03 1150 uint8_t mpa_stripe_size; 1151 uint8_t mpa_no_drv_per_span; 1152 uint8_t mpa_span_depth; 1153 uint8_t mpa_state; 1154 uint8_t mpa_init_state; 1155 uint8_t mpa_is_consistent; 1156 uint8_t mpa_res1[6]; 1157 uint8_t mpa_isSSCD; 1158 uint8_t mpa_res[16]; 1159} __packed; 1160 1161struct mfi_ld_span { 1162 uint64_t mls_start_block; 1163 uint64_t mls_no_blocks; 1164 uint16_t mls_index; 1165 uint8_t mls_res[6]; 1166} __packed; 1167 1168struct mfi_ld_cfg { 1169 struct mfi_ld_prop mlc_prop; 1170 struct mfi_ld_parm mlc_parm; 1171 struct mfi_ld_span mlc_span[MFI_MAX_SPAN]; 1172} __packed; 1173 1174struct mfi_ld_progress { 1175 uint32_t mlp_in_prog; 1176#define MFI_LD_PROG_CC 0x01 1177#define MFI_LD_PROG_BGI 0x02 1178#define MFI_LD_PROG_FGI 0x04 1179#define MFI_LD_PROG_RECONSTRUCT 0x08 1180 struct mfi_progress mlp_cc; 1181 struct mfi_progress mlp_bgi; 1182 struct mfi_progress mlp_fgi; 1183 struct mfi_progress mlp_reconstruct; 1184 struct mfi_progress mlp_res[4]; 1185} __packed; 1186 1187struct mfi_ld_details { 1188 struct mfi_ld_cfg mld_cfg; 1189 uint64_t mld_size; 1190 struct mfi_ld_progress mld_progress; 1191 uint16_t mld_clust_own_id; 1192 uint8_t mld_res1; 1193 uint8_t mld_res2; 1194 uint8_t mld_inq_page83[64]; 1195 uint8_t mld_res[16]; 1196} __packed; 1197 1198/* physical disk info from MR_DCMD_PD_GET_LIST */ 1199struct mfi_pd_address { 1200 uint16_t mpa_pd_id; 1201 uint16_t mpa_enc_id; 1202 uint8_t mpa_enc_index; 1203 uint8_t mpa_enc_slot; 1204 uint8_t mpa_scsi_type; 1205 uint8_t mpa_port; 1206 uint64_t mpa_sas_address[2]; 1207} __packed; 1208 1209struct mfi_pd_list { 1210 uint32_t mpl_size; 1211 uint32_t mpl_no_pd; 1212 struct mfi_pd_address mpl_address[MFI_MAX_PD]; 1213} __packed; 1214 1215struct mfi_pd { 1216 uint16_t mfp_id; 1217 uint16_t mfp_seq; 1218} __packed; 1219 1220struct mfi_pd_progress { 1221 uint32_t mfp_in_prog; 1222#define MFI_PD_PROG_RBLD 0x01 1223#define MFI_PD_PROG_PR 0x02 1224#define MFI_PD_PROG_CLEAR 0x04 1225 struct mfi_progress mfp_rebuild; 1226 struct mfi_progress mfp_patrol_read; 1227 struct mfi_progress mfp_clear; 1228 struct mfi_progress mfp_res[4]; 1229} __packed; 1230 1231struct mfi_pd_details { 1232 struct mfi_pd mpd_pd; 1233 uint8_t mpd_inq_data[96]; 1234 uint8_t mpd_inq_page83[64]; 1235 uint8_t mpd_no_support; 1236 uint8_t mpd_scsi_type; 1237 uint8_t mpd_port; 1238 uint8_t mpd_speed; 1239 uint32_t mpd_mediaerr_cnt; 1240 uint32_t mpd_othererr_cnt; 1241 uint32_t mpd_predfail_cnt; 1242 uint32_t mpd_last_pred_event; 1243 uint16_t mpd_fw_state; 1244 uint8_t mpd_rdy_for_remove; 1245 uint8_t mpd_link_speed; 1246 uint32_t mpd_ddf_state; 1247#define MFI_DDF_GUID_FORCED 0x01 1248#define MFI_DDF_PART_OF_VD 0x02 1249#define MFI_DDF_GLOB_HOTSPARE 0x04 1250#define MFI_DDF_HOTSPARE 0x08 1251#define MFI_DDF_FOREIGN 0x10 1252#define MFI_DDF_TYPE_MASK 0xf000 1253#define MFI_DDF_TYPE_UNKNOWN 0x0000 1254#define MFI_DDF_TYPE_PAR_SCSI 0x1000 1255#define MFI_DDF_TYPE_SAS 0x2000 1256#define MFI_DDF_TYPE_SATA 0x3000 1257#define MFI_DDF_TYPE_FC 0x4000 1258 struct { 1259 uint8_t mpp_cnt; 1260 uint8_t mpp_severed; 1261 uint8_t mpp_res[6]; 1262 uint64_t mpp_sas_addr[4]; 1263 } __packed mpd_path; 1264 uint64_t mpd_size; 1265 uint64_t mpd_no_coerce_size; 1266 uint64_t mpd_coerce_size; 1267 uint16_t mpd_enc_id; 1268 uint8_t mpd_enc_idx; 1269 uint8_t mpd_enc_slot; 1270 struct mfi_pd_progress mpd_progress; 1271 uint8_t mpd_bblock_full; 1272 uint8_t mpd_unusable; 1273 uint8_t mpd_res[218]; /* size is 512 */ 1274} __packed; 1275 1276/* array configuration from MR_DCMD_CONF_GET */ 1277struct mfi_array { 1278 uint64_t mar_smallest_pd; 1279 uint8_t mar_no_disk; 1280 uint8_t mar_res1; 1281 uint16_t mar_array_ref; 1282 uint8_t mar_res2[20]; 1283 struct { 1284 struct mfi_pd mar_pd; 1285 uint16_t mar_pd_state; 1286#define MFI_PD_UNCONFIG_GOOD 0x00 1287#define MFI_PD_UNCONFIG_BAD 0x01 1288#define MFI_PD_HOTSPARE 0x02 1289#define MFI_PD_OFFLINE 0x10 1290#define MFI_PD_FAILED 0x11 1291#define MFI_PD_REBUILD 0x14 1292#define MFI_PD_ONLINE 0x18 1293#define MFI_PD_COPYBACK 0x20 1294#define MFI_PD_SYSTEM 0x40 1295#define MFI_PD_JBOD MFI_PD_SYSTEM 1296 uint8_t mar_enc_pd; 1297 uint8_t mar_enc_slot; 1298 } pd[MFI_MAX_PD_ARRAY]; 1299} __packed; 1300 1301struct mfi_hotspare { 1302 struct mfi_pd mhs_pd; 1303 uint8_t mhs_type; 1304#define MFI_PD_HS_DEDICATED 0x01 1305#define MFI_PD_HS_REVERTIBLE 0x02 1306#define MFI_PD_HS_ENC_AFFINITY 0x04 1307 uint8_t mhs_res[2]; 1308 uint8_t mhs_array_max; 1309 uint16_t mhs_array_ref[MFI_MAX_ARRAY_DEDICATED]; 1310} __packed; 1311 1312struct mfi_conf { 1313 uint32_t mfc_size; 1314 uint16_t mfc_no_array; 1315 uint16_t mfc_array_size; 1316 uint16_t mfc_no_ld; 1317 uint16_t mfc_ld_size; 1318 uint16_t mfc_no_hs; 1319 uint16_t mfc_hs_size; 1320 uint8_t mfc_res[16]; 1321 /* 1322 * XXX this is a ridiculous hack and does not reflect reality 1323 * Structures are actually indexed and therefore need pointer 1324 * math to reach. We need the size of this structure first so 1325 * call it with the size of this structure and then use the returned 1326 * values to allocate memory and do the transfer of the whole structure 1327 * then calculate pointers to each of these structures. 1328 */ 1329 struct mfi_array mfc_array[1]; 1330 struct mfi_ld_cfg mfc_ld[1]; 1331 struct mfi_hotspare mfc_hs[1]; 1332} __packed; 1333 1334/* informations from MR_DCMD_BBU_GET_CAPACITY_INFO */ 1335struct mfi_bbu_capacity_info { 1336 uint16_t relative_charge; 1337 uint16_t absolute_charge; 1338 uint16_t remaining_capacity; 1339 uint16_t full_charge_capacity; 1340 uint16_t run_time_to_empty; 1341 uint16_t average_time_to_empty; 1342 uint16_t average_time_to_full; 1343 uint16_t cycle_count; 1344 uint16_t max_error; 1345 uint16_t remaining_capacity_alarm; 1346 uint16_t remaining_time_alarm; 1347 uint8_t reserved[26]; 1348} __packed; 1349 1350/* informations from MR_DCMD_BBU_GET_DESIGN_INFO */ 1351struct mfi_bbu_design_info { 1352 uint32_t mfg_date; 1353 uint16_t design_capacity; 1354 uint16_t design_voltage; 1355 uint16_t spec_info; 1356 uint16_t serial_number; 1357 uint16_t pack_stat_config; 1358 uint8_t mfg_name[12]; 1359 uint8_t device_name[8]; 1360 uint8_t device_chemistry[8]; 1361 uint8_t mfg_data[8]; 1362 uint8_t reserved[17]; 1363} __packed; 1364 1365struct mfi_ibbu_state { 1366 uint16_t gas_guage_status; 1367 uint16_t relative_charge; 1368 uint16_t charger_system_state; 1369 uint16_t charger_system_ctrl; 1370 uint16_t charging_current; 1371 uint16_t absolute_charge; 1372 uint16_t max_error; 1373 uint8_t reserved[18]; 1374} __packed; 1375 1376struct mfi_bbu_state { 1377 uint16_t gas_guage_status; 1378 uint16_t relative_charge; 1379 uint16_t charger_status; 1380 uint16_t remaining_capacity; 1381 uint16_t full_charge_capacity; 1382 uint8_t is_SOH_good; 1383 uint8_t reserved[21]; 1384} __packed; 1385 1386union mfi_bbu_status_detail { 1387 struct mfi_ibbu_state ibbu; 1388 struct mfi_bbu_state bbu; 1389}; 1390 1391/* informations from MR_DCMD_BBU_GET_STATUS */ 1392struct mfi_bbu_status { 1393 uint8_t battery_type; 1394#define MFI_BBU_TYPE_NONE 0 1395#define MFI_BBU_TYPE_IBBU 1 1396#define MFI_BBU_TYPE_BBU 2 1397#define MFI_BBU_TYPE_IBBU09 5 1398#define MFI_BBU_TYPE_CVPM02 6 1399 uint8_t reserved; 1400 uint16_t voltage; /* mV */ 1401 int16_t current; /* mA */ 1402 uint16_t temperature; /* degC */ 1403 uint32_t fw_status; 1404#define MFI_BBU_STATE_PACK_MISSING (1 << 0) 1405#define MFI_BBU_STATE_VOLTAGE_LOW (1 << 1) 1406#define MFI_BBU_STATE_TEMPERATURE_HIGH (1 << 2) 1407#define MFI_BBU_STATE_CHARGE_ACTIVE (1 << 3) 1408#define MFI_BBU_STATE_DISCHARGE_ACTIVE (1 << 4) 1409#define MFI_BBU_STATE_LEARN_CYC_REQ (1 << 5) 1410#define MFI_BBU_STATE_LEARN_CYC_ACTIVE (1 << 6) 1411#define MFI_BBU_STATE_LEARN_CYC_FAIL (1 << 7) 1412#define MFI_BBU_STATE_LEARN_CYC_TIMEOUT (1 << 8) 1413#define MFI_BBU_STATE_I2C_ERR_DETECT (1 << 9) 1414#define MFI_BBU_STATE_REPLACE_PACK (1 << 10) 1415#define MFI_BBU_STATE_CAPACITY_LOW (1 << 11) 1416#define MFI_BBU_STATE_LEARN_REQUIRED (1 << 12) 1417#define MFI_BBU_STATE_BAD_IBBU ( \ 1418 MFI_BBU_STATE_PACK_MISSING | \ 1419 MFI_BBU_STATE_VOLTAGE_LOW | \ 1420 MFI_BBU_STATE_DISCHARGE_ACTIVE | \ 1421 MFI_BBU_STATE_LEARN_CYC_ACTIVE | \ 1422 MFI_BBU_STATE_REPLACE_PACK | \ 1423 MFI_BBU_STATE_CAPACITY_LOW) 1424#define MFI_BBU_STATE_BAD_BBU ( \ 1425 MFI_BBU_STATE_PACK_MISSING | \ 1426 MFI_BBU_STATE_REPLACE_PACK | \ 1427 MFI_BBU_STATE_CAPACITY_LOW) 1428 uint8_t pad[20]; 1429 union mfi_bbu_status_detail detail; 1430} __packed; 1431 1432/* ThunderBolt support */ 1433 1434/* 1435 * Raid Context structure which describes MegaRAID specific IO Parameters 1436 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 1437 */ 1438typedef struct _mpi2_scsi_io_vendor_unique { 1439 uint16_t resvd0; /* 0x00 - 0x01 */ 1440 uint16_t timeoutValue; /* 0x02 - 0x03 */ 1441 uint8_t regLockFlags; 1442 uint8_t armId; 1443 uint16_t TargetID; /* 0x06 - 0x07 */ 1444 1445 uint64_t RegLockLBA; /* 0x08 - 0x0F */ 1446 1447 uint32_t RegLockLength; /* 0x10 - 0x13 */ 1448 1449 uint16_t SMID; /* 0x14 - 0x15 nextLMId */ 1450 uint8_t exStatus; /* 0x16 */ 1451 uint8_t Status; /* 0x17 status */ 1452 1453 uint8_t RAIDFlags; /* 0x18 */ 1454 uint8_t numSGE; /* 0x19 numSge */ 1455 uint16_t configSeqNum; /* 0x1A - 0x1B */ 1456 uint8_t spanArm; /* 0x1C */ 1457 uint8_t resvd2[3]; /* 0x1D - 0x1F */ 1458} mpi2_scsi_io_vendor_unique, mpi25_scsi_io_vendor_unique; 1459 1460/***************************************************************************** 1461* 1462* Message Functions 1463* 1464*****************************************************************************/ 1465 1466#define NA_MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 1467#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 1468#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 1469#define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 1470#define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 1471#define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 1472#define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 1473#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 1474#define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 1475#define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 1476#define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 1477#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 1478#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 1479#define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 1480#define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 1481#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 1482#define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 1483#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 1484#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 1485#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ 1486#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 1487#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 1488#define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 1489#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 1490#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 1491#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 1492#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 1493#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ 1494#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ 1495#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ 1496 1497/* Doorbell functions */ 1498#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 1499#define MPI2_FUNCTION_HANDSHAKE (0x42) 1500 1501/***************************************************************************** 1502* 1503* MPI Version Definitions 1504* 1505*****************************************************************************/ 1506 1507#define MPI2_VERSION_MAJOR (0x02) 1508#define MPI2_VERSION_MINOR (0x00) 1509#define MPI2_VERSION_MAJOR_MASK (0xFF00) 1510#define MPI2_VERSION_MAJOR_SHIFT (8) 1511#define MPI2_VERSION_MINOR_MASK (0x00FF) 1512#define MPI2_VERSION_MINOR_SHIFT (0) 1513#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 1514 MPI2_VERSION_MINOR) 1515 1516#define MPI2_VERSION_02_00 (0x0200) 1517 1518/* versioning for this MPI header set */ 1519#define MPI2_HEADER_VERSION_UNIT (0x10) 1520#define MPI2_HEADER_VERSION_DEV (0x00) 1521#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 1522#define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 1523#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 1524#define MPI2_HEADER_VERSION_DEV_SHIFT (0) 1525#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 1526 MPI2_HEADER_VERSION_DEV) 1527 1528 1529/* IOCInit Request message */ 1530struct mpi2_ioc_init_request { 1531 uint8_t WhoInit; /* 0x00 */ 1532 uint8_t Reserved1; /* 0x01 */ 1533 uint8_t ChainOffset; /* 0x02 */ 1534 uint8_t Function; /* 0x03 */ 1535 uint16_t Reserved2; /* 0x04 */ 1536 uint8_t Reserved3; /* 0x06 */ 1537 uint8_t MsgFlags; /* 0x07 */ 1538 uint8_t VP_ID; /* 0x08 */ 1539 uint8_t VF_ID; /* 0x09 */ 1540 uint16_t Reserved4; /* 0x0A */ 1541 uint16_t MsgVersion; /* 0x0C */ 1542 uint16_t HeaderVersion; /* 0x0E */ 1543 uint32_t Reserved5; /* 0x10 */ 1544 uint16_t Reserved6; /* 0x14 */ 1545 uint8_t Reserved7; /* 0x16 */ 1546 uint8_t HostMSIxVectors; /* 0x17 */ 1547 uint16_t Reserved8; /* 0x18 */ 1548 uint16_t SystemRequestFrameSize; /* 0x1A */ 1549 uint16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 1550 uint16_t ReplyFreeQueueDepth; /* 0x1E */ 1551 uint32_t SenseBufferAddressHigh; /* 0x20 */ 1552 uint32_t SystemReplyAddressHigh; /* 0x24 */ 1553 uint64_t SystemRequestFrameBaseAddress; /* 0x28 */ 1554 uint64_t ReplyDescriptorPostQueueAddress;/* 0x30 */ 1555 uint64_t ReplyFreeQueueAddress; /* 0x38 */ 1556 uint64_t TimeStamp; /* 0x40 */ 1557}; 1558 1559/* WhoInit values */ 1560#define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 1561#define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 1562#define MPI2_WHOINIT_ROM_BIOS (0x02) 1563#define MPI2_WHOINIT_PCI_PEER (0x03) 1564#define MPI2_WHOINIT_HOST_DRIVER (0x04) 1565#define MPI2_WHOINIT_MANUFACTURER (0x05) 1566 1567struct mpi2_sge_chain_union { 1568 uint16_t Length; 1569 uint8_t NextChainOffset; 1570 uint8_t Flags; 1571 union { 1572 uint32_t Address32; 1573 uint64_t Address64; 1574 } u; 1575}; 1576 1577struct mpi2_ieee_sge_simple32 { 1578 uint32_t Address; 1579 uint32_t FlagsLength; 1580}; 1581 1582struct mpi2_ieee_sge_simple64 { 1583 uint64_t Address; 1584 uint32_t Length; 1585 uint16_t Reserved1; 1586 uint8_t Reserved2; 1587 uint8_t Flags; 1588}; 1589 1590typedef union _mpi2_ieee_simple_union { 1591 struct mpi2_ieee_sge_simple32 Simple32; 1592 struct mpi2_ieee_sge_simple64 Simple64; 1593} mpi2_ieee_simple_union; 1594 1595typedef struct _mpi2_sge_simple_union { 1596 uint32_t FlagsLength; 1597 union { 1598 uint32_t Address32; 1599 uint64_t Address64; 1600 } u; 1601} mpi2_sge_simple_union; 1602 1603/* MPI 2.5 SGLs */ 1604 1605#define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1606 1607struct mpi25_ieee_sge_chain64 { 1608 uint64_t Address; 1609 uint32_t Length; 1610 uint16_t Reserved1; 1611 uint8_t NextChainOffset; 1612 uint8_t Flags; 1613}; 1614 1615/* use MPI2_IEEE_SGE_FLAGS_ defines for the Flags field */ 1616 1617/**************************************************************************** 1618* IEEE SGE field definitions and masks 1619****************************************************************************/ 1620 1621/* Flags field bit definitions */ 1622 1623#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1624 1625#define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1626 1627#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1628 1629/* Element Type */ 1630 1631#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1632#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1633 1634/* Data Location Address Space */ 1635 1636#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1637#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1638#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1639#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1640#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1641 1642/* Address Size */ 1643 1644#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 1645#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 1646 1647/*******************/ 1648/* SCSI IO Control bits */ 1649#define MPI2_SCSIIO_CONTROL_ADDCDBLEN_MASK (0xFC000000) 1650#define MPI2_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26) 1651 1652#define MPI2_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000) 1653#define MPI2_SCSIIO_CONTROL_NODATATRANSFER (0x00000000) 1654#define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 1655#define MPI2_SCSIIO_CONTROL_READ (0x02000000) 1656#define MPI2_SCSIIO_CONTROL_BIDIRECTIONAL (0x03000000) 1657 1658#define MPI2_SCSIIO_CONTROL_TASKPRI_MASK (0x00007800) 1659#define MPI2_SCSIIO_CONTROL_TASKPRI_SHIFT (11) 1660 1661#define MPI2_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700) 1662#define MPI2_SCSIIO_CONTROL_SIMPLEQ (0x00000000) 1663#define MPI2_SCSIIO_CONTROL_HEADOFQ (0x00000100) 1664#define MPI2_SCSIIO_CONTROL_ORDEREDQ (0x00000200) 1665#define MPI2_SCSIIO_CONTROL_ACAQ (0x00000400) 1666 1667#define MPI2_SCSIIO_CONTROL_TLR_MASK (0x000000C0) 1668#define MPI2_SCSIIO_CONTROL_NO_TLR (0x00000000) 1669#define MPI2_SCSIIO_CONTROL_TLR_ON (0x00000040) 1670#define MPI2_SCSIIO_CONTROL_TLR_OFF (0x00000080) 1671 1672/*******************/ 1673 1674typedef struct { 1675 uint8_t CDB[20]; /* 0x00 */ 1676 uint32_t PrimaryReferenceTag; /* 0x14 */ 1677 uint16_t PrimaryApplicationTag; /* 0x18 */ 1678 uint16_t PrimaryApplicationTagMask; /* 0x1A */ 1679 uint32_t TransferLength; /* 0x1C */ 1680} mpi2_scsi_io_cdb_eedp32; 1681 1682 1683typedef union _mpi2_ieee_sge_chain_union { 1684 struct mpi2_ieee_sge_simple32 Chain32; 1685 struct mpi25_ieee_sge_chain64 Chain64; 1686} mpi2_ieee_sge_chain_union; 1687 1688typedef union _mpi2_simple_sge_union { 1689 mpi2_sge_simple_union MpiSimple; 1690 mpi2_ieee_simple_union IeeeSimple; 1691} mpi2_simple_sge_union; 1692 1693typedef union _mpi2_sge_io_union { 1694 mpi2_sge_simple_union MpiSimple; 1695 struct mpi2_sge_chain_union MpiChain; 1696 mpi2_ieee_simple_union IeeeSimple; 1697 mpi2_ieee_sge_chain_union IeeeChain; 1698} mpi2_sge_io_union; 1699 1700typedef union { 1701 uint8_t CDB32[32]; 1702 mpi2_scsi_io_cdb_eedp32 EEDP32; 1703 mpi2_sge_simple_union SGE; 1704} mpi2_scsi_io_cdb_union; 1705 1706 1707 1708/********/ 1709 1710/* 1711 * RAID SCSI IO Request Message 1712 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 1713 */ 1714struct mfi_mpi2_request_raid_scsi_io { 1715 uint16_t DevHandle; /* 0x00 */ 1716 uint8_t ChainOffset; /* 0x02 */ 1717 uint8_t Function; /* 0x03 */ 1718 uint16_t Reserved1; /* 0x04 */ 1719 uint8_t Reserved2; /* 0x06 */ 1720 uint8_t MsgFlags; /* 0x07 */ 1721 uint8_t VP_ID; /* 0x08 */ 1722 uint8_t VF_ID; /* 0x09 */ 1723 uint16_t Reserved3; /* 0x0A */ 1724 uint32_t SenseBufferLowAddress; /* 0x0C */ 1725 uint16_t SGLFlags; /* 0x10 */ 1726 uint8_t SenseBufferLength; /* 0x12 */ 1727 uint8_t Reserved4; /* 0x13 */ 1728 uint8_t SGLOffset0; /* 0x14 */ 1729 uint8_t SGLOffset1; /* 0x15 */ 1730 uint8_t SGLOffset2; /* 0x16 */ 1731 uint8_t SGLOffset3; /* 0x17 */ 1732 uint32_t SkipCount; /* 0x18 */ 1733 uint32_t DataLength; /* 0x1C */ 1734 uint32_t BidirectionalDataLength; /* 0x20 */ 1735 uint16_t IoFlags; /* 0x24 */ 1736 uint16_t EEDPFlags; /* 0x26 */ 1737 uint32_t EEDPBlockSize; /* 0x28 */ 1738 uint32_t SecondaryReferenceTag; /* 0x2C */ 1739 uint16_t SecondaryApplicationTag; /* 0x30 */ 1740 uint16_t ApplicationTagTranslationMask; /* 0x32 */ 1741 uint8_t LUN[8]; /* 0x34 */ 1742 uint32_t Control; /* 0x3C */ 1743 mpi2_scsi_io_cdb_union CDB; /* 0x40 */ 1744 mpi2_scsi_io_vendor_unique RaidContext; /* 0x60 */ 1745 mpi2_sge_io_union SGL; /* 0x80 */ 1746} __packed; 1747 1748/* 1749 * MPT RAID MFA IO Descriptor. 1750 */ 1751typedef struct _mfi_raid_mfa_io_descriptor { 1752 uint32_t RequestFlags : 8; 1753 uint32_t MessageAddress1 : 24; /* bits 31:8*/ 1754 uint32_t MessageAddress2; /* bits 61:32 */ 1755} mfi_raid_mfa_io_request_descriptor; 1756 1757struct mfi_mpi2_request_header { 1758 uint8_t RequestFlags; /* 0x00 */ 1759 uint8_t MSIxIndex; /* 0x01 */ 1760 uint16_t SMID; /* 0x02 */ 1761 uint16_t LMID; /* 0x04 */ 1762}; 1763 1764/* defines for the RequestFlags field */ 1765#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 1766#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 1767#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 1768#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 1769#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 1770#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 1771 1772#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 1773 1774struct mfi_mpi2_request_high_priority { 1775 struct mfi_mpi2_request_header header; 1776 uint16_t reserved; 1777}; 1778 1779struct mfi_mpi2_request_scsi_io { 1780 struct mfi_mpi2_request_header header; 1781 uint16_t scsi_io_dev_handle; 1782}; 1783 1784struct mfi_mpi2_request_scsi_target { 1785 struct mfi_mpi2_request_header header; 1786 uint16_t scsi_target_io_index; 1787}; 1788 1789/* Request Descriptors */ 1790union mfi_mpi2_request_descriptor { 1791 struct mfi_mpi2_request_header header; 1792 struct mfi_mpi2_request_high_priority high_priority; 1793 struct mfi_mpi2_request_scsi_io scsi_io; 1794 struct mfi_mpi2_request_scsi_target scsi_target; 1795 uint64_t words; 1796}; 1797 1798/* 1799 * Request descriptor types 1800 */ 1801#define MFI_REQ_DESCRIPT_FLAGS_LD_IO 0x7 1802#define MFI_REQ_DESCRIPT_FLAGS_MFA 0x1 1803#define MFI_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 0x1 1804 1805#define MFI_FUSION_FP_DEFAULT_TIMEOUT 0x14 1806 1807struct mfi_mpi2_reply_header { 1808 uint8_t ReplyFlags; /* 0x00 */ 1809 uint8_t MSIxIndex; /* 0x01 */ 1810 uint16_t SMID; /* 0x02 */ 1811}; 1812 1813/* defines for the ReplyFlags field */ 1814#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 1815#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 1816#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 1817#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 1818#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 1819#define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 1820#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 1821 1822/* values for marking a reply descriptor as unused */ 1823#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 1824#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 1825 1826struct mfi_mpi2_reply_default { 1827 struct mfi_mpi2_reply_header header; 1828 uint32_t DescriptorTypeDependent2; 1829}; 1830 1831struct mfi_mpi2_reply_address { 1832 struct mfi_mpi2_reply_header header; 1833 uint32_t ReplyFrameAddress; 1834}; 1835 1836struct mfi_mpi2_reply_scsi_io { 1837 struct mfi_mpi2_reply_header header; 1838 uint16_t TaskTag; /* 0x04 */ 1839 uint16_t Reserved1; /* 0x06 */ 1840}; 1841 1842struct mfi_mpi2_reply_target_assist { 1843 struct mfi_mpi2_reply_header header; 1844 uint8_t SequenceNumber; /* 0x04 */ 1845 uint8_t Reserved1; /* 0x04 */ 1846 uint16_t IoIndex; /* 0x06 */ 1847}; 1848 1849struct mfi_mpi2_reply_target_cmd_buffer { 1850 struct mfi_mpi2_reply_header header; 1851 uint8_t SequenceNumber; /* 0x04 */ 1852 uint8_t Flags; /* 0x04 */ 1853 uint16_t InitiatorDevHandle; /* 0x06 */ 1854 uint16_t IoIndex; /* 0x06 */ 1855}; 1856 1857struct mfi_mpi2_reply_raid_accel { 1858 struct mfi_mpi2_reply_header header; 1859 uint8_t SequenceNumber; /* 0x04 */ 1860 uint32_t Reserved; /* 0x04 */ 1861}; 1862 1863/* union of Reply Descriptors */ 1864union mfi_mpi2_reply_descriptor { 1865 struct mfi_mpi2_reply_header header; 1866 struct mfi_mpi2_reply_scsi_io scsi_io; 1867 struct mfi_mpi2_reply_target_assist target_assist; 1868 struct mfi_mpi2_reply_target_cmd_buffer target_cmd; 1869 struct mfi_mpi2_reply_raid_accel raid_accel; 1870 struct mfi_mpi2_reply_default reply_default; 1871 uint64_t words; 1872}; 1873 1874struct io_request_info { 1875 uint64_t ldStartBlock; 1876 uint32_t numBlocks; 1877 uint16_t ldTgtId; 1878 uint8_t isRead; 1879 uint16_t devHandle; 1880 uint64_t pdBlock; 1881 uint8_t fpOkForIo; 1882}; 1883 1884/* 1885 * Define MFI Address Context union. 1886 */ 1887#ifdef MFI_ADDRESS_IS_uint64_t 1888typedef uint64_t mfi_address; 1889#else 1890typedef union _mfi_address { 1891 struct { 1892 uint32_t addressLow; 1893 uint32_t addressHigh; 1894 } u; 1895 uint64_t address; 1896} mfi_address; 1897#endif 1898 1899#define MEGASAS_MAX_NAME 32 1900#define MEGASAS_VERSION "4.23" 1901 1902#endif /* _DEV_IC_MFIREG_H_ */ 1903