dwc_mmc.c revision 1.3
1/* $NetBSD: dwc_mmc.c,v 1.3 2014/12/29 23:58:25 jmcneill Exp $ */ 2 3/*- 4 * Copyright (c) 2014 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29#include "opt_dwc_mmc.h" 30 31#include <sys/cdefs.h> 32__KERNEL_RCSID(0, "$NetBSD: dwc_mmc.c,v 1.3 2014/12/29 23:58:25 jmcneill Exp $"); 33 34#include <sys/param.h> 35#include <sys/bus.h> 36#include <sys/device.h> 37#include <sys/intr.h> 38#include <sys/systm.h> 39#include <sys/kernel.h> 40 41#include <dev/sdmmc/sdmmcvar.h> 42#include <dev/sdmmc/sdmmcchip.h> 43#include <dev/sdmmc/sdmmc_ioreg.h> 44 45#include <dev/ic/dwc_mmc_reg.h> 46#include <dev/ic/dwc_mmc_var.h> 47 48static int dwc_mmc_host_reset(sdmmc_chipset_handle_t); 49static uint32_t dwc_mmc_host_ocr(sdmmc_chipset_handle_t); 50static int dwc_mmc_host_maxblklen(sdmmc_chipset_handle_t); 51static int dwc_mmc_card_detect(sdmmc_chipset_handle_t); 52static int dwc_mmc_write_protect(sdmmc_chipset_handle_t); 53static int dwc_mmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 54static int dwc_mmc_bus_clock(sdmmc_chipset_handle_t, int); 55static int dwc_mmc_bus_width(sdmmc_chipset_handle_t, int); 56static int dwc_mmc_bus_rod(sdmmc_chipset_handle_t, int); 57static void dwc_mmc_exec_command(sdmmc_chipset_handle_t, 58 struct sdmmc_command *); 59static void dwc_mmc_card_enable_intr(sdmmc_chipset_handle_t, int); 60static void dwc_mmc_card_intr_ack(sdmmc_chipset_handle_t); 61 62static int dwc_mmc_set_clock(struct dwc_mmc_softc *, u_int); 63static int dwc_mmc_update_clock(struct dwc_mmc_softc *); 64static int dwc_mmc_wait_rint(struct dwc_mmc_softc *, uint32_t, int); 65static int dwc_mmc_pio_wait(struct dwc_mmc_softc *, 66 struct sdmmc_command *); 67static int dwc_mmc_pio_transfer(struct dwc_mmc_softc *, 68 struct sdmmc_command *); 69 70void dwc_mmc_dump_regs(void); 71 72static struct sdmmc_chip_functions dwc_mmc_chip_functions = { 73 .host_reset = dwc_mmc_host_reset, 74 .host_ocr = dwc_mmc_host_ocr, 75 .host_maxblklen = dwc_mmc_host_maxblklen, 76 .card_detect = dwc_mmc_card_detect, 77 .write_protect = dwc_mmc_write_protect, 78 .bus_power = dwc_mmc_bus_power, 79 .bus_clock = dwc_mmc_bus_clock, 80 .bus_width = dwc_mmc_bus_width, 81 .bus_rod = dwc_mmc_bus_rod, 82 .exec_command = dwc_mmc_exec_command, 83 .card_enable_intr = dwc_mmc_card_enable_intr, 84 .card_intr_ack = dwc_mmc_card_intr_ack, 85}; 86 87#define MMC_WRITE(sc, reg, val) \ 88 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 89#define MMC_READ(sc, reg) \ 90 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 91 92void 93dwc_mmc_init(struct dwc_mmc_softc *sc) 94{ 95 struct sdmmcbus_attach_args saa; 96 97 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO); 98 cv_init(&sc->sc_intr_cv, "dwcmmcirq"); 99 100 dwc_mmc_host_reset(sc); 101 dwc_mmc_bus_width(sc, 1); 102 103 memset(&saa, 0, sizeof(saa)); 104 saa.saa_busname = "sdmmc"; 105 saa.saa_sct = &dwc_mmc_chip_functions; 106 saa.saa_sch = sc; 107 saa.saa_clkmin = 400; 108 if (sc->sc_clock_max) { 109 saa.saa_clkmax = sc->sc_clock_max; 110 } else { 111 saa.saa_clkmax = sc->sc_clock_freq / 1000; 112 } 113 saa.saa_caps = SMC_CAPS_4BIT_MODE| 114 SMC_CAPS_8BIT_MODE| 115 SMC_CAPS_SD_HIGHSPEED| 116 SMC_CAPS_MMC_HIGHSPEED| 117 SMC_CAPS_AUTO_STOP; 118 119#if notyet 120 saa.saa_dmat = sc->sc_dmat; 121 saa.saa_caps |= SMC_CAPS_DMA| 122 SMC_CAPS_MULTI_SEG_DMA; 123#endif 124 125 sc->sc_sdmmc_dev = config_found(sc->sc_dev, &saa, NULL); 126} 127 128int 129dwc_mmc_intr(void *priv) 130{ 131 struct dwc_mmc_softc *sc = priv; 132 uint32_t mint, rint; 133 134 mutex_enter(&sc->sc_intr_lock); 135 rint = MMC_READ(sc, DWC_MMC_RINTSTS_REG); 136 mint = MMC_READ(sc, DWC_MMC_MINTSTS_REG); 137 if (!rint && !mint) { 138 mutex_exit(&sc->sc_intr_lock); 139 return 0; 140 } 141 MMC_WRITE(sc, DWC_MMC_RINTSTS_REG, rint); 142 MMC_WRITE(sc, DWC_MMC_MINTSTS_REG, mint); 143 144#ifdef DWC_MMC_DEBUG 145 device_printf(sc->sc_dev, "mint %#x rint %#x\n", mint, rint); 146#endif 147 148 if (rint & DWC_MMC_INT_CARDDET) { 149 rint &= ~DWC_MMC_INT_CARDDET; 150 if (sc->sc_sdmmc_dev) { 151 sdmmc_needs_discover(sc->sc_sdmmc_dev); 152 } 153 } 154 155 if (rint) { 156 sc->sc_intr_rint |= rint; 157 cv_broadcast(&sc->sc_intr_cv); 158 } 159 160 mutex_exit(&sc->sc_intr_lock); 161 162 return 1; 163} 164 165static int 166dwc_mmc_set_clock(struct dwc_mmc_softc *sc, u_int freq) 167{ 168 u_int pll_freq, clk_div; 169 170 pll_freq = sc->sc_clock_freq / 1000; 171 clk_div = (pll_freq / freq) >> 1; 172 if (pll_freq % freq) 173 clk_div++; 174 175 MMC_WRITE(sc, DWC_MMC_CLKDIV_REG, 176 __SHIFTIN(clk_div, DWC_MMC_CLKDIV_CLK_DIVIDER0)); 177 return dwc_mmc_update_clock(sc); 178} 179 180static int 181dwc_mmc_update_clock(struct dwc_mmc_softc *sc) 182{ 183 uint32_t cmd; 184 int retry; 185 186 cmd = DWC_MMC_CMD_START_CMD | 187 DWC_MMC_CMD_UPDATE_CLOCK_REGS_ONLY | 188 DWC_MMC_CMD_WAIT_PRVDATA_COMPLETE; 189 190 if (sc->sc_flags & DWC_MMC_F_USE_HOLD_REG) 191 cmd |= DWC_MMC_CMD_USE_HOLD_REG; 192 193 MMC_WRITE(sc, DWC_MMC_CMD_REG, cmd); 194 retry = 0xfffff; 195 while (--retry > 0) { 196 cmd = MMC_READ(sc, DWC_MMC_CMD_REG); 197 if ((cmd & DWC_MMC_CMD_START_CMD) == 0) 198 break; 199 delay(10); 200 } 201 202 if (retry == 0) { 203 device_printf(sc->sc_dev, "timeout updating clock\n"); 204 return ETIMEDOUT; 205 } 206 207 return 0; 208} 209 210static int 211dwc_mmc_wait_rint(struct dwc_mmc_softc *sc, uint32_t mask, int timeout) 212{ 213 int retry, error; 214 215 KASSERT(mutex_owned(&sc->sc_intr_lock)); 216 217 if (sc->sc_intr_rint & mask) 218 return 0; 219 220 retry = timeout / hz; 221 222 while (retry > 0) { 223 error = cv_timedwait(&sc->sc_intr_cv, &sc->sc_intr_lock, hz); 224 if (error && error != EWOULDBLOCK) 225 return error; 226 if (sc->sc_intr_rint & mask) 227 return 0; 228 --retry; 229 } 230 231 return ETIMEDOUT; 232} 233 234static int 235dwc_mmc_pio_wait(struct dwc_mmc_softc *sc, struct sdmmc_command *cmd) 236{ 237 int retry = 0xfffff; 238 uint32_t bit = (cmd->c_flags & SCF_CMD_READ) ? 239 DWC_MMC_STATUS_FIFO_EMPTY : DWC_MMC_STATUS_FIFO_FULL; 240 241 while (--retry > 0) { 242 uint32_t status = MMC_READ(sc, DWC_MMC_STATUS_REG); 243 if (!(status & bit)) 244 return 0; 245 delay(10); 246 } 247 248#ifdef DWC_MMC_DEBUG 249 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 250#endif 251 252 return ETIMEDOUT; 253} 254 255static int 256dwc_mmc_pio_transfer(struct dwc_mmc_softc *sc, struct sdmmc_command *cmd) 257{ 258 uint32_t *datap = (uint32_t *)cmd->c_data; 259 int i; 260 261 for (i = 0; i < (cmd->c_resid >> 2); i++) { 262 if (dwc_mmc_pio_wait(sc, cmd)) 263 return ETIMEDOUT; 264 if (cmd->c_flags & SCF_CMD_READ) { 265 datap[i] = MMC_READ(sc, DWC_MMC_FIFO_BASE_REG); 266 } else { 267 MMC_WRITE(sc, DWC_MMC_FIFO_BASE_REG, datap[i]); 268 } 269 } 270 271 return 0; 272} 273 274static int 275dwc_mmc_host_reset(sdmmc_chipset_handle_t sch) 276{ 277 struct dwc_mmc_softc *sc = sch; 278 int retry = 1000; 279 uint32_t ctrl, fifoth; 280 uint32_t rx_wmark, tx_wmark; 281 282 if (sc->sc_flags & DWC_MMC_F_PWREN_CLEAR) { 283 MMC_WRITE(sc, DWC_MMC_PWREN_REG, 0); 284 } else { 285 MMC_WRITE(sc, DWC_MMC_PWREN_REG, DWC_MMC_PWREN_POWER_ENABLE); 286 } 287 288 MMC_WRITE(sc, DWC_MMC_CTRL_REG, 289 MMC_READ(sc, DWC_MMC_CTRL_REG) | DWC_MMC_CTRL_RESET_ALL); 290 while (--retry > 0) { 291 ctrl = MMC_READ(sc, DWC_MMC_CTRL_REG); 292 if ((ctrl & DWC_MMC_CTRL_RESET_ALL) == 0) 293 break; 294 delay(100); 295 } 296 297 MMC_WRITE(sc, DWC_MMC_CLKSRC_REG, 0); 298 299 MMC_WRITE(sc, DWC_MMC_TMOUT_REG, 0xffffff40); 300 MMC_WRITE(sc, DWC_MMC_RINTSTS_REG, 0xffffffff); 301 302 MMC_WRITE(sc, DWC_MMC_INTMASK_REG, 303 DWC_MMC_INT_CD | DWC_MMC_INT_ACD | DWC_MMC_INT_DTO | 304 DWC_MMC_INT_ERROR | DWC_MMC_INT_CARDDET | 305 DWC_MMC_INT_RXDR | DWC_MMC_INT_TXDR); 306 307 rx_wmark = (sc->sc_fifo_depth / 2) - 1; 308 tx_wmark = sc->sc_fifo_depth / 2; 309 fifoth = __SHIFTIN(DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE_16, 310 DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE); 311 fifoth |= __SHIFTIN(rx_wmark, DWC_MMC_FIFOTH_RX_WMARK); 312 fifoth |= __SHIFTIN(tx_wmark, DWC_MMC_FIFOTH_TX_WMARK); 313 MMC_WRITE(sc, DWC_MMC_FIFOTH_REG, fifoth); 314 315 ctrl = MMC_READ(sc, DWC_MMC_CTRL_REG); 316 ctrl |= DWC_MMC_CTRL_INT_ENABLE; 317 MMC_WRITE(sc, DWC_MMC_CTRL_REG, ctrl); 318 319 return 0; 320} 321 322static uint32_t 323dwc_mmc_host_ocr(sdmmc_chipset_handle_t sch) 324{ 325 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V; 326} 327 328static int 329dwc_mmc_host_maxblklen(sdmmc_chipset_handle_t sch) 330{ 331 return 32768; 332} 333 334static int 335dwc_mmc_card_detect(sdmmc_chipset_handle_t sch) 336{ 337 struct dwc_mmc_softc *sc = sch; 338 uint32_t cdetect; 339 340 cdetect = MMC_READ(sc, DWC_MMC_CDETECT_REG); 341 return !!(cdetect & DWC_MMC_CDETECT_CARD_DETECT_N); 342} 343 344static int 345dwc_mmc_write_protect(sdmmc_chipset_handle_t sch) 346{ 347 struct dwc_mmc_softc *sc = sch; 348 uint32_t wrtprt; 349 350 wrtprt = MMC_READ(sc, DWC_MMC_WRTPRT_REG); 351 return !!(wrtprt & DWC_MMC_WRTPRT_WRITE_PROTECT); 352} 353 354static int 355dwc_mmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 356{ 357 return 0; 358} 359 360static int 361dwc_mmc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 362{ 363 struct dwc_mmc_softc *sc = sch; 364 uint32_t clkena; 365 366#ifdef DWC_MMC_DEBUG 367 device_printf(sc->sc_dev, "%s: freq %d\n", __func__, freq); 368#endif 369 370 MMC_WRITE(sc, DWC_MMC_CLKENA_REG, 0); 371 if (dwc_mmc_update_clock(sc) != 0) 372 return ETIMEDOUT; 373 374 if (freq) { 375 if (dwc_mmc_set_clock(sc, freq) != 0) 376 return EIO; 377 378 clkena = DWC_MMC_CLKENA_CCLK_ENABLE; 379 clkena |= DWC_MMC_CLKENA_CCLK_LOW_POWER; /* XXX SD/MMC only */ 380 MMC_WRITE(sc, DWC_MMC_CLKENA_REG, clkena); 381 if (dwc_mmc_update_clock(sc) != 0) 382 return ETIMEDOUT; 383 } 384 385 delay(1000); 386 387 sc->sc_cur_freq = freq; 388 389 return 0; 390} 391 392static int 393dwc_mmc_bus_width(sdmmc_chipset_handle_t sch, int width) 394{ 395 struct dwc_mmc_softc *sc = sch; 396 uint32_t ctype; 397 398 switch (width) { 399 case 1: 400 ctype = DWC_MMC_CTYPE_CARD_WIDTH_1; 401 break; 402 case 4: 403 ctype = DWC_MMC_CTYPE_CARD_WIDTH_4; 404 break; 405 case 8: 406 ctype = DWC_MMC_CTYPE_CARD_WIDTH_8; 407 break; 408 default: 409 return EINVAL; 410 } 411 412 MMC_WRITE(sc, DWC_MMC_CTYPE_REG, ctype); 413 414 return 0; 415} 416 417static int 418dwc_mmc_bus_rod(sdmmc_chipset_handle_t sch, int on) 419{ 420 return ENOTSUP; 421} 422 423static void 424dwc_mmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 425{ 426 struct dwc_mmc_softc *sc = sch; 427 uint32_t cmdval = DWC_MMC_CMD_START_CMD; 428 uint32_t ctrl; 429 430#ifdef DWC_MMC_DEBUG 431 device_printf(sc->sc_dev, "exec opcode=%d flags=%#x\n", 432 cmd->c_opcode, cmd->c_flags); 433#endif 434 435 if (sc->sc_flags & DWC_MMC_F_FORCE_CLK) { 436 cmd->c_error = dwc_mmc_bus_clock(sc, sc->sc_cur_freq); 437 if (cmd->c_error) 438 return; 439 } 440 441 if (sc->sc_flags & DWC_MMC_F_USE_HOLD_REG) 442 cmdval |= DWC_MMC_CMD_USE_HOLD_REG; 443 444 mutex_enter(&sc->sc_intr_lock); 445 if (cmd->c_opcode == 0) 446 cmdval |= DWC_MMC_CMD_SEND_INIT; 447 if (cmd->c_flags & SCF_RSP_PRESENT) 448 cmdval |= DWC_MMC_CMD_RESP_EXPECTED; 449 if (cmd->c_flags & SCF_RSP_136) 450 cmdval |= DWC_MMC_CMD_RESP_LEN; 451 if (cmd->c_flags & SCF_RSP_CRC) 452 cmdval |= DWC_MMC_CMD_CHECK_RESP_CRC; 453 454 if (cmd->c_datalen > 0) { 455 unsigned int nblks; 456 457 cmdval |= DWC_MMC_CMD_DATA_EXPECTED; 458 cmdval |= DWC_MMC_CMD_WAIT_PRVDATA_COMPLETE; 459 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) { 460 cmdval |= DWC_MMC_CMD_WR; 461 } 462 463 nblks = cmd->c_datalen / cmd->c_blklen; 464 if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0) 465 ++nblks; 466 467 if (nblks > 1) { 468 cmdval |= DWC_MMC_CMD_SEND_AUTO_STOP; 469 } 470 471 MMC_WRITE(sc, DWC_MMC_BLKSIZ_REG, cmd->c_blklen); 472 MMC_WRITE(sc, DWC_MMC_BYTCNT_REG, nblks * cmd->c_blklen); 473 } 474 475 sc->sc_intr_rint = 0; 476 477 MMC_WRITE(sc, DWC_MMC_CMDARG_REG, cmd->c_arg); 478 479 cmd->c_resid = cmd->c_datalen; 480 MMC_WRITE(sc, DWC_MMC_CMD_REG, cmdval | cmd->c_opcode); 481 if (cmd->c_datalen > 0) { 482 cmd->c_error = dwc_mmc_pio_transfer(sc, cmd); 483 if (cmd->c_error) { 484 goto done; 485 } 486 } 487 488 cmd->c_error = dwc_mmc_wait_rint(sc, 489 DWC_MMC_INT_ERROR|DWC_MMC_INT_CD, hz * 10); 490 if (cmd->c_error == 0 && (sc->sc_intr_rint & DWC_MMC_INT_ERROR)) { 491#ifdef DWC_MMC_DEBUG 492 device_printf(sc->sc_dev, "%s: rint %#x\n", __func__, 493 sc->sc_intr_rint); 494#endif 495 if (sc->sc_intr_rint & DWC_MMC_INT_RTO) { 496 cmd->c_error = ETIMEDOUT; 497 } else { 498 cmd->c_error = EIO; 499 } 500 } 501 if (cmd->c_error) { 502 goto done; 503 } 504 505 if (cmd->c_datalen > 0) { 506 cmd->c_error = dwc_mmc_wait_rint(sc, 507 DWC_MMC_INT_ERROR|DWC_MMC_INT_ACD|DWC_MMC_INT_DTO, 508 hz * 10); 509 if (cmd->c_error == 0 && 510 (sc->sc_intr_rint & DWC_MMC_INT_ERROR)) { 511#ifdef DWC_MMC_DEBUG 512 device_printf(sc->sc_dev, "%s: rint2 %#x\n", __func__, 513 sc->sc_intr_rint); 514#endif 515 cmd->c_error = ETIMEDOUT; 516 } 517 if (cmd->c_error) { 518 goto done; 519 } 520 } 521 522 if (cmd->c_flags & SCF_RSP_PRESENT) { 523 if (cmd->c_flags & SCF_RSP_136) { 524 cmd->c_resp[0] = MMC_READ(sc, DWC_MMC_RESP0_REG); 525 cmd->c_resp[1] = MMC_READ(sc, DWC_MMC_RESP1_REG); 526 cmd->c_resp[2] = MMC_READ(sc, DWC_MMC_RESP2_REG); 527 cmd->c_resp[3] = MMC_READ(sc, DWC_MMC_RESP3_REG); 528 if (cmd->c_flags & SCF_RSP_CRC) { 529 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 530 (cmd->c_resp[1] << 24); 531 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 532 (cmd->c_resp[2] << 24); 533 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 534 (cmd->c_resp[3] << 24); 535 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 536 } 537 } else { 538 cmd->c_resp[0] = MMC_READ(sc, DWC_MMC_RESP0_REG); 539 } 540 } 541 542done: 543 cmd->c_flags |= SCF_ITSDONE; 544 mutex_exit(&sc->sc_intr_lock); 545 546 ctrl = MMC_READ(sc, DWC_MMC_CTRL_REG); 547 ctrl |= DWC_MMC_CTRL_FIFO_RESET; 548 MMC_WRITE(sc, DWC_MMC_CTRL_REG, ctrl); 549} 550 551static void 552dwc_mmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 553{ 554} 555 556static void 557dwc_mmc_card_intr_ack(sdmmc_chipset_handle_t sch) 558{ 559} 560 561void 562dwc_mmc_dump_regs(void) 563{ 564 static const struct { 565 const char *name; 566 unsigned int reg; 567 } regs[] = { 568 { "CTRL", DWC_MMC_CTRL_REG }, 569 { "PWREN", DWC_MMC_PWREN_REG }, 570 { "CLKDIV", DWC_MMC_CLKDIV_REG }, 571 { "CLKENA", DWC_MMC_CLKENA_REG }, 572 { "TMOUT", DWC_MMC_TMOUT_REG }, 573 { "CTYPE", DWC_MMC_CTYPE_REG }, 574 { "BLKSIZ", DWC_MMC_BLKSIZ_REG }, 575 { "BYTCNT", DWC_MMC_BYTCNT_REG }, 576 { "INTMASK", DWC_MMC_INTMASK_REG }, 577 { "MINTSTS", DWC_MMC_MINTSTS_REG }, 578 { "RINTSTS", DWC_MMC_RINTSTS_REG }, 579 { "STATUS", DWC_MMC_STATUS_REG }, 580 { "CDETECT", DWC_MMC_CDETECT_REG }, 581 { "WRTPRT", DWC_MMC_WRTPRT_REG }, 582 { "USRID", DWC_MMC_USRID_REG }, 583 { "VERID", DWC_MMC_VERID_REG }, 584 { "RST", DWC_MMC_RST_REG }, 585 { "BACK_END_POWER", DWC_MMC_BACK_END_POWER_REG }, 586 }; 587 device_t self = device_find_by_driver_unit("dwcmmc", 0); 588 if (self == NULL) 589 return; 590 struct dwc_mmc_softc *sc = device_private(self); 591 int i; 592 593 for (i = 0; i < __arraycount(regs); i++) { 594 device_printf(sc->sc_dev, "%s: %#x\n", regs[i].name, 595 MMC_READ(sc, regs[i].reg)); 596 } 597} 598