1/* $NetBSD: dwc_gmac_var.h,v 1.19 2024/02/27 08:33:06 skrll Exp $ */
2
3/*-
4 * Copyright (c) 2013, 2014 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Matt Thomas of 3am Software Foundry and Martin Husemann.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#ifdef _KERNEL_OPT
33#include "opt_net_mpsafe.h"
34#endif
35
36/* Use DWCGMAC_MPSAFE inside the front-ends for interrupt handlers.  */
37#ifdef NET_MPSAFE
38#define DWCGMAC_MPSAFE	1
39#endif
40
41#ifdef DWCGMAC_MPSAFE
42#define DWCGMAC_FDT_INTR_MPSAFE FDT_INTR_MPSAFE
43#else
44#define DWCGMAC_FDT_INTR_MPSAFE 0
45#endif
46
47/*
48 * Rx and Tx Ring counts that map into single 4K page with 16byte descriptor
49 * size. For Rx a full mbuf cluster is allocated for each which consumes
50 * around 512k Byte of RAM for mbuf clusters.
51 * XXX Maybe fine-tune later, or reconsider unsharing of RX/TX dmamap.
52 */
53#define		AWGE_RX_RING_COUNT	256
54#define		AWGE_TX_RING_COUNT	256
55#define		AWGE_TOTAL_RING_COUNT	\
56			(AWGE_RX_RING_COUNT + AWGE_TX_RING_COUNT)
57
58#define		AWGE_MAX_PACKET		0x7ff
59
60struct dwc_gmac_dev_dmadesc;
61
62struct dwc_gmac_desc_methods {
63	void (*tx_init_flags)(struct dwc_gmac_dev_dmadesc *);
64	void (*tx_set_owned_by_dev)(struct dwc_gmac_dev_dmadesc *);
65	int  (*tx_is_owned_by_dev)(struct dwc_gmac_dev_dmadesc *);
66	void (*tx_set_len)(struct dwc_gmac_dev_dmadesc *, int);
67	void (*tx_set_first_frag)(struct dwc_gmac_dev_dmadesc *);
68	void (*tx_set_last_frag)(struct dwc_gmac_dev_dmadesc *);
69
70	void (*rx_init_flags)(struct dwc_gmac_dev_dmadesc *);
71	void (*rx_set_owned_by_dev)(struct dwc_gmac_dev_dmadesc *);
72	int  (*rx_is_owned_by_dev)(struct dwc_gmac_dev_dmadesc *);
73	void (*rx_set_len)(struct dwc_gmac_dev_dmadesc *, int);
74	uint32_t  (*rx_get_len)(struct dwc_gmac_dev_dmadesc *);
75	int  (*rx_has_error)(struct dwc_gmac_dev_dmadesc *);
76};
77
78struct dwc_gmac_rx_data {
79	bus_dmamap_t	rd_map;
80	struct mbuf	*rd_m;
81};
82
83struct dwc_gmac_tx_data {
84	bus_dmamap_t	td_map;
85	bus_dmamap_t	td_active;
86	struct mbuf	*td_m;
87};
88
89struct dwc_gmac_tx_ring {
90	bus_addr_t			t_physaddr; /* PA of TX ring start */
91	struct dwc_gmac_dev_dmadesc	*t_desc;    /* VA of TX ring start */
92	struct dwc_gmac_tx_data	t_data[AWGE_TX_RING_COUNT];
93	int				t_cur, t_next, t_queued;
94	kmutex_t			t_mtx;
95};
96
97struct dwc_gmac_rx_ring {
98	bus_addr_t			r_physaddr; /* PA of RX ring start */
99	struct dwc_gmac_dev_dmadesc	*r_desc;    /* VA of RX ring start */
100	struct dwc_gmac_rx_data	r_data[AWGE_RX_RING_COUNT];
101	int				r_cur, r_next;
102	kmutex_t			r_mtx;
103};
104
105struct dwc_gmac_softc {
106	device_t sc_dev;
107	bus_space_tag_t sc_bst;
108	bus_space_handle_t sc_bsh;
109	bus_dma_tag_t sc_dmat;
110	uint32_t sc_flags;
111#define	DWC_GMAC_FORCE_THRESH_DMA_MODE	__BIT(0)/* force DMA to use threshold mode */
112	struct ethercom sc_ec;
113	struct mii_data sc_mii;
114	kmutex_t sc_mdio_lock;
115	bus_dmamap_t sc_dma_ring_map;		/* common dma memory for RX */
116	bus_dma_segment_t sc_dma_ring_seg;	/* and TX ring */
117	struct dwc_gmac_rx_ring sc_rxq;
118	struct dwc_gmac_tx_ring sc_txq;
119	const struct dwc_gmac_desc_methods *sc_descm;
120	u_short sc_if_flags;			/* shadow of ether flags */
121	uint16_t sc_mii_clk;
122	bool sc_txbusy;
123	bool sc_stopping;
124	krndsource_t rnd_source;
125	kmutex_t *sc_lock;			/* lock for softc operations */
126
127	struct if_percpuq *sc_ipq;		/* softint-based input queues */
128
129	void (*sc_set_speed)(struct dwc_gmac_softc *, int);
130};
131
132int dwc_gmac_attach(struct dwc_gmac_softc*, int /*phy_id*/,
133    uint32_t /*mii_clk*/);
134int dwc_gmac_intr(struct dwc_gmac_softc*);
135