1/*	$NetBSD: cpc700reg.h,v 1.4 2005/12/11 12:21:26 christos Exp $	*/
2
3/*
4 * Copyright (c) 2002 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Lennart Augustsson (lennart@augustsson.net) at Sandburst Corp.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32/* PCI memory space */
33#define CPC_PCI_MEM_BASE	0x80000000
34#define CPC_PCI_MEM_END		0xf7ffffff
35
36/* PCI IO space */
37#define CPC_PCI_IO_BASE		0xf8000000
38#define CPC_PCI_IO_START	0xf8800000 /* for allocation */
39#define CPC_PCI_IO_END		0xfbffffff
40
41/* PCI config space */
42#define CPC_PCICFGADR		0xfec00000
43#define   CPC_PCI_CONFIG_ENABLE		0x80000000
44#define CPC_PCICFGDATA		0xfec00004
45
46/* Config space regs */
47#define CPC_PCI_BRDGERR		0x48
48#define CPC_PCI_CLEARERR	0x0000ff00
49
50#define CPC_BRIDGE_OPTIONS2	0x60
51#define  CPC_BRIDGE_O2_ILAT_MASK	0x00f8
52#define  CPC_BRIDGE_O2_ILAT_SHIFT	3
53#define  CPC_BRIDGE_O2_ILAT_PRIM_ASYNC	18
54#define  CPC_BRIDGE_O2_SLAT_MASK	0x0f00
55#define  CPC_BRIDGE_O2_SLAT_SHIFT	8
56#define  CPC_BRIDGE_O2_2LAT_PRIM_ASYNC	2
57
58/* PCI interrupt acknowledge & special cycle */
59#define CPC_INTR_ACK		0xfed00000
60
61#define CPC_PMM0_LOCAL		0xff400000
62#define CPC_PMM0_MASK_ATTR	0xff400004
63#define CPC_PMM0_PCI_LOW	0xff400008
64#define CPC_PMM0_PCI_HIGH	0xff40000c
65#define CPC_PMM1_LOCAL		0xff400010
66#define CPC_PMM1_MASK_ATTR	0xff400014
67#define CPC_PMM1_PCI_LOW	0xff400018
68#define CPC_PMM1_PCI_HIGH	0xff40001c
69#define CPC_PMM2_LOCAL		0xff400020
70#define CPC_PMM2_MASK_ATTR	0xff400024
71#define CPC_PMM2_PCI_LOW	0xff400028
72#define CPC_PMM2_PCI_HIGH	0xff40002c
73#define CPC_PTM1_LOCAL		0xff400030
74#define CPC_PTM1_MEMSIZE	0xff400034
75#define CPC_PTM2_LOCAL		0xff400038
76#define CPC_PTM2_MEMSIZE	0xff40003c
77
78/* serial ports */
79#define CPC_COM0		0xff600300
80#define CPC_COM1		0xff600400
81#define CPC_COM_SPEED(bus)	((bus) / (2 * 4))
82
83/* processor interface registers */
84#define CPC_PIF_CFGADR		0xff500000
85#define  CPC_PIF_CFG_PRIFOPT1		0x00
86#define  CPC_PIF_CFG_ERRDET1		0x04
87#define  CPC_PIF_CFG_ERREN1		0x08
88#define  CPC_PIF_CFG_CPUERAD		0x0c
89#define  CPC_PIF_CFG_CPUERAT		0x10
90#define  CPC_PIF_CFG_PLBMIFOPT		0x18
91#define  CPC_PIF_CFG_PLBMTLSA1		0x20
92#define  CPC_PIF_CFG_PLBMTLEA1		0x24
93#define  CPC_PIF_CFG_PLBMTLSA2		0x28
94#define  CPC_PIF_CFG_PLBMTLEA2		0x2c
95#define  CPC_PIF_CFG_PLBMTLSA3		0x30
96#define  CPC_PIF_CFG_PLBMTLEA3		0x34
97#define  CPC_PIF_CFG_PLBSNSSA0		0x38
98#define  CPC_PIF_CFG_PLBSNSEA0		0x3c
99#define  CPC_PIF_CFG_BESR		0x40
100#define  CPC_PIF_CFG_BESRSET		0x44
101#define  CPC_PIF_CFG_BEAR		0x4c
102#define  CPC_PIF_CFG_PLBSWRINT		0x80
103#define CPC_PIF_CFGDATA		0xff500004
104
105/* interrupt controller */
106#define CPC_UIC_BASE		0xff500880
107#define CPC_UIC_SIZE		0x00000024
108#define CPC_UIC_SR		0x00000000 /* UIC status (read/clear) */
109#define CPC_UIC_SRS		0x00000004 /* UIC status (set) */
110#define CPC_UIC_ER		0x00000008 /* UIC enable */
111#define CPC_UIC_CR		0x0000000c /* UIC critical */
112#define CPC_UIC_PR		0x00000010 /* UIC polarity 0=low, 1=high*/
113#define CPC_UIC_TR		0x00000014 /* UIC trigger 0=level; 1=edge */
114#define CPC_UIC_MSR		0x00000018 /* UIC masked status */
115#define CPC_UIC_VR		0x0000001c /* UIC vector */
116#define CPC_UIC_VCR		0x00000020 /* UIC vector configuration */
117#define   CPC_UIC_CVR_PRI	  0x00000001 /* 0=intr31 high, 1=intr0 high */
118/*
119 * if intr0 high then interrupt vector at (vcr&~3) + N*512
120 * if intr31 high then interrupt vector at (vcr&~3) + (31-N)*512
121 */
122
123/* UIC interrupt bits.  Note, MSB is bit 0 */
124/* Internal */
125#define CPC_IB_ECC		0
126#define CPC_IB_PCI_WR_RANGE	1
127#define CPC_IB_PCI_WR_CMD	2
128#define CPC_IB_UART_0		3
129#define CPC_IB_UART_1		4
130#define CPC_IB_IIC_0		5
131#define CPC_IB_IIC_1		6
132/* 6-16 GPT compare&capture */
133/* 20-31 external */
134#define CPC_IB_EXT0		20
135#define CPC_IB_EXT1		21
136#define CPC_IB_EXT2		22
137#define CPC_IB_EXT3		23
138#define CPC_IB_EXT4		24
139#define CPC_IB_EXT5		25
140#define CPC_IB_EXT6		26
141#define CPC_IB_EXT7		27
142#define CPC_IB_EXT8		28
143#define CPC_IB_EXT9		29
144#define CPC_IB_EXT10		30
145#define CPC_IB_EXT11		31
146
147#define CPC_INTR_MASK(irq) (0x80000000 >> (irq))
148
149
150/* IIC */
151#define CPC_IIC0		0xff620000
152#define CPC_IIC1		0xff630000
153#define CPC_IIC_SIZE		0x00000014
154/* offsets from base */
155#define CPC_IIC_MDBUF		0x00000000
156#define CPC_IIC_SDBUF		0x00000002
157#define CPC_IIC_LMADR		0x00000004
158#define CPC_IIC_HNADR		0x00000005
159#define CPC_IIC_CNTL		0x00000006
160#define CPC_IIC_MDCNTL		0x00000007
161#define CPC_IIC_STS		0x00000008
162#define CPC_IIC_EXTSTS		0x00000009
163#define CPC_IIC_LSADR		0x0000000a
164#define CPC_IIC_HSADR		0x0000000b
165#define CPC_IIC_CLKDIV		0x0000000c
166#define CPC_IIC_INTRMSK		0x0000000d
167#define CPC_IIC_FRCNT		0x0000000e
168#define CPC_IIC_TCNTLSS		0x0000000f
169#define CPC_IIC_DIRECTCNTL	0x00000010
170
171/* timer */
172#define CPC_TIMER		0xff650000
173#define CPC_GPTTBC		0x00000000
174