1/*	$NetBSD: si.c,v 1.64 2020/11/21 00:27:52 thorpej Exp $	*/
2
3/*-
4 * Copyright (c) 1996 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Adam Glass, David Jones, and Gordon W. Ross.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32/*
33 * This file contains only the machine-dependent parts of the
34 * Sun3 SCSI driver.  (Autoconfig stuff and DMA functions.)
35 * The machine-independent parts are in ncr5380sbc.c
36 *
37 * Supported hardware includes:
38 * Sun SCSI-3 on OBIO (Sun3/50,Sun3/60)
39 * Sun SCSI-3 on VME (Sun3/160,Sun3/260)
40 *
41 * Could be made to support the Sun3/E if someone wanted to.
42 *
43 * Note:  Both supported variants of the Sun SCSI-3 adapter have
44 * some really unusual "features" for this driver to deal with,
45 * generally related to the DMA engine.  The OBIO variant will
46 * ignore any attempt to write the FIFO count register while the
47 * SCSI bus is in DATA_IN or DATA_OUT phase.  This is dealt with
48 * by setting the FIFO count early in COMMAND or MSG_IN phase.
49 *
50 * The VME variant has a bit to enable or disable the DMA engine,
51 * but that bit also gates the interrupt line from the NCR5380!
52 * Therefore, in order to get any interrupt from the 5380, (i.e.
53 * for reselect) one must clear the DMA engine transfer count and
54 * then enable DMA.  This has the further complication that you
55 * CAN NOT touch the NCR5380 while the DMA enable bit is set, so
56 * we have to turn DMA back off before we even look at the 5380.
57 *
58 * What wonderfully whacky hardware this is!
59 *
60 * Credits, history:
61 *
62 * David Jones wrote the initial version of this module, which
63 * included support for the VME adapter only. (no reselection).
64 *
65 * Gordon Ross added support for the OBIO adapter, and re-worked
66 * both the VME and OBIO code to support disconnect/reselect.
67 * (Required figuring out the hardware "features" noted above.)
68 *
69 * The autoconfiguration boilerplate came from Adam Glass.
70 */
71
72#include <sys/cdefs.h>
73__KERNEL_RCSID(0, "$NetBSD: si.c,v 1.64 2020/11/21 00:27:52 thorpej Exp $");
74
75#include <sys/param.h>
76#include <sys/systm.h>
77#include <sys/errno.h>
78#include <sys/kernel.h>
79#include <sys/kmem.h>
80#include <sys/device.h>
81#include <sys/buf.h>
82#include <sys/proc.h>
83
84#include <dev/scsipi/scsi_all.h>
85#include <dev/scsipi/scsipi_all.h>
86#include <dev/scsipi/scsipi_debug.h>
87#include <dev/scsipi/scsiconf.h>
88
89#include <machine/autoconf.h>
90#include <machine/bus.h>
91#include <machine/dvma.h>
92
93/* #define DEBUG XXX */
94
95#include <dev/ic/ncr5380reg.h>
96#include <dev/ic/ncr5380var.h>
97
98#include "sireg.h"
99#include "sivar.h"
100
101/*
102 * Transfers smaller than this are done using PIO
103 * (on assumption they're not worth DMA overhead)
104 */
105#define	MIN_DMA_LEN 128
106
107int si_debug = 0;
108#ifdef	DEBUG
109#endif
110
111/* How long to wait for DMA before declaring an error. */
112int si_dma_intr_timo = 500;	/* ticks (sec. X 100) */
113
114static void	si_minphys(struct buf *);
115
116/*
117 * New-style autoconfig attachment. The cfattach
118 * structures are in si_obio.c and si_vme.c
119 */
120
121void
122si_attach(struct si_softc *sc)
123{
124	struct ncr5380_softc *ncr_sc = &sc->ncr_sc;
125	volatile struct si_regs *regs = sc->sc_regs;
126	int i;
127
128	/*
129	 * Support the "options" (config file flags).
130	 * Disconnect/reselect is a per-target mask.
131	 * Interrupts and DMA are per-controller.
132	 */
133	ncr_sc->sc_no_disconnect =
134	    (sc->sc_options & SI_NO_DISCONNECT);
135	ncr_sc->sc_parity_disable =
136	    (sc->sc_options & SI_NO_PARITY_CHK) >> 8;
137	if (sc->sc_options & SI_FORCE_POLLING)
138		ncr_sc->sc_flags |= NCR5380_FORCE_POLLING;
139
140#if 1	/* XXX - Temporary */
141	/* XXX - In case we think DMA is completely broken... */
142	if (sc->sc_options & SI_DISABLE_DMA) {
143		/* Override this function pointer. */
144		ncr_sc->sc_dma_alloc = NULL;
145	}
146#endif
147	ncr_sc->sc_min_dma_len = MIN_DMA_LEN;
148
149	/*
150	 * Initialize fields used by the MI code
151	 */
152	ncr_sc->sci_r0 = &regs->sci.sci_r0;
153	ncr_sc->sci_r1 = &regs->sci.sci_r1;
154	ncr_sc->sci_r2 = &regs->sci.sci_r2;
155	ncr_sc->sci_r3 = &regs->sci.sci_r3;
156	ncr_sc->sci_r4 = &regs->sci.sci_r4;
157	ncr_sc->sci_r5 = &regs->sci.sci_r5;
158	ncr_sc->sci_r6 = &regs->sci.sci_r6;
159	ncr_sc->sci_r7 = &regs->sci.sci_r7;
160
161	ncr_sc->sc_rev = NCR_VARIANT_NCR5380;
162
163	/*
164	 * Allocate DMA handles.
165	 */
166	i = SCI_OPENINGS * sizeof(struct si_dma_handle);
167	sc->sc_dma = kmem_alloc(i, KM_SLEEP);
168	for (i = 0; i < SCI_OPENINGS; i++)
169		sc->sc_dma[i].dh_flags = 0;
170
171	ncr_sc->sc_channel.chan_id = 7;
172	ncr_sc->sc_adapter.adapt_minphys = si_minphys;
173
174	/*
175	 *  Initialize si board itself.
176	 */
177	ncr5380_attach(ncr_sc);
178}
179
180static void
181si_minphys(struct buf *bp)
182{
183
184	if (bp->b_bcount > MAX_DMA_LEN) {
185#ifdef	DEBUG
186		if (si_debug) {
187			printf("%s len = 0x%x.\n", __func__, bp->b_bcount);
188			Debugger();
189		}
190#endif
191		bp->b_bcount = MAX_DMA_LEN;
192	}
193	minphys(bp);
194}
195
196
197#define CSR_WANT (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \
198	SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR )
199
200int
201si_intr(void *arg)
202{
203	struct si_softc *sc = arg;
204	volatile struct si_regs *si = sc->sc_regs;
205	int dma_error, claimed;
206	u_short csr;
207
208	claimed = 0;
209	dma_error = 0;
210
211	/* SBC interrupt? DMA interrupt? */
212	csr = si->si_csr;
213	NCR_TRACE("si_intr: csr=0x%x\n", csr);
214
215	if (csr & SI_CSR_DMA_CONFLICT) {
216		dma_error |= SI_CSR_DMA_CONFLICT;
217		printf("%s: DMA conflict\n", __func__);
218	}
219	if (csr & SI_CSR_DMA_BUS_ERR) {
220		dma_error |= SI_CSR_DMA_BUS_ERR;
221		printf("%s: DMA bus error\n", __func__);
222	}
223	if (dma_error) {
224		if (sc->ncr_sc.sc_state & NCR_DOINGDMA)
225			sc->ncr_sc.sc_state |= NCR_ABORTING;
226		/* Make sure we will call the main isr. */
227		csr |= SI_CSR_DMA_IP;
228	}
229
230	if (csr & (SI_CSR_SBC_IP | SI_CSR_DMA_IP)) {
231		claimed = ncr5380_intr(&sc->ncr_sc);
232#ifdef	DEBUG
233		if (!claimed) {
234			printf("%s: spurious from SBC\n", __func__);
235			if (si_debug & 4)
236				Debugger();	/* XXX */
237		}
238#endif
239		/* Yes, we DID cause this interrupt. */
240		claimed = 1;
241	}
242
243	return claimed;
244}
245
246
247/*****************************************************************
248 * Common functions for DMA
249 ****************************************************************/
250
251/*
252 * Allocate a DMA handle and put it in sc->sc_dma.  Prepare
253 * for DMA transfer.  On the Sun3, this means mapping the buffer
254 * into DVMA space.  dvma_mapin() flushes the cache for us.
255 */
256void
257si_dma_alloc(struct ncr5380_softc *ncr_sc)
258{
259	struct si_softc *sc = (struct si_softc *)ncr_sc;
260	struct sci_req *sr = ncr_sc->sc_current;
261	struct scsipi_xfer *xs = sr->sr_xs;
262	struct si_dma_handle *dh;
263	int i, xlen;
264	void *addr;
265
266#ifdef	DIAGNOSTIC
267	if (sr->sr_dma_hand != NULL)
268		panic("%s: already have DMA handle", __func__);
269#endif
270
271	addr = ncr_sc->sc_dataptr;
272	xlen = ncr_sc->sc_datalen;
273
274	/* If the DMA start addr is misaligned then do PIO */
275	if (((vaddr_t)addr & 1) || (xlen & 1)) {
276		printf("%s: misaligned.\n", __func__);
277		return;
278	}
279
280	/* Make sure our caller checked sc_min_dma_len. */
281	if (xlen < MIN_DMA_LEN)
282		panic("%s: xlen=0x%x", __func__, xlen);
283
284	/*
285	 * Never attempt single transfers of more than 63k, because
286	 * our count register may be only 16 bits (an OBIO adapter).
287	 * This should never happen since already bounded by minphys().
288	 * XXX - Should just segment these...
289	 */
290	if (xlen > MAX_DMA_LEN) {
291		printf("%s: excessive xlen=0x%x\n", __func__, xlen);
292		Debugger();
293		ncr_sc->sc_datalen = xlen = MAX_DMA_LEN;
294	}
295
296	/* Find free DMA handle.  Guaranteed to find one since we have
297	   as many DMA handles as the driver has processes. */
298	for (i = 0; i < SCI_OPENINGS; i++) {
299		if ((sc->sc_dma[i].dh_flags & SIDH_BUSY) == 0)
300			goto found;
301	}
302	panic("si: no free DMA handles.");
303found:
304
305	dh = &sc->sc_dma[i];
306	dh->dh_flags = SIDH_BUSY;
307
308	if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, addr, xlen, NULL,
309	    BUS_DMA_NOWAIT) != 0)
310		panic("%s: can't load dmamap", device_xname(ncr_sc->sc_dev));
311	dh->dh_dmaaddr = sc->sc_dmap->dm_segs[0].ds_addr;
312	dh->dh_dmalen  = xlen;
313
314	/* Copy the "write" flag for convenience. */
315	if (xs->xs_control & XS_CTL_DATA_OUT)
316		dh->dh_flags |= SIDH_OUT;
317
318	bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, dh->dh_dmalen,
319	    (dh->dh_flags & SIDH_OUT) == 0 ?
320	    BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
321
322#if 0
323	/*
324	 * Some machines might not need to remap B_PHYS buffers.
325	 * The sun3 does not map B_PHYS buffers into DVMA space,
326	 * (they are mapped into normal KV space) so on the sun3
327	 * we must always remap to a DVMA address here. Re-map is
328	 * cheap anyway, because it's done by segments, not pages.
329	 */
330	if (xs->bp && (xs->bp->b_flags & B_PHYS))
331		dh->dh_flags |= SIDH_PHYS;
332#endif
333
334	/* success */
335	sr->sr_dma_hand = dh;
336
337	return;
338}
339
340
341void
342si_dma_free(struct ncr5380_softc *ncr_sc)
343{
344	struct si_softc *sc = (struct si_softc *)ncr_sc;
345	struct sci_req *sr = ncr_sc->sc_current;
346	struct si_dma_handle *dh = sr->sr_dma_hand;
347
348#ifdef	DIAGNOSTIC
349	if (dh == NULL)
350		panic("%s: no DMA handle", __func__);
351#endif
352
353	if (ncr_sc->sc_state & NCR_DOINGDMA)
354		panic("%s: free while in progress", __func__);
355
356	if (dh->dh_flags & SIDH_BUSY) {
357		bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap, 0, dh->dh_dmalen,
358		    (dh->dh_flags & SIDH_OUT) == 0 ?
359		    BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
360		bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap);
361		dh->dh_dmaaddr = 0;
362		dh->dh_flags = 0;
363	}
364	sr->sr_dma_hand = NULL;
365}
366
367
368#define	CSR_MASK (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \
369		SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR)
370#define	POLL_TIMO	50000	/* X100 = 5 sec. */
371
372/*
373 * Poll (spin-wait) for DMA completion.
374 * Called right after xx_dma_start(), and
375 * xx_dma_stop() will be called next.
376 * Same for either VME or OBIO.
377 */
378void
379si_dma_poll(struct ncr5380_softc *ncr_sc)
380{
381	struct si_softc *sc = (struct si_softc *)ncr_sc;
382	struct sci_req *sr = ncr_sc->sc_current;
383	volatile struct si_regs *si = sc->sc_regs;
384	int tmo;
385
386	/* Make sure DMA started successfully. */
387	if (ncr_sc->sc_state & NCR_ABORTING)
388		return;
389
390	/*
391	 * XXX: The Sun driver waits for ~SI_CSR_DMA_ACTIVE here
392	 * XXX: (on obio) or even worse (on vme) a 10mS. delay!
393	 * XXX: I really doubt that is necessary...
394	 */
395
396	/* Wait for any "DMA complete" or error bits. */
397	tmo = POLL_TIMO;
398	for (;;) {
399		if (si->si_csr & CSR_MASK)
400			break;
401		if (--tmo <= 0) {
402			printf("si: DMA timeout (while polling)\n");
403			/* Indicate timeout as MI code would. */
404			sr->sr_flags |= SR_OVERDUE;
405			break;
406		}
407		delay(100);
408	}
409	NCR_TRACE("si_dma_poll: waited %d\n",
410			  POLL_TIMO - tmo);
411
412#ifdef	DEBUG
413	if (si_debug & 2) {
414		printf("%s: done, csr=0x%x\n", __func__, si->si_csr);
415	}
416#endif
417}
418