1/* $NetBSD: vmereg.h,v 1.8 2024/03/10 16:58:08 rillig Exp $ */ 2 3/*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32struct vmebusreg { 33 volatile uint32_t vmebus_cr; /* VMEbus control register */ 34 volatile uint32_t vmebus_afar; /* VMEbus async fault address */ 35 volatile uint32_t vmebus_afsr; /* VMEbus async fault status */ 36}; 37 38/* VME bus Register offsets */ 39#define VMEBUS_CR_REG 0 40#define VMEBUS_AFAR_REG 4 41#define VMEBUS_AFSR_REG 8 42 43/* VME Control Register bits */ 44#define VMEBUS_CR_C 0x80000000 /* I/O cache enable */ 45#define VMEBUS_CR_S 0x40000000 /* VME slave enable */ 46#define VMEBUS_CR_L 0x20000000 /* Loopback enable (diagnostic) */ 47#define VMEBUS_CR_R 0x10000000 /* VMEbus reset */ 48#define VMEBUS_CR_RSVD 0x0ffffff0 /* reserved */ 49#define VMEBUS_CR_IMPL 0x0000000f /* VMEbus interface implementation */ 50#define VMEBUS_CR_BITS "\177\020" \ 51 "f\0\4IMPL\0b\34R\0b\35L\0b\36S\0b\37C\0" 52 53/* VME Asynchronous Fault Status bits */ 54#define VMEBUS_AFSR_SZ 0xe0000000 /* Error transaction size */ 55#define VMEBUS_AFSR_SZ4 0 /* 4 byte */ 56#define VMEBUS_AFSR_SZ1 1 /* 1 byte */ 57#define VMEBUS_AFSR_SZ2 2 /* 2 byte */ 58#define VMEBUS_AFSR_SZ32 5 /* 32 byte */ 59#define VMEBUS_AFSR_TO 0x10000000 /* VME master access time-out */ 60#define VMEBUS_AFSR_BERR 0x08000000 /* VME master got BERR */ 61#define VMEBUS_AFSR_WB 0x04000000 /* IOC write-back error (if SZ == 32) */ 62 /* Non-IOC write error (id SZ != 32) */ 63#define VMEBUS_AFSR_ERR 0x02000000 /* Error summary bit */ 64#define VMEBUS_AFSR_S 0x01000000 /* MVME error in supervisor space */ 65#define VMEBUS_AFSR_ME 0x00800000 /* Multiple error */ 66#define VMEBUS_AFSR_RSVD 0x007fffff /* reserved */ 67#define VMEBUS_AFSR_BITS "\177\020" \ 68 "b\27ME\0b\30S\0b\31ERR\0b\32WB\0b\33BERR\0b\34TO\0f\35\3SZ\0" 69 70struct vmebusvec { 71 volatile uint8_t vmebusvec[16]; 72}; 73 74/* 75 * VME IO-cache definitions. 76 */ 77#define VME_IOC_SIZE 0x8000 78#define VME_IOC_LINESHFT 5 79#define VME_IOC_LINESZ (1 << VME_IOC_LINESHFT) 80 81/* 82 * The VME IO cache lines are selected by bits [13-22] of the DVMA address. 83 * A byte within a cache line is selected by bits [0-4]. The bits in between 84 * (e.g. [5-12]) are used as the cache tag. 85 */ 86#define VME_IOC_IDXSHFT 13 87#define VME_IOC_IDXMASK 0x3ff 88#define VME_IOC_PAGESZ (1 << VME_IOC_IDXSHFT) /* 8192 */ 89#define VME_IOC_LINE_IDX(addr) \ 90 ((((u_long)(addr)) >> VME_IOC_IDXSHFT) & VME_IOC_IDXMASK) 91#define VME_IOC_LINE(addr) (VME_IOC_LINE_IDX(addr) << VME_IOC_LINESHFT) 92 93/* Format of a IO cache tag entry */ 94#define VME_IOC_W 0x00100000 /* Allow writes */ 95#define VME_IOC_IC 0x00200000 /* Line is cacheable */ 96#define VME_IOC_M 0x00400000 /* Line is modified */ 97#define VME_IOC_V 0x00800000 /* Data is valid */ 98#define VME_IOC_TAGMASK 0xff000000 /* Tag (bits <5-12> of DVMA) */ 99#define VME_IOC_BITS "\177\020" \ 100 "b\24W\0b\25IC\0b\26M\0b\27V\0f\30\10TAG\0" 101 102/* 103 * Physical IO-cache addresses. 104 * (expressed as offsets relative to VME vector registers, for want 105 * of something better). 106 */ 107#define VME_IOC_TAGOFFSET 0x0f000000 108#define VME_IOC_DATAOFFSET 0x0f008000 109#define VME_IOC_FLUSHOFFSET 0x0f020000 110