1/* $NetBSD: mmu_sh4.h,v 1.8 2023/04/28 22:31:38 andvar Exp $ */ 2 3/*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#ifndef _SH3_MMU_SH4_H_ 33#define _SH3_MMU_SH4_H_ 34#include <sh3/devreg.h> 35 36/* ITLB 4-entry full-associative UTLB 64-entry full-associative */ 37#define SH4_PTEH 0xff000000 38#define SH4_PTEH_VPN_MASK 0xfffffc00 39#define SH4_PTEH_ASID_MASK 0x000000ff 40#define SH4_PTEL 0xff000004 41#define SH4_PTEL_WT 0x00000001 42#define SH4_PTEL_SH 0x00000002 43#define SH4_PTEL_D 0x00000004 44#define SH4_PTEL_C 0x00000008 45#define SH4_PTEL_PR_SHIFT 5 46#define SH4_PTEL_PR_MASK 0x00000060 /* [5:6] */ 47#define SH4_PTEL_SZ_MASK 0x00000090 /* [4][7] */ 48#define SH4_PTEL_SZ_1K 0x00000000 49#define SH4_PTEL_SZ_4K 0x00000010 50#define SH4_PTEL_SZ_64K 0x00000080 51#define SH4_PTEL_SZ_1M 0x00000090 52#define SH4_PTEL_V 0x00000100 53#define SH4_PTEL_HWBITS 0x1ffff1ff /* [28:12]PFN [8:0]attr. */ 54 55#define SH4_PTEA 0xff000034 56#define SH4_PTEA_SA_MASK 0x00000007 57#define SH4_PTEA_SA_TC 0x00000008 58#define SH4_TTB 0xff000008 59#define SH4_TEA 0xff00000c 60#define SH4_MMUCR 0xff000010 61#define SH4_MMUCR_AT 0x00000001 62#define SH4_MMUCR_TI 0x00000004 63#define SH4_MMUCR_SV 0x00000100 64#define SH4_MMUCR_SQMD 0x00000200 65#define SH4_MMUCR_URC_SHIFT 10 66#define SH4_MMUCR_URC_MASK 0x0000fc00 /* [10:15] */ 67#define SH4_MMUCR_URB_SHIFT 18 68#define SH4_MMUCR_URB_MASK 0x00fc0000 /* [18:23] */ 69#define SH4_MMUCR_LRUI_SHIFT 26 70#define SH4_MMUCR_LRUT_MASK 0xfc000000 /* [26:31] */ 71 72#define SH4_MMUCR_MASK (SH4_MMUCR_LRUT_MASK | SH4_MMUCR_URB_MASK | \ 73 SH4_MMUCR_URC_MASK | SH4_MMUCR_SQMD | SH4_MMUCR_SV | SH4_MMUCR_AT) 74/* 75 * memory-mapped TLB 76 * must be accessed from P2-area program. 77 * branch to the other area must be made at least 8 instructions 78 * after the access. 79 */ 80#define SH4_ITLB_ENTRY 4 81#define SH4_UTLB_ENTRY 64 82 83/* ITLB */ 84#define SH4_ITLB_AA 0xf2000000 85/* address specification (common for address and data array(0,1)) */ 86#define SH4_ITLB_E_SHIFT 8 87#define SH4_ITLB_E_MASK 0x00000300 /* [9:8] */ 88/* data specification */ 89/* address-array */ 90#define SH4_ITLB_AA_ASID_MASK 0x000000ff /* [7:0] */ 91#define SH4_ITLB_AA_V 0x00000100 92#define SH4_ITLB_AA_VPN_SHIFT 10 93#define SH4_ITLB_AA_VPN_MASK 0xfffffc00 /* [31:10] */ 94/* data-array 1 */ 95#define SH4_ITLB_DA1 0xf3000000 96#define SH4_ITLB_DA1_SH 0x00000002 97#define SH4_ITLB_DA1_C 0x00000008 98#define SH4_ITLB_DA1_SZ_MASK 0x00000090 /* [7][4] */ 99#define SH4_ITLB_DA1_SZ_1K 0x00000000 100#define SH4_ITLB_DA1_SZ_4K 0x00000010 101#define SH4_ITLB_DA1_SZ_64K 0x00000080 102#define SH4_ITLB_DA1_SZ_1M 0x00000090 103#define SH4_ITLB_DA1_PR 0x00000040 104#define SH4_ITLB_DA1_V 0x00000100 105#define SH4_ITLB_DA1_PPN_SHIFT 11 106#define SH4_ITLB_DA1_PPN_MASK 0x1ffffc00 /* [28:10] */ 107/* data-array 2 */ 108#define SH4_ITLB_DA2 0xf3800000 109#define SH4_ITLB_DA2_SA_MASK 0x00000003 110#define SH4_ITLB_DA2_TC 0x00000004 111 112/* UTLB */ 113#define SH4_UTLB_AA 0xf6000000 114/* address specification (common for address and data array(0,1)) */ 115#define SH4_UTLB_E_SHIFT 8 116#define SH4_UTLB_E_MASK 0x00003f00 117#define SH4_UTLB_A 0x00000080 118/* data specification */ 119/* address-array */ 120#define SH4_UTLB_AA_VPN_MASK 0xfffffc00 /* [31:10] */ 121#define SH4_UTLB_AA_D 0x00000200 122#define SH4_UTLB_AA_V 0x00000100 123#define SH4_UTLB_AA_ASID_MASK 0x000000ff /* [7:0] */ 124/* data-array 1 */ 125#define SH4_UTLB_DA1 0xf7000000 126#define SH4_UTLB_DA1_WT 0x00000001 127#define SH4_UTLB_DA1_SH 0x00000002 128#define SH4_UTLB_DA1_D 0x00000004 129#define SH4_UTLB_DA1_C 0x00000008 130#define SH4_UTLB_DA1_SZ_MASK 0x00000090 /* [7][4] */ 131#define SH4_UTLB_DA1_SZ_1K 0x00000000 132#define SH4_UTLB_DA1_SZ_4K 0x00000010 133#define SH4_UTLB_DA1_SZ_64K 0x00000080 134#define SH4_UTLB_DA1_SZ_1M 0x00000090 135#define SH4_UTLB_DA1_PR_SHIFT 5 136#define SH4_UTLB_DA1_PR_MASK 0x00000060 137#define SH4_UTLB_DA1_V 0x00000100 138#define SH4_UTLB_DA1_PPN_SHIFT 11 139#define SH4_UTLB_DA1_PPN_MASK 0x1ffffc00 /* [28:10] */ 140/* data-array 2 */ 141#define SH4_UTLB_DA2 0xf7800000 142#define SH4_UTLB_DA2_SA_MASK 0x00000003 143#define SH4_UTLB_DA2_TC 0x00000004 144 145#define SH4_TLB_DISABLE *(volatile uint32_t *)SH4_MMUCR = SH4_MMUCR_TI 146#endif /* !_SH3_MMU_SH4_H_ */ 147