1/* $NetBSD: shpcicvar.h,v 1.8 2011/07/01 19:17:38 dyoung Exp $ */ 2 3/*- 4 * Copyright (C) 2005 NONAKA Kimihiro <nonaka@netbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28#ifndef _SH3_SHPCICVAR_H_ 29#define _SH3_SHPCICVAR_H_ 30 31#include <sys/bus.h> 32 33bus_space_tag_t shpcic_get_bus_io_tag(void); 34bus_space_tag_t shpcic_get_bus_mem_tag(void); 35bus_dma_tag_t shpcic_get_bus_dma_tag(void); 36 37int shpcic_bus_maxdevs(void *v, int busno); 38pcitag_t shpcic_make_tag(void *v, int bus, int device, int function); 39void shpcic_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp); 40pcireg_t shpcic_conf_read(void *v, pcitag_t tag, int reg); 41void shpcic_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data); 42 43int shpcic_set_intr_priority(int intr, int level); 44void *shpcic_intr_establish(int evtcode, int (*ih_func)(void *), void *ih_arg); 45void shpcic_intr_disestablish(void *ih); 46 47/* 48 * shpcic io/mem bus space 49 */ 50int shpcic_iomem_map(void *v, bus_addr_t bpa, bus_size_t size, int flags, 51 bus_space_handle_t *bshp); 52void shpcic_iomem_unmap(void *v, bus_space_handle_t bsh, bus_size_t size); 53int shpcic_iomem_subregion(void *v, bus_space_handle_t bsh, bus_size_t offset, 54 bus_size_t size, bus_space_handle_t *nbshp); 55int shpcic_iomem_alloc(void *v, bus_addr_t rstart, bus_addr_t rend, 56 bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags, 57 bus_addr_t *bpap, bus_space_handle_t *bshp); 58void shpcic_iomem_free(void *v, bus_space_handle_t bsh, bus_size_t size); 59paddr_t shpcic_iomem_mmap(void *v, bus_addr_t addr, off_t off, int prot, 60 int flags); 61 62/* read single */ 63uint8_t shpcic_io_read_1(void *v, bus_space_handle_t bsh, bus_size_t offset); 64uint16_t shpcic_io_read_2(void *v, bus_space_handle_t bsh, bus_size_t offset); 65uint32_t shpcic_io_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset); 66uint8_t shpcic_mem_read_1(void *v, bus_space_handle_t bsh, bus_size_t offset); 67uint16_t shpcic_mem_read_2(void *v, bus_space_handle_t bsh, bus_size_t offset); 68uint32_t shpcic_mem_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset); 69 70/* read multi */ 71void shpcic_io_read_multi_1(void *v, bus_space_handle_t bsh, 72 bus_size_t offset, uint8_t *addr, bus_size_t count); 73void shpcic_io_read_multi_2(void *v, bus_space_handle_t bsh, 74 bus_size_t offset, uint16_t *addr, bus_size_t count); 75void shpcic_io_read_multi_4(void *v, bus_space_handle_t bsh, 76 bus_size_t offset, uint32_t *addr, bus_size_t count); 77void shpcic_mem_read_multi_1(void *v, bus_space_handle_t bsh, 78 bus_size_t offset, uint8_t *addr, bus_size_t count); 79void shpcic_mem_read_multi_2(void *v, bus_space_handle_t bsh, 80 bus_size_t offset, uint16_t *addr, bus_size_t count); 81void shpcic_mem_read_multi_4(void *v, bus_space_handle_t bsh, 82 bus_size_t offset, uint32_t *addr, bus_size_t count); 83 84/* read region */ 85void shpcic_io_read_region_1(void *v, bus_space_handle_t bsh, 86 bus_size_t offset, uint8_t *addr, bus_size_t count); 87void shpcic_io_read_region_2(void *v, bus_space_handle_t bsh, 88 bus_size_t offset, uint16_t *addr, bus_size_t count); 89void shpcic_io_read_region_4(void *v, bus_space_handle_t bsh, 90 bus_size_t offset, uint32_t *addr, bus_size_t count); 91void shpcic_mem_read_region_1(void *v, bus_space_handle_t bsh, 92 bus_size_t offset, uint8_t *addr, bus_size_t count); 93void shpcic_mem_read_region_2(void *v, bus_space_handle_t bsh, 94 bus_size_t offset, uint16_t *addr, bus_size_t count); 95void shpcic_mem_read_region_4(void *v, bus_space_handle_t bsh, 96 bus_size_t offset, uint32_t *addr, bus_size_t count); 97 98/* write single */ 99void shpcic_io_write_1(void *v, bus_space_handle_t bsh, 100 bus_size_t offset, uint8_t data); 101void shpcic_io_write_2(void *v, bus_space_handle_t bsh, 102 bus_size_t offset, uint16_t data); 103void shpcic_io_write_4(void *v, bus_space_handle_t bsh, 104 bus_size_t offset, uint32_t data); 105void shpcic_mem_write_1(void *v, bus_space_handle_t bsh, 106 bus_size_t offset, uint8_t data); 107void shpcic_mem_write_2(void *v, bus_space_handle_t bsh, 108 bus_size_t offset, uint16_t data); 109void shpcic_mem_write_4(void *v, bus_space_handle_t bsh, 110 bus_size_t offset, uint32_t data); 111 112/* write multi */ 113void shpcic_io_write_multi_1(void *v, bus_space_handle_t bsh, 114 bus_size_t offset, const uint8_t *addr, bus_size_t count); 115void shpcic_io_write_multi_2(void *v, bus_space_handle_t bsh, 116 bus_size_t offset, const uint16_t *addr, bus_size_t count); 117void shpcic_io_write_multi_4(void *v, bus_space_handle_t bsh, 118 bus_size_t offset, const uint32_t *addr, bus_size_t count); 119void shpcic_mem_write_multi_1(void *v, bus_space_handle_t bsh, 120 bus_size_t offset, const uint8_t *addr, bus_size_t count); 121void shpcic_mem_write_multi_2(void *v, bus_space_handle_t bsh, 122 bus_size_t offset, const uint16_t *addr, bus_size_t count); 123void shpcic_mem_write_multi_4(void *v, bus_space_handle_t bsh, 124 bus_size_t offset, const uint32_t *addr, bus_size_t count); 125 126/* write region */ 127void shpcic_io_write_region_1(void *v, bus_space_handle_t bsh, 128 bus_size_t offset, const uint8_t *addr, bus_size_t count); 129void shpcic_io_write_region_2(void *v, bus_space_handle_t bsh, 130 bus_size_t offset, const uint16_t *addr, bus_size_t count); 131void shpcic_io_write_region_4(void *v, bus_space_handle_t bsh, 132 bus_size_t offset, const uint32_t *addr, bus_size_t count); 133void shpcic_mem_write_region_1(void *v, bus_space_handle_t bsh, 134 bus_size_t offset, const uint8_t *addr, bus_size_t count); 135void shpcic_mem_write_region_2(void *v, bus_space_handle_t bsh, 136 bus_size_t offset, const uint16_t *addr, bus_size_t count); 137void shpcic_mem_write_region_4(void *v, bus_space_handle_t bsh, 138 bus_size_t offset, const uint32_t *addr, bus_size_t count); 139 140/* set multi */ 141void shpcic_io_set_multi_1(void *v, bus_space_handle_t bsh, 142 bus_size_t offset, uint8_t val, bus_size_t count); 143void shpcic_io_set_multi_2(void *v, bus_space_handle_t bsh, 144 bus_size_t offset, uint16_t val, bus_size_t count); 145void shpcic_io_set_multi_4(void *v, bus_space_handle_t bsh, 146 bus_size_t offset, uint32_t val, bus_size_t count); 147void shpcic_mem_set_multi_1(void *v, bus_space_handle_t bsh, 148 bus_size_t offset, uint8_t val, bus_size_t count); 149void shpcic_mem_set_multi_2(void *v, bus_space_handle_t bsh, 150 bus_size_t offset, uint16_t val, bus_size_t count); 151void shpcic_mem_set_multi_4(void *v, bus_space_handle_t bsh, 152 bus_size_t offset, uint32_t val, bus_size_t count); 153 154/* set region */ 155void shpcic_io_set_region_1(void *v, bus_space_handle_t bsh, 156 bus_size_t offset, uint8_t val, bus_size_t count); 157void shpcic_io_set_region_2(void *v, bus_space_handle_t bsh, 158 bus_size_t offset, uint16_t val, bus_size_t count); 159void shpcic_io_set_region_4(void *v, bus_space_handle_t bsh, 160 bus_size_t offset, uint32_t val, bus_size_t count); 161void shpcic_mem_set_region_1(void *v, bus_space_handle_t bsh, 162 bus_size_t offset, uint8_t val, bus_size_t count); 163void shpcic_mem_set_region_2(void *v, bus_space_handle_t bsh, 164 bus_size_t offset, uint16_t val, bus_size_t count); 165void shpcic_mem_set_region_4(void *v, bus_space_handle_t bsh, 166 bus_size_t offset, uint32_t val, bus_size_t count); 167 168/* copy region */ 169void shpcic_io_copy_region_1(void *v, bus_space_handle_t bsh1, 170 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 171 bus_size_t count); 172void shpcic_io_copy_region_2(void *v, bus_space_handle_t bsh1, 173 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 174 bus_size_t count); 175void shpcic_io_copy_region_4(void *v, bus_space_handle_t bsh1, 176 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 177 bus_size_t count); 178void shpcic_mem_copy_region_1(void *v, bus_space_handle_t bsh1, 179 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 180 bus_size_t count); 181void shpcic_mem_copy_region_2(void *v, bus_space_handle_t bsh1, 182 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 183 bus_size_t count); 184void shpcic_mem_copy_region_4(void *v, bus_space_handle_t bsh1, 185 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 186 bus_size_t count); 187 188#endif /* _SH3_SHPCICVAR_H_ */ 189