pci_mace.c revision 1.15 
1/*	$NetBSD: pci_mace.c,v 1.15 2012/10/27 17:18:10 chs Exp $	*/
2
3/*
4 * Copyright (c) 2001,2003 Christopher Sekiya
5 * Copyright (c) 2000 Soren S. Jorvang
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 *    must display the following acknowledgement:
18 *          This product includes software developed for the
19 *          NetBSD Project.  See http://www.NetBSD.org/ for
20 *          information about NetBSD.
21 * 4. The name of the author may not be used to endorse or promote products
22 *    derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36#include <sys/cdefs.h>
37__KERNEL_RCSID(0, "$NetBSD: pci_mace.c,v 1.15 2012/10/27 17:18:10 chs Exp $");
38
39#include "opt_pci.h"
40#include "pci.h"
41
42#include <sys/param.h>
43#include <sys/device.h>
44#include <sys/systm.h>
45
46#include <machine/cpu.h>
47#include <machine/locore.h>
48#include <machine/autoconf.h>
49#include <machine/vmparam.h>
50#include <sys/bus.h>
51#include <machine/machtype.h>
52
53#include <mips/cache.h>
54
55#include <dev/pci/pcivar.h>
56#include <dev/pci/pcireg.h>
57#include <dev/pci/pcidevs.h>
58
59#include <sys/extent.h>
60#include <sys/malloc.h>
61#include <dev/pci/pciconf.h>
62
63#include <sgimips/mace/macereg.h>
64#include <sgimips/mace/macevar.h>
65
66#include <sgimips/mace/pcireg_mace.h>
67
68struct macepci_softc {
69	struct sgimips_pci_chipset sc_pc;
70};
71
72static int	macepci_match(device_t, cfdata_t, void *);
73static void	macepci_attach(device_t, device_t, void *);
74static int	macepci_bus_maxdevs(pci_chipset_tag_t, int);
75static pcireg_t	macepci_conf_read(pci_chipset_tag_t, pcitag_t, int);
76static void	macepci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t);
77static int	macepci_intr_map(const struct pci_attach_args *,
78		    pci_intr_handle_t *);
79static const char *
80		macepci_intr_string(pci_chipset_tag_t, pci_intr_handle_t);
81static int	macepci_intr(void *);
82
83CFATTACH_DECL_NEW(macepci, sizeof(struct macepci_softc),
84    macepci_match, macepci_attach, NULL, NULL);
85
86static int
87macepci_match(device_t parent, cfdata_t match, void *aux)
88{
89
90	return (1);
91}
92
93static void
94macepci_attach(device_t parent, device_t self, void *aux)
95{
96	struct macepci_softc *sc = device_private(self);
97	pci_chipset_tag_t pc = &sc->sc_pc;
98	struct mace_attach_args *maa = aux;
99	struct pcibus_attach_args pba;
100	u_int32_t control;
101	int rev;
102
103	if (bus_space_subregion(maa->maa_st, maa->maa_sh,
104	    maa->maa_offset, 0, &pc->ioh) )
105		panic("macepci_attach: couldn't map");
106
107	pc->iot = maa->maa_st;
108
109	rev = bus_space_read_4(pc->iot, pc->ioh, MACEPCI_REVISION);
110	printf(": rev %d\n", rev);
111
112	pc->pc_bus_maxdevs = macepci_bus_maxdevs;
113	pc->pc_conf_read = macepci_conf_read;
114	pc->pc_conf_write = macepci_conf_write;
115	pc->pc_intr_map = macepci_intr_map;
116	pc->pc_intr_string = macepci_intr_string;
117	pc->intr_establish = mace_intr_establish;
118	pc->intr_disestablish = mace_intr_disestablish;
119
120	bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_ERROR_ADDR, 0);
121	bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_ERROR_FLAGS, 0);
122
123	/* Turn on PCI error interrupts */
124	bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONTROL,
125	    MACE_PCI_CONTROL_SERR_ENA |
126	    MACE_PCI_CONTROL_PARITY_ERR |
127	    MACE_PCI_CONTROL_PARK_LIU |
128	    MACE_PCI_CONTROL_OVERRUN_INT |
129	    MACE_PCI_CONTROL_PARITY_INT |
130	    MACE_PCI_CONTROL_SERR_INT |
131	    MACE_PCI_CONTROL_IT_INT |
132	    MACE_PCI_CONTROL_RE_INT |
133	    MACE_PCI_CONTROL_DPED_INT |
134	    MACE_PCI_CONTROL_TAR_INT |
135	    MACE_PCI_CONTROL_MAR_INT);
136
137	/*
138	 * Enable all MACE PCI interrupts. They will be masked by
139	 * the CRIME code.
140	 */
141	control = bus_space_read_4(pc->iot, pc->ioh, MACEPCI_CONTROL);
142	control |= CONTROL_INT_MASK;
143	bus_space_write_4(pc->iot, pc->ioh, MACEPCI_CONTROL, control);
144
145#if NPCI > 0
146	pc->pc_ioext = extent_create("macepciio", 0x00001000, 0x01ffffff,
147	    NULL, 0, EX_NOWAIT);
148	pc->pc_memext = extent_create("macepcimem", 0x80100000, 0x81ffffff,
149	    NULL, 0, EX_NOWAIT);
150	pci_configure_bus(pc, pc->pc_ioext, pc->pc_memext, NULL, 0,
151	    mips_cache_info.mci_dcache_align);
152	memset(&pba, 0, sizeof pba);
153/*XXX*/	pba.pba_iot = SGIMIPS_BUS_SPACE_IO;
154/*XXX*/	pba.pba_memt = SGIMIPS_BUS_SPACE_MEM;
155	pba.pba_dmat = &pci_bus_dma_tag;
156	pba.pba_dmat64 = NULL;
157	pba.pba_bus = 0;
158	pba.pba_bridgetag = NULL;
159	pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY |
160	    PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY;
161	pba.pba_pc = pc;
162
163#ifdef MACEPCI_IO_WAS_BUGGY
164	if (rev == 0)
165		pba.pba_flags &= ~PCI_FLAGS_IO_OKAY;		/* Buggy? */
166#endif
167
168	cpu_intr_establish(maa->maa_intr, IPL_NONE, macepci_intr, sc);
169
170	config_found_ia(self, "pcibus", &pba, pcibusprint);
171#endif
172}
173
174int
175macepci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
176{
177
178	if (busno == 0)
179		return 5;	/* 2 on-board SCSI chips, slots 0, 1 and 2 */
180	else
181		return 0;	/* XXX */
182}
183
184pcireg_t
185macepci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
186{
187	pcireg_t data;
188
189	bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, (tag | reg));
190	data = bus_space_read_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_DATA);
191	bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, 0);
192
193	return data;
194}
195
196void
197macepci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
198{
199	/* XXX O2 soren */
200	if (tag == 0)
201		return;
202
203	bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, (tag | reg));
204	bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_DATA, data);
205	bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, 0);
206}
207
208int
209macepci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
210{
211	pci_chipset_tag_t pc = pa->pa_pc;
212	pcitag_t intrtag = pa->pa_intrtag;
213	int pin = pa->pa_intrpin;
214	int bus, dev, func, start;
215
216	pci_decompose_tag(pc, intrtag, &bus, &dev, &func);
217
218	if (dev < 3 && pin != PCI_INTERRUPT_PIN_A)
219		panic("SCSI0 and SCSI1 must be hardwired!");
220
221	switch (pin) {
222	default:
223	case PCI_INTERRUPT_PIN_NONE:
224		return -1;
225
226	case PCI_INTERRUPT_PIN_A:
227		/*
228		 * Each of SCSI{0,1}, & slots 0 - 2 has dedicated interrupt
229		 * for pin A?
230		 */
231		*ihp = dev + 7;
232		return 0;
233
234	case PCI_INTERRUPT_PIN_B:
235		start = 0;
236		break;
237	case PCI_INTERRUPT_PIN_C:
238		start = 1;
239		break;
240	case PCI_INTERRUPT_PIN_D:
241		start = 2;
242		break;
243	}
244
245	/* Pins B,C,D are mapped to PCI_SHARED0 - PCI_SHARED2 interrupts */
246	*ihp = 13 /* PCI_SHARED0 */ + (start + dev - 3) % 3;
247	return 0;
248}
249
250const char *
251macepci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih)
252{
253	static char irqstr[32];
254
255	sprintf(irqstr, "crime interrupt %d", ih);
256	return irqstr;
257}
258
259
260/*
261 * Handle PCI error interrupts.
262 */
263int
264macepci_intr(void *arg)
265{
266	struct macepci_softc *sc = (struct macepci_softc *)arg;
267	pci_chipset_tag_t pc = &sc->sc_pc;
268	u_int32_t error, address;
269
270	error = bus_space_read_4(pc->iot, pc->ioh, MACE_PCI_ERROR_FLAGS);
271	address = bus_space_read_4(pc->iot, pc->ioh, MACE_PCI_ERROR_ADDR);
272	while (error & 0xffc00000) {
273		if (error & MACE_PERR_MASTER_ABORT) {
274			/*
275			 * this seems to be a more-or-less normal error
276			 * condition (e.g., "pcictl pci0 list" generates
277			 * a _lot_ of these errors, so no message for now
278			 * while I figure out if I missed a trick somewhere.
279			 */
280			error &= ~MACE_PERR_MASTER_ABORT;
281			bus_space_write_4(pc->iot, pc->ioh,
282			    MACE_PCI_ERROR_FLAGS, error);
283		}
284
285		if (error & MACE_PERR_TARGET_ABORT) {
286			printf("mace: target abort at %x\n", address);
287			error &= ~MACE_PERR_TARGET_ABORT;
288			bus_space_write_4(pc->iot, pc->ioh,
289			    MACE_PCI_ERROR_FLAGS, error);
290		}
291
292		if (error & MACE_PERR_DATA_PARITY_ERR) {
293			printf("mace: parity error at %x\n", address);
294			error &= ~MACE_PERR_DATA_PARITY_ERR;
295			bus_space_write_4(pc->iot, pc->ioh,
296			    MACE_PCI_ERROR_FLAGS, error);
297		}
298
299		if (error & MACE_PERR_RETRY_ERR) {
300			printf("mace: retry error at %x\n", address);
301			error &= ~MACE_PERR_RETRY_ERR;
302			bus_space_write_4(pc->iot, pc->ioh,
303			    MACE_PCI_ERROR_FLAGS, error);
304		}
305
306		if (error & MACE_PERR_ILLEGAL_CMD) {
307			printf("mace: illegal command at %x\n", address);
308			error &= ~MACE_PERR_ILLEGAL_CMD;
309			bus_space_write_4(pc->iot, pc->ioh,
310			    MACE_PCI_ERROR_FLAGS, error);
311		}
312
313		if (error & MACE_PERR_SYSTEM_ERR) {
314			printf("mace: system error at %x\n", address);
315			error &= ~MACE_PERR_SYSTEM_ERR;
316			bus_space_write_4(pc->iot, pc->ioh,
317			    MACE_PCI_ERROR_FLAGS, error);
318		}
319
320		if (error & MACE_PERR_INTERRUPT_TEST) {
321			printf("mace: interrupt test at %x\n", address);
322			error &= ~MACE_PERR_INTERRUPT_TEST;
323			bus_space_write_4(pc->iot, pc->ioh,
324			    MACE_PCI_ERROR_FLAGS, error);
325		}
326
327		if (error & MACE_PERR_PARITY_ERR) {
328			printf("mace: parity error at %x\n", address);
329			error &= ~MACE_PERR_PARITY_ERR;
330			bus_space_write_4(pc->iot, pc->ioh,
331			    MACE_PCI_ERROR_FLAGS, error);
332		}
333
334		if (error & MACE_PERR_RSVD) {
335			printf("mace: reserved condition at %x\n", address);
336			error &= ~MACE_PERR_RSVD;
337			bus_space_write_4(pc->iot, pc->ioh,
338			    MACE_PCI_ERROR_FLAGS, error);
339		}
340
341		if (error & MACE_PERR_OVERRUN) {
342			printf("mace: overrun at %x\n", address);
343			error &= ~MACE_PERR_OVERRUN;
344			bus_space_write_4(pc->iot, pc->ioh,
345			    MACE_PCI_ERROR_FLAGS, error);
346		}
347	}
348	return 0;
349}
350