1/* $NetBSD: spr.h,v 1.7 2020/07/06 10:31:23 rin Exp $ */ 2 3#ifndef _POWERPC_OEA_SPR_H_ 4#define _POWERPC_OEA_SPR_H_ 5 6#if !defined(_LOCORE) && defined(_KERNEL) 7 8#ifdef _KERNEL_OPT 9#include "opt_ppcarch.h" 10#endif 11 12#if defined(PPC_OEA64_BRIDGE) || defined (_ARCH_PPC64) 13#include <powerpc/psl.h> 14#include <powerpc/spr.h> 15#endif 16 17#endif /* !_LOCORE && _KERNEL */ 18 19/* 20 * Special Purpose Register declarations. 21 * 22 * The first column in the comments indicates which PowerPC architectures the 23 * SPR is valid on - E for BookE series, 4 for 4xx series, 24 * 6 for 6xx/7xx series and 8 for 8xx (but not most 8xxx) series. 25 */ 26 27#define SPR_MQ 0x000 /* ..6. 601 MQ register */ 28#define SPR_RTCU_R 0x004 /* ..6. 601 RTC Upper - Read */ 29#define SPR_RTCL_R 0x005 /* ..6. 601 RTC Lower - Read */ 30#define SPR_DSISR 0x012 /* ..68 DSI exception source */ 31#define DSISR_DIRECT 0x80000000 /* Direct-store error exception */ 32#define DSISR_NOTFOUND 0x40000000 /* Translation not found */ 33#define DSISR_PROTECT 0x08000000 /* Memory access not permitted */ 34#define DSISR_INVRX 0x04000000 /* Reserve-indexed insn direct-store access */ 35#define DSISR_STORE 0x02000000 /* Store operation */ 36#define DSISR_DABR 0x00400000 /* DABR match */ 37#define DSISR_SEGMENT 0x00200000 /* XXX; not in 6xx PEM */ 38#define DSISR_EAR 0x00100000 /* eciwx/ecowx && EAR[E] == 0 */ 39#define SPR_DAR 0x013 /* ..68 Data Address Register */ 40#define SPR_RTCU_W 0x014 /* ..6. 601 RTC Upper - Write */ 41#define SPR_RTCL_W 0x015 /* ..6. 601 RTC Lower - Write */ 42#define SPR_SDR1 0x019 /* ..68 Page table base address register */ 43#define SPR_VRSAVE 0x100 /* ..6. AltiVec VRSAVE */ 44#define SPR_SCOMC 0x114 /* .... SCOM Control Register (970) */ 45#define SPR_SCOMD 0x115 /* .... SCOM Data Register (970) */ 46#define SCOM_PCR 0x0aa00100 /* Power Control Register */ 47#define SCOM_PCR_BIT 0x80000000 /* Data bit */ 48#define SCOM_PSR 0x40800100 /* Power Status Register */ 49#define PSR_RECEIVED (1ULL << 61) 50#define PSR_COMPLETED (1ULL << 60) 51#define SCOMC_READ 0x00008000 52#define SCOMC_WRITE 0x00000000 53#define SPR_ASR 0x118 /* ..6. Address Space Register (PPC64) */ 54#define SPR_EAR 0x11a /* ..68 External Access Register */ 55#define MPC601 0x0001 56#define MPC603 0x0003 57#define MPC604 0x0004 58#define MPC602 0x0005 59#define MPC603e 0x0006 60#define MPC603ev 0x0007 61#define MPC750 0x0008 62#define MPC604e 0x0009 63#define MPC604ev 0x000a 64#define MPC7400 0x000c 65#define MPC620 0x0014 66#define IBMRS64II 0x0033 67#define IBMRS64IIIp 0x0034 68#define IBMPOWER4 0x0035 69#define IBMRS64IIIi 0x0036 70#define IBMRS64IV 0x0037 71#define IBMPOWER4II 0x0038 72#define IBM970 0x0039 73#define IBMPOWER5GR 0x003a 74#define IBMPOWER5GS 0x003b 75#define IBM970FX 0x003c 76#define IBMPOWER6 0x003e 77#define IBMPOWER3 0x0040 78#define IBMPOWER3II 0x0041 79#define IBM970MP 0x0044 80#define IBM970GX 0x0045 81#define IBMCELL 0x0070 82#define MPC8240 0x0081 83#define PA6T 0x0090 84#define IBMPOWER6P5 0x0f00 85#define IBMSTB25 0x5151 86#define IBM750FX 0x7000 87#define IBM750GX 0x7002 88#define MPC7450 0x8000 89#define MPC7455 0x8001 90#define MPC7457 0x8002 91#define MPC7447A 0x8003 92#define MPC7448 0x8004 93#define MPC745X_P(v) ((v & 0xFFF8) == 0x8000) 94#define MPC7410 0x800c 95#define MPC5200 0x8011 96#define MPC8245 0x8081 97#define MPCG2 0x8082 98#define MPCe300c1 0x8083 99#define MPCe300c2 0x8084 100#define MPCe300c3 0x8085 101#define SPR_HIOR 0x137 /* .... HW Interrupt Offset (970) */ 102 103#define SPR_IBAT0U 0x210 /* ..68 Instruction BAT Reg 0 Upper */ 104#define SPR_IBAT0L 0x211 /* ..6. Instruction BAT Reg 0 Lower */ 105#define SPR_IBAT1U 0x212 /* ..6. Instruction BAT Reg 1 Upper */ 106#define SPR_IBAT1L 0x213 /* ..6. Instruction BAT Reg 1 Lower */ 107#define SPR_IBAT2U 0x214 /* ..6. Instruction BAT Reg 2 Upper */ 108#define SPR_IBAT2L 0x215 /* ..6. Instruction BAT Reg 2 Lower */ 109#define SPR_IBAT3U 0x216 /* ..6. Instruction BAT Reg 3 Upper */ 110#define SPR_IBAT3L 0x217 /* ..6. Instruction BAT Reg 3 Lower */ 111#define SPR_DBAT0U 0x218 /* ..6. Data BAT Reg 0 Upper */ 112#define SPR_DBAT0L 0x219 /* ..6. Data BAT Reg 0 Lower */ 113#define SPR_DBAT1U 0x21a /* ..6. Data BAT Reg 1 Upper */ 114#define SPR_DBAT1L 0x21b /* ..6. Data BAT Reg 1 Lower */ 115#define SPR_DBAT2U 0x21c /* ..6. Data BAT Reg 2 Upper */ 116#define SPR_DBAT2L 0x21d /* ..6. Data BAT Reg 2 Lower */ 117#define SPR_DBAT3U 0x21e /* ..6. Data BAT Reg 3 Upper */ 118#define SPR_DBAT3L 0x21f /* ..6. Data BAT Reg 3 Lower */ 119#define SPR_IBAT4U 0x230 /* ..6. Instruction BAT Reg 4 Upper */ 120#define SPR_IBAT4L 0x231 /* ..6. Instruction BAT Reg 4 Lower */ 121#define SPR_IBAT5U 0x232 /* ..6. Instruction BAT Reg 5 Upper */ 122#define SPR_IBAT5L 0x233 /* ..6. Instruction BAT Reg 5 Lower */ 123#define SPR_IBAT6U 0x234 /* ..6. Instruction BAT Reg 6 Upper */ 124#define SPR_IBAT6L 0x235 /* ..6. Instruction BAT Reg 6 Lower */ 125#define SPR_IBAT7U 0x236 /* ..6. Instruction BAT Reg 7 Upper */ 126#define SPR_IBAT7L 0x237 /* ..6. Instruction BAT Reg 7 Lower */ 127#define SPR_DBAT4U 0x238 /* ..6. Data BAT Reg 4 Upper */ 128#define SPR_DBAT4L 0x239 /* ..6. Data BAT Reg 4 Lower */ 129#define SPR_DBAT5U 0x23a /* ..6. Data BAT Reg 5 Upper */ 130#define SPR_DBAT5L 0x23b /* ..6. Data BAT Reg 5 Lower */ 131#define SPR_DBAT6U 0x23c /* ..6. Data BAT Reg 6 Upper */ 132#define SPR_DBAT6L 0x23d /* ..6. Data BAT Reg 6 Lower */ 133#define SPR_DBAT7U 0x23e /* ..6. Data BAT Reg 7 Upper */ 134#define SPR_DBAT7L 0x23f /* ..6. Data BAT Reg 7 Upper */ 135#define SPR_UMMCR2 0x3a0 /* ..6. User Monitor Mode Control Register 2 */ 136#define SPR_UMMCR0 0x3a8 /* ..6. User Monitor Mode Control Register 0 */ 137#define SPR_USIA 0x3ab /* ..6. User Sampled Instruction Address */ 138#define SPR_UMMCR1 0x3ac /* ..6. User Monitor Mode Control Register 1 */ 139#define SPR_MMCR2 0x3b0 /* ..6. Monitor Mode Control Register 2 */ 140#define SPR_MMCR2_THRESHMULT_32 0x80000000 /* Multiply MMCR0 threshold by 32 */ 141#define SPR_MMCR2_THRESHMULT_2 0x00000000 /* Multiply MMCR0 threshold by 2 */ 142#define SPR_PMC5 0x3b1 /* ..6. Performance Counter Register 5 */ 143#define SPR_PMC6 0x3b2 /* ..6. Performance Counter Register 6 */ 144 145#define SPR_MMCR0 0x3b8 /* ..6. Monitor Mode Control Register 0 */ 146#define MMCR0_FC 0x80000000 /* Freeze counters */ 147#define MMCR0_FCS 0x40000000 /* Freeze counters in supervisor mode */ 148#define MMCR0_FCP 0x20000000 /* Freeze counters in user mode */ 149#define MMCR0_FCM1 0x10000000 /* Freeze counters when mark=1 */ 150#define MMCR0_FCM0 0x08000000 /* Freeze counters when mark=0 */ 151#define MMCR0_PMXE 0x04000000 /* Enable PM interrupt */ 152#define MMCR0_FCECE 0x02000000 /* Freeze counters after event */ 153#define MMCR0_TBSEL_15 0x01800000 /* Count bit 15 of TBL */ 154#define MMCR0_TBSEL_19 0x01000000 /* Count bit 19 of TBL */ 155#define MMCR0_TBSEL_23 0x00800000 /* Count bit 23 of TBL */ 156#define MMCR0_TBSEL_31 0x00000000 /* Count bit 31 of TBL */ 157#define MMCR0_TBEE 0x00400000 /* Time-base event enable */ 158#define MMCRO_THRESHOLD(x) ((x) << 16) /* Threshold value */ 159#define MMCR0_PMC1CE 0x00008000 /* PMC1 condition enable */ 160#define MMCR0_PMCNCE 0x00004000 /* PMCn condition enable */ 161#define MMCR0_TRIGGER 0x00002000 /* Trigger */ 162#define MMCR0_PMC1SEL(x) ((x) << 6) /* PMC1 selector */ 163#define MMCR0_PMC2SEL(x) ((x) << 0) /* PMC2 selector */ 164#define SPR_PMC1 0x3b9 /* ..6. Performance Counter Register 1 */ 165#define SPR_PMC2 0x3ba /* ..6. Performance Counter Register 2 */ 166#define SPR_SIA 0x3bb /* ..6. Sampled Instruction Address */ 167#define SPR_MMCR1 0x3bc /* ..6. Monitor Mode Control Register 2 */ 168#define MMCR1_PMC3SEL(x) ((x) << 27) /* PMC 3 selector */ 169#define MMCR1_PMC4SEL(x) ((x) << 22) /* PMC 4 selector */ 170#define MMCR1_PMC5SEL(x) ((x) << 17) /* PMC 5 selector */ 171#define MMCR1_PMC6SEL(x) ((x) << 11) /* PMC 6 selector */ 172 173#define SPR_PMC3 0x3bd /* ..6. Performance Counter Register 3 */ 174#define SPR_PMC4 0x3be /* ..6. Performance Counter Register 4 */ 175#define SPR_DMISS 0x3d0 /* ..68 Data TLB Miss Address Register */ 176#define SPR_DCMP 0x3d1 /* ..68 Data TLB Compare Register */ 177#define SPR_HASH1 0x3d2 /* ..68 Primary Hash Address Register */ 178#define SPR_HASH2 0x3d3 /* ..68 Secondary Hash Address Register */ 179#define SPR_IMISS 0x3d4 /* ..68 Instruction TLB Miss Address Register */ 180#define SPR_TLBMISS 0x3d4 /* ..6. TLB Miss Address Register */ 181#define SPR_ICMP 0x3d5 /* ..68 Instruction TLB Compare Register */ 182#define SPR_PTEHI 0x3d5 /* ..6. Instruction TLB Compare Register */ 183#define SPR_RPA 0x3d6 /* ..68 Required Physical Address Register */ 184#define SPR_PTELO 0x3d6 /* ..6. Required Physical Address Register */ 185#define SPR_HID0 0x3f0 /* E.68 Hardware Implementation Register 186 0 */ 187#define SPR_HID1 0x3f1 /* E.68 Hardware Implementation Register 188 1 */ 189#define SPR_HID4 0x3f4 /* ..6. 970 HID4 */ 190#define SPR_HID5 0x3f6 /* ..6. 970 HID5 */ 191#define SPR_DABR 0x3f5 /* ..6. Data Address Breakpoint Register */ 192#define SPR_MSSCR0 0x3f6 /* ..6. Memory SubSystem Control Register */ 193#define MSSCR0_SHDEN 0x80000000 /* 0: Shared-state enable */ 194#define MSSCR0_SHDPEN3 0x40000000 /* 1: ~SHD[01] signal enable in MEI mode */ 195#define MSSCR0_L1INTVEN 0x38000000 /* 2-4: L1 data cache ~HIT intervention enable */ 196#define MSSCR0_L2INTVEN 0x07000000 /* 5-7: L2 data cache ~HIT intervention enable */ 197#define MSSCR0_DL1HWF 0x00800000 /* 8: L1 data cache hardware flush */ 198#define MSSCR0_MBO 0x00400000 /* 9: must be one */ 199#define MSSCR0_EMODE 0x00200000 /* 10: MPX bus mode (read-only) */ 200#define MSSCR0_ABD 0x00100000 /* 11: address bus driven (read-only) */ 201#define MSSCR0_BMODE 0x0000c000 /* 16-17: Bus Mode (read-only) (7450) */ 202#define MSSCR0_ID 0x00000040 /* 26: Processor ID */ 203#define MSSCR0_L2PFE 0x00000003 /* 30-31: L2 prefetching enabled (7450) */ 204#define SPR_L2PM 0x3f8 /* ..6. L2 Private Memory Control Register */ 205#define SPR_L2CR 0x3f9 /* ..6. L2 Control Register */ 206#define L2CR_L2E 0x80000000 /* 0: L2 enable */ 207#define L2CR_L2PE 0x40000000 /* 1: L2 data parity enable */ 208#define L2CR_L2SIZ 0x30000000 /* 2-3: L2 size */ 209#define L2SIZ_2M 0x00000000 210#define L2SIZ_256K 0x10000000 211#define L2SIZ_512K 0x20000000 212#define L2SIZ_1M 0x30000000 213#define L2CR_L2CLK 0x0e000000 /* 4-6: L2 clock ratio */ 214#define L2CLK_DIS 0x00000000 /* disable L2 clock */ 215#define L2CLK_10 0x02000000 /* core clock / 1 */ 216#define L2CLK_15 0x04000000 /* / 1.5 */ 217#define L2CLK_35 0x06000000 /* / 3.5 */ 218#define L2CLK_20 0x08000000 /* / 2 */ 219#define L2CLK_25 0x0a000000 /* / 2.5 */ 220#define L2CLK_30 0x0c000000 /* / 3 */ 221#define L2CLK_40 0x0e000000 /* / 4 */ 222#define L2CR_L2RAM 0x01800000 /* 7-8: L2 RAM type */ 223#define L2RAM_FLOWTHRU_BURST 0x00000000 224#define L2RAM_PIPELINE_BURST 0x01000000 225#define L2RAM_PIPELINE_LATE 0x01800000 226#define L2CR_L2DO 0x00400000 /* 9: L2 data-only. 227 Setting this bit disables instruction 228 caching. */ 229#define L2CR_L2I 0x00200000 /* 10: L2 global invalidate. */ 230#define L2CR_L2CTL 0x00100000 /* 11: L2 RAM control (ZZ enable). 231 Enables automatic operation of the 232 L2ZZ (low-power mode) signal. */ 233#define L2CR_L2WT 0x00080000 /* 12: L2 write-through. */ 234#define L2CR_L2TS 0x00040000 /* 13: L2 test support. */ 235#define L2CR_L2OH 0x00030000 /* 14-15: L2 output hold. */ 236#define L2CR_L2SL 0x00008000 /* 16: L2 DLL slow. */ 237#define L2CR_L2DF 0x00004000 /* 17: L2 differential clock. */ 238#define L2CR_L2BYP 0x00002000 /* 18: L2 DLL bypass. */ 239#define L2CR_L2FA 0x00001000 /* 19: L2 flush assist (for software flush). */ 240#define L2CR_L2HWF 0x00000800 /* 20: L2 hardware flush. */ 241#define L2CR_L2IO 0x00000400 /* 21: L2 instruction-only. */ 242#define L2CR_L2CLKSTP 0x00000200 /* 22: L2 clock stop. */ 243#define L2CR_L2DRO 0x00000100 /* 23: L2DLL rollover checkstop enable. */ 244#define L2CR_L2IP 0x00000001 /* 31: L2 global invalidate in */ 245 /* progress (read only). */ 246#define SPR_L3CR 0x3fa /* ..6. L3 Control Register */ 247#define L3CR_RESERVED 0x0438003a /* Reserved bits in L3CR */ 248#define L3CR_L3E 0x80000000 /* 0: L3 enable */ 249#define L3CR_L3PE 0x40000000 /* 1: L3 data parity checking enable */ 250#define L3CR_L3APE 0x20000000 /* 2: L3 address parity checking enable */ 251#define L3CR_L3SIZ 0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */ 252#define L3SIZ_1M 0x00000000 253#define L3SIZ_2M 0x10000000 254#define L3CR_L3CLKEN 0x08000000 /* 4: Enables the L3_CLK[0:1] signals */ 255#define L3CR_L3CLK 0x03800000 /* 6-8: L3 clock ratio */ 256#define L3CLK_60 0x00000000 /* core clock / 6 */ 257#define L3CLK_20 0x01000000 /* / 2 */ 258#define L3CLK_25 0x01800000 /* / 2.5 */ 259#define L3CLK_30 0x02000000 /* / 3 */ 260#define L3CLK_35 0x02800000 /* / 3.5 */ 261#define L3CLK_40 0x03000000 /* / 4 */ 262#define L3CLK_50 0x03800000 /* / 5 */ 263#define L3CR_L3IO 0x00400000 /* 9: L3 instruction-only mode */ 264#define L3CR_L3SPO 0x00040000 /* 13: L3 sample point override */ 265#define L3CR_L3CKSP 0x00030000 /* 14-15: L3 clock sample point */ 266#define L3CKSP_2 0x00000000 /* 2 clocks */ 267#define L3CKSP_3 0x00010000 /* 3 clocks */ 268#define L3CKSP_4 0x00020000 /* 4 clocks */ 269#define L3CKSP_5 0x00030000 /* 5 clocks */ 270#define L3CR_L3PSP 0x0000e000 /* 16-18: L3 P-clock sample point */ 271#define L3PSP_0 0x00000000 /* 0 clocks */ 272#define L3PSP_1 0x00002000 /* 1 clocks */ 273#define L3PSP_2 0x00004000 /* 2 clocks */ 274#define L3PSP_3 0x00006000 /* 3 clocks */ 275#define L3PSP_4 0x00008000 /* 4 clocks */ 276#define L3PSP_5 0x0000a000 /* 5 clocks */ 277#define L3CR_L3REP 0x00001000 /* 19: L3 replacement algorithm (0=default, 1=alternate) */ 278#define L3CR_L3HWF 0x00000800 /* 20: L3 hardware flush */ 279#define L3CR_L3I 0x00000400 /* 21: L3 global invalidate */ 280#define L3CR_L3RT 0x00000300 /* 22-23: L3 SRAM type */ 281#define L3RT_MSUG2_DDR 0x00000000 /* MSUG2 DDR SRAM */ 282#define L3RT_PIPELINE_LATE 0x00000100 /* Pipelined (register-register) synchronous late-write SRAM */ 283#define L3RT_PB2_SRAM 0x00000300 /* PB2 SRAM */ 284#define L3CR_L3NIRCA 0x00000080 /* 24: L3 non-integer ratios clock adjustment for the SRAM */ 285#define L3CR_L3DO 0x00000040 /* 25: L3 data-only mode */ 286#define L3CR_PMEN 0x00000004 /* 29: Private memory enable */ 287#define L3CR_PMSIZ 0x00000004 /* 31: Private memory size (0=1MB, 1=2MB) */ 288#define SPR_ICTC 0x3fb /* ..6. instruction cache throttling */ 289#define ICTC_ENABLE 0x00000001 /* enable throttling */ 290#define ICTC_COUNT_M 0x000001fe /* number of waits to insert */ 291#define SPR_THRM1 0x3fc /* ..6. Thermal Management Register */ 292#define SPR_THRM2 0x3fd /* ..6. Thermal Management Register */ 293#define SPR_THRM_TIN 0x80000000 /* Thermal interrupt bit (RO) */ 294#define SPR_THRM_TIV 0x40000000 /* Thermal interrupt valid (RO) */ 295#define SPR_THRM_THRESHOLD(x) ((x) << 23) /* Thermal sensor threshold */ 296#define SPR_THRM_TID 0x00000004 /* Thermal interrupt direction */ 297#define SPR_THRM_TIE 0x00000002 /* Thermal interrupt enable */ 298#define SPR_THRM_VALID 0x00000001 /* Valid bit */ 299#define SPR_THRM3 0x3fe /* ..6. Thermal Management Register */ 300#define SPR_THRM_TIMER(x) ((x) << 1) /* Sampling interval timer */ 301#define SPR_THRM_ENABLE 0x00000001 /* TAU Enable */ 302#define SPR_FPECR 0x3fe /* ..6. Floating-Point Exception Cause Register */ 303#define SPR_PIR 0x3ff /* ..6. Processor Identification Register */ 304 305/* Performance counter declarations */ 306#define PMC_OVERFLOW 0x80000000 /* Counter has overflowed */ 307 308/* The first five countable [non-]events are common to all the PMC's */ 309#define PMCN_NONE 0 /* Count nothing */ 310#define PMCN_CYCLES 1 /* Processor cycles */ 311#define PMCN_ICOMP 2 /* Instructions completed */ 312#define PMCN_TBLTRANS 3 /* TBL bit transitions */ 313#define PCMN_IDISPATCH 4 /* Instructions dispatched */ 314 315#if !defined(_LOCORE) && defined(_KERNEL) 316 317#if defined(PPC_OEA64_BRIDGE) || defined (_ARCH_PPC64) 318 319static inline uint64_t 320scom_read(register_t address) 321{ 322 register_t msr; 323 uint64_t ret; 324 325 msr = mfmsr(); 326 mtmsr(msr & ~PSL_EE); 327 __asm volatile("isync;"); 328 329 mtspr(SPR_SCOMC, address | SCOMC_READ); 330 __asm volatile("isync;"); 331 332 ret = mfspr(SPR_SCOMD); 333 mtmsr(msr); 334 __asm volatile("isync;"); 335 336 return ret; 337} 338 339static inline void 340scom_write(register_t address, uint64_t data) 341{ 342 register_t msr; 343 344 msr = mfmsr(); 345 mtmsr(msr & ~PSL_EE); 346 __asm volatile("isync;"); 347 348 mtspr(SPR_SCOMD, data); 349 __asm volatile("isync;"); 350 mtspr(SPR_SCOMC, address | SCOMC_WRITE); 351 __asm volatile("isync;"); 352 353 mtmsr(msr); 354 __asm volatile("isync;"); 355} 356 357#endif /* defined(PPC_OEA64_BRIDGE) || defined (_ARCH_PPC64) */ 358 359#endif /* !defined(_LOCORE) && defined(_KERNEL) */ 360 361#endif /* !_POWERPC_SPR_H_ */ 362