1/*	$NetBSD: fpu_div.c,v 1.9 2022/09/06 23:04:08 rin Exp $ */
2
3/*
4 * Copyright (c) 1992, 1993
5 *	The Regents of the University of California.  All rights reserved.
6 *
7 * This software was developed by the Computer Systems Engineering group
8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
9 * contributed to Berkeley.
10 *
11 * All advertising materials mentioning features or use of this software
12 * must display the following acknowledgement:
13 *	This product includes software developed by the University of
14 *	California, Lawrence Berkeley Laboratory.
15 *
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted provided that the following conditions
18 * are met:
19 * 1. Redistributions of source code must retain the above copyright
20 *    notice, this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright
22 *    notice, this list of conditions and the following disclaimer in the
23 *    documentation and/or other materials provided with the distribution.
24 * 3. Neither the name of the University nor the names of its contributors
25 *    may be used to endorse or promote products derived from this software
26 *    without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
39 *
40 *	@(#)fpu_div.c	8.1 (Berkeley) 6/11/93
41 */
42
43/*
44 * Perform an FPU divide (return x / y).
45 */
46
47#include <sys/cdefs.h>
48__KERNEL_RCSID(0, "$NetBSD: fpu_div.c,v 1.9 2022/09/06 23:04:08 rin Exp $");
49
50#include <sys/types.h>
51#if defined(DIAGNOSTIC)||defined(DEBUG)
52#include <sys/systm.h>
53#endif
54
55#include <machine/fpu.h>
56#include <machine/reg.h>
57
58#include <powerpc/fpu/fpu_arith.h>
59#include <powerpc/fpu/fpu_emu.h>
60
61/*
62 * Division of normal numbers is done as follows:
63 *
64 * x and y are floating point numbers, i.e., in the form 1.bbbb * 2^e.
65 * If X and Y are the mantissas (1.bbbb's), the quotient is then:
66 *
67 *	q = (X / Y) * 2^((x exponent) - (y exponent))
68 *
69 * Since X and Y are both in [1.0,2.0), the quotient's mantissa (X / Y)
70 * will be in [0.5,2.0).  Moreover, it will be less than 1.0 if and only
71 * if X < Y.  In that case, it will have to be shifted left one bit to
72 * become a normal number, and the exponent decremented.  Thus, the
73 * desired exponent is:
74 *
75 *	left_shift = x->fp_mant < y->fp_mant;
76 *	result_exp = x->fp_exp - y->fp_exp - left_shift;
77 *
78 * The quotient mantissa X/Y can then be computed one bit at a time
79 * using the following algorithm:
80 *
81 *	Q = 0;			-- Initial quotient.
82 *	R = X;			-- Initial remainder,
83 *	if (left_shift)		--   but fixed up in advance.
84 *		R *= 2;
85 *	for (bit = FP_NMANT; --bit >= 0; R *= 2) {
86 *		if (R >= Y) {
87 *			Q |= 1 << bit;
88 *			R -= Y;
89 *		}
90 *	}
91 *
92 * The subtraction R -= Y always removes the uppermost bit from R (and
93 * can sometimes remove additional lower-order 1 bits); this proof is
94 * left to the reader.
95 *
96 * This loop correctly calculates the guard and round bits since they are
97 * included in the expanded internal representation.  The sticky bit
98 * is to be set if and only if any other bits beyond guard and round
99 * would be set.  From the above it is obvious that this is true if and
100 * only if the remainder R is nonzero when the loop terminates.
101 *
102 * Examining the loop above, we can see that the quotient Q is built
103 * one bit at a time ``from the top down''.  This means that we can
104 * dispense with the multi-word arithmetic and just build it one word
105 * at a time, writing each result word when it is done.
106 *
107 * Furthermore, since X and Y are both in [1.0,2.0), we know that,
108 * initially, R >= Y.  (Recall that, if X < Y, R is set to X * 2 and
109 * is therefore at in [2.0,4.0).)  Thus Q is sure to have bit FP_NMANT-1
110 * set, and R can be set initially to either X - Y (when X >= Y) or
111 * 2X - Y (when X < Y).  In addition, comparing R and Y is difficult,
112 * so we will simply calculate R - Y and see if that underflows.
113 * This leads to the following revised version of the algorithm:
114 *
115 *	R = X;
116 *	bit = FP_1;
117 *	D = R - Y;
118 *	if (D >= 0) {
119 *		result_exp = x->fp_exp - y->fp_exp;
120 *		R = D;
121 *		q = bit;
122 *		bit >>= 1;
123 *	} else {
124 *		result_exp = x->fp_exp - y->fp_exp - 1;
125 *		q = 0;
126 *	}
127 *	R <<= 1;
128 *	do  {
129 *		D = R - Y;
130 *		if (D >= 0) {
131 *			q |= bit;
132 *			R = D;
133 *		}
134 *		R <<= 1;
135 *	} while ((bit >>= 1) != 0);
136 *	Q[0] = q;
137 *	for (i = 1; i < 4; i++) {
138 *		q = 0, bit = 1 << 31;
139 *		do {
140 *			D = R - Y;
141 *			if (D >= 0) {
142 *				q |= bit;
143 *				R = D;
144 *			}
145 *			R <<= 1;
146 *		} while ((bit >>= 1) != 0);
147 *		Q[i] = q;
148 *	}
149 *
150 * This can be refined just a bit further by moving the `R <<= 1'
151 * calculations to the front of the do-loops and eliding the first one.
152 * The process can be terminated immediately whenever R becomes 0, but
153 * this is relatively rare, and we do not bother.
154 */
155
156struct fpn *
157fpu_div(struct fpemu *fe)
158{
159	struct fpn *x = &fe->fe_f1, *y = &fe->fe_f2;
160	u_int q, bit;
161	u_int r0, r1, r2, r3, d0, d1, d2, d3, y0, y1, y2, y3;
162	FPU_DECL_CARRY
163
164	/*
165	 * Since divide is not commutative, we cannot just use ORDER.
166	 * Check either operand for NaN first; if there is at least one,
167	 * order the signalling one (if only one) onto the right, then
168	 * return it.  Otherwise we have the following cases:
169	 *
170	 *	Inf / Inf = NaN, plus NV exception
171	 *	Inf / num = Inf [i.e., return x]
172	 *	Inf / 0   = Inf [i.e., return x]
173	 *	0 / Inf = 0 [i.e., return x]
174	 *	0 / num = 0 [i.e., return x]
175	 *	0 / 0   = NaN, plus NV exception
176	 *	num / Inf = 0
177	 *	num / num = num (do the divide)
178	 *	num / 0   = Inf, plus DZ exception
179	 */
180	DPRINTF(FPE_REG, ("fpu_div:\n"));
181	DUMPFPN(FPE_REG, x);
182	DUMPFPN(FPE_REG, y);
183	DPRINTF(FPE_REG, ("=>\n"));
184	if (ISNAN(x) || ISNAN(y)) {
185		if (ISSNAN(x) || ISSNAN(y))
186			fe->fe_cx |= FPSCR_VXSNAN;
187		if (ISNAN(x))
188			y = x;
189		DUMPFPN(FPE_REG, y);
190		return (y);
191	}
192	/*
193	 * Need to split the following out cause they generate different
194	 * exceptions.
195	 */
196	if (ISINF(x)) {
197		if (x->fp_class == y->fp_class) {
198			fe->fe_cx |= FPSCR_VXIDI;
199			return (fpu_newnan(fe));
200		}
201		DUMPFPN(FPE_REG, x);
202		return (x);
203	}
204	if (ISZERO(x)) {
205		if (x->fp_class == y->fp_class) {
206			fe->fe_cx |= FPSCR_VXZDZ;
207			return (fpu_newnan(fe));
208		}
209		DUMPFPN(FPE_REG, x);
210		return (x);
211	}
212
213	/* all results at this point use XOR of operand signs */
214	x->fp_sign ^= y->fp_sign;
215	if (ISINF(y)) {
216		x->fp_class = FPC_ZERO;
217		DUMPFPN(FPE_REG, x);
218		return (x);
219	}
220	if (ISZERO(y)) {
221		fe->fe_cx = FPSCR_ZX;
222		x->fp_class = FPC_INF;
223		DUMPFPN(FPE_REG, x);
224		return (x);
225	}
226
227	/*
228	 * Macros for the divide.  See comments at top for algorithm.
229	 * Note that we expand R, D, and Y here.
230	 */
231
232#define	SUBTRACT		/* D = R - Y */ \
233	FPU_SUBS(d3, r3, y3); FPU_SUBCS(d2, r2, y2); \
234	FPU_SUBCS(d1, r1, y1); FPU_SUBC(d0, r0, y0)
235
236#define	NONNEGATIVE		/* D >= 0 */ \
237	((int)d0 >= 0)
238
239#ifdef FPU_SHL1_BY_ADD
240#define	SHL1			/* R <<= 1 */ \
241	FPU_ADDS(r3, r3, r3); FPU_ADDCS(r2, r2, r2); \
242	FPU_ADDCS(r1, r1, r1); FPU_ADDC(r0, r0, r0)
243#else
244#define	SHL1 \
245	r0 = (r0 << 1) | (r1 >> 31), r1 = (r1 << 1) | (r2 >> 31), \
246	r2 = (r2 << 1) | (r3 >> 31), r3 <<= 1
247#endif
248
249#define	LOOP			/* do ... while (bit >>= 1) */ \
250	do { \
251		SHL1; \
252		SUBTRACT; \
253		if (NONNEGATIVE) { \
254			q |= bit; \
255			r0 = d0, r1 = d1, r2 = d2, r3 = d3; \
256		} \
257	} while ((bit >>= 1) != 0)
258
259#define	WORD(r, i)			/* calculate r->fp_mant[i] */ \
260	q = 0; \
261	bit = 1 << 31; \
262	LOOP; \
263	(x)->fp_mant[i] = q
264
265	/* Setup.  Note that we put our result in x. */
266	r0 = x->fp_mant[0];
267	r1 = x->fp_mant[1];
268	r2 = x->fp_mant[2];
269	r3 = x->fp_mant[3];
270	y0 = y->fp_mant[0];
271	y1 = y->fp_mant[1];
272	y2 = y->fp_mant[2];
273	y3 = y->fp_mant[3];
274
275	bit = FP_1;
276	SUBTRACT;
277	if (NONNEGATIVE) {
278		x->fp_exp -= y->fp_exp;
279		r0 = d0, r1 = d1, r2 = d2, r3 = d3;
280		q = bit;
281		bit >>= 1;
282	} else {
283		x->fp_exp -= y->fp_exp + 1;
284		q = 0;
285	}
286	LOOP;
287	x->fp_mant[0] = q;
288	WORD(x, 1);
289	WORD(x, 2);
290	WORD(x, 3);
291	x->fp_sticky = r0 | r1 | r2 | r3;
292
293	DUMPFPN(FPE_REG, x);
294	return (x);
295}
296