1/*	$NetBSD: rtciic.c,v 1.5 2021/08/07 16:19:00 thorpej Exp $	*/
2/*
3 * Copyright (c) 2011 KIYOHARA Takashi
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 *
27 */
28#include <sys/cdefs.h>
29__KERNEL_RCSID(0, "$NetBSD: rtciic.c,v 1.5 2021/08/07 16:19:00 thorpej Exp $");
30
31#include <sys/param.h>
32#include <sys/bus.h>
33#include <sys/device.h>
34#include <sys/errno.h>
35
36#include <machine/autoconf.h>
37
38#include <dev/i2c/i2cvar.h>
39#include <dev/i2c/i2c_bitbang.h>
40
41#include "locators.h"
42
43#ifdef RTCIIC_DEBUG
44#define DPRINTF(x) printf x
45#else
46#define DPRINTF(x)
47#endif
48
49#define RTCIIC_SDAR	(1 << 3)	/* received serial data */
50#define RTCIIC_SDAW	(1 << 2)	/* sended serial data */
51#define RTCIIC_SCL	(1 << 1)	/* serial clock */
52#define RTCIIC_RW	(1 << 0)	/* data direction (0:write, 1:read) */
53
54/* This device is Big Endian */
55#define RTCIIC_READ(sc) \
56	bswap16(bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, 0))
57#define RTCIIC_WRITE(sc, val) \
58	bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, 0, bswap16(val))
59
60struct rtciic_softc {
61	device_t sc_dev;
62
63	bus_space_tag_t sc_iot;
64	bus_space_handle_t sc_ioh;
65
66	struct i2c_controller sc_i2c;
67	struct i2c_bitbang_ops sc_bops;
68
69	int sc_rw;
70};
71
72static int rtciic_match(device_t, cfdata_t , void *);
73static void rtciic_attach(device_t, device_t, void *);
74
75static int rtciic_send_start(void *, int);
76static int rtciic_send_stop(void *, int);
77static int rtciic_initiate_xfer(void *, i2c_addr_t, int);
78static int rtciic_read_byte(void *, uint8_t *, int);
79static int rtciic_write_byte(void *, uint8_t, int);
80
81static void rtciic_set_dir(void *, uint32_t);
82static void rtciic_set_bits(void *, uint32_t);
83static uint32_t rtciic_read_bits(void *);
84
85CFATTACH_DECL_NEW(rtciic, sizeof(struct rtciic_softc),
86    rtciic_match, rtciic_attach, NULL, NULL);
87
88static int
89rtciic_match(device_t parent, cfdata_t match, void *aux)
90{
91	struct mainbus_attach_args *ma = aux;
92
93	if (strcmp(ma->ma_name, match->cf_name) != 0)
94		return 0;
95
96	/* Disallow wildcarded values. */
97	if (ma->ma_addr1 == MAINBUSCF_ADDR1_DEFAULT)
98		return 0;
99
100	/* no irq */
101	if (ma->ma_irq1 != MAINBUSCF_IRQ1_DEFAULT)
102		return 0;
103
104	return 1;
105}
106
107void
108rtciic_attach(device_t parent, device_t self, void *aux)
109{
110	struct rtciic_softc *sc = device_private(self);
111	struct mainbus_attach_args *ma = aux;
112	struct i2cbus_attach_args iba;
113
114	sc->sc_dev = self;
115
116	aprint_normal("\n");
117	aprint_naive("\n");
118
119	/* Map I/O space(16bit). */
120	sc->sc_iot = 0;
121	if (bus_space_map(sc->sc_iot, ma->ma_addr1, 2, 0, &sc->sc_ioh)) {
122		aprint_error_dev(self, "can't map registers\n");
123		return;
124	}
125	sc->sc_rw = RTCIIC_READ(sc) & RTCIIC_RW;
126
127	/* register with iic */
128	iic_tag_init(&sc->sc_i2c);
129	sc->sc_i2c.ic_cookie = sc;
130	sc->sc_i2c.ic_send_start = rtciic_send_start;
131	sc->sc_i2c.ic_send_stop = rtciic_send_stop;
132	sc->sc_i2c.ic_initiate_xfer = rtciic_initiate_xfer;
133	sc->sc_i2c.ic_read_byte = rtciic_read_byte;
134	sc->sc_i2c.ic_write_byte = rtciic_write_byte;
135
136	sc->sc_bops.ibo_set_dir = rtciic_set_dir;
137	sc->sc_bops.ibo_set_bits = rtciic_set_bits;
138	sc->sc_bops.ibo_read_bits = rtciic_read_bits;
139	sc->sc_bops.ibo_bits[I2C_BIT_SDA] = RTCIIC_SDAW;
140	sc->sc_bops.ibo_bits[I2C_BIT_SCL] = RTCIIC_SCL;
141	sc->sc_bops.ibo_bits[I2C_BIT_OUTPUT] = 0;
142	sc->sc_bops.ibo_bits[I2C_BIT_INPUT] = RTCIIC_RW;
143
144	memset(&iba, 0, sizeof(iba));
145	iba.iba_tag = &sc->sc_i2c;
146	config_found(sc->sc_dev, &iba, iicbus_print, CFARGS_NONE);
147}
148
149static int
150rtciic_send_start(void *arg, int flags)
151{
152	struct rtciic_softc *sc = arg;
153
154	return i2c_bitbang_send_start(sc, flags, &sc->sc_bops);
155}
156
157static int
158rtciic_send_stop(void *arg, int flags)
159{
160	struct rtciic_softc *sc = arg;
161
162	return i2c_bitbang_send_stop(sc, flags, &sc->sc_bops);
163}
164
165static int
166rtciic_initiate_xfer(void *arg, i2c_addr_t addr, int flags)
167{
168	struct rtciic_softc *sc = arg;
169
170	return i2c_bitbang_initiate_xfer(sc, addr, flags, &sc->sc_bops);
171}
172
173static int
174rtciic_read_byte(void *arg, uint8_t *vp, int flags)
175{
176	struct rtciic_softc *sc = arg;
177
178	return i2c_bitbang_read_byte(sc, vp, flags, &sc->sc_bops);
179}
180
181static int
182rtciic_write_byte(void *arg, uint8_t v, int flags)
183{
184	struct rtciic_softc *sc = arg;
185
186	return i2c_bitbang_write_byte(sc, v, flags, &sc->sc_bops);
187}
188
189
190static void
191rtciic_set_dir(void *arg, uint32_t bits)
192{
193	struct rtciic_softc *sc = arg;
194	uint16_t reg;
195
196	DPRINTF(("%s: set dir %s\n",
197	    device_xname(sc->sc_dev), (bits & RTCIIC_RW) ? "READ" : "WRITE"));
198
199	if (sc->sc_rw != (bits & RTCIIC_RW)) {
200		reg = RTCIIC_READ(sc);
201		reg &= ~RTCIIC_RW;
202		reg |= bits;
203		RTCIIC_WRITE(sc, reg);
204		delay(30);
205		sc->sc_rw = bits & RTCIIC_RW;
206	}
207}
208
209static void
210rtciic_set_bits(void *arg, uint32_t bits)
211{
212	struct rtciic_softc *sc = arg;
213
214	DPRINTF(("%s: %s\n",
215	    device_xname(sc->sc_dev),
216	    (bits == (RTCIIC_SDAW | RTCIIC_SCL)) ? "set SDA/SCL" :
217	    ((bits == RTCIIC_SDAW) ? "set SDA" :
218	    ((bits == RTCIIC_SCL) ? "set SCL" : "reset"))));
219
220	if (sc->sc_rw & RTCIIC_RW) {
221		bits &= RTCIIC_SCL;
222		bits |= RTCIIC_RW;
223	}
224	RTCIIC_WRITE(sc, bits);
225	delay(40);
226}
227
228static uint32_t
229rtciic_read_bits(void *arg)
230{
231	struct rtciic_softc *sc = arg;
232	uint8_t rv, v;
233
234	v = RTCIIC_READ(sc);
235	rv = v & RTCIIC_SCL;
236	if (v & RTCIIC_SDAR)
237		rv |= RTCIIC_SDAW;
238
239	DPRINTF(("%s: read %s\n",
240	    device_xname(sc->sc_dev),
241	    (rv == (RTCIIC_SDAW | RTCIIC_SCL)) ? "SDA/SCL" :
242	    ((rv == RTCIIC_SDAW) ? "SDA" :
243	    ((rv == RTCIIC_SCL) ? "SCL" : "no"))));
244
245	return (uint32_t)rv;
246}
247