1/*	$NetBSD: ingenic_var.h,v 1.6 2017/05/21 06:49:13 skrll Exp $ */
2
3/*-
4 * Copyright (c) 2014 Michael Lorenz
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef INGENIC_VAR_H
30#define INGENIC_VAR_H
31
32#include <sys/bus.h>
33
34struct apbus_attach_args {
35	const char	*aa_name;
36	bus_space_tag_t	aa_bst;
37	bus_dma_tag_t	aa_dmat;
38	bus_addr_t	aa_addr;
39	uint32_t	aa_irq;
40	uint32_t	aa_pclk;	/* PCLK in kHz */
41	uint32_t	aa_mclk;	/* MCLK in kHz */
42	uint32_t	aa_clockreg;
43};
44
45extern bus_space_tag_t ingenic_memt;
46void apbus_init(void);
47
48uint32_t mips_cp0_corectrl_read(void);
49uint32_t mips_cp0_corestatus_read(void);
50uint32_t mips_cp0_corereim_read(void);
51uint32_t mips_cp0_corembox_read(u_int);
52
53void mips_cp0_corectrl_write(uint32_t);
54void mips_cp0_corestatus_write(uint32_t);
55void mips_cp0_corereim_write(uint32_t);
56void mips_cp0_corembox_write(u_int, uint32_t);
57
58#endif /* INGENIC_VAR_H */
59